You are on page 1of 20

TC7106

TC7106A
1
TC7107
TC7107A

3-1/2 DIGIT A/D CONVERTERS


FEATURES GENERAL DESCRIPTION 2
■ Internal Reference with Low Temperature Drift The TC7106A and TC7107A 3-1/2 digit direct-display
TC7106/7 ....................................... 80ppm/°C Typical drive analog-to-digital converters allow existing 7106/7107
TC7106A/7A .................................. 20ppm/°C Typical based systems to be upgraded. Each device has a preci-
■ Drives LCD (TC7106) or LED (TC7107) Display sion reference with a 20ppm/°C max temperature coeffi-
Directly cient. This represents a 4 to 7 times improvement over
■ Guaranteed Zero Reading With Zero Input similar 3-1/2 digit converters. Existing 7106 and 7107 based
■ Low Noise for Stable Display
■ Auto-Zero Cycle Eliminates Need for Zero
Adjustment
systems may be upgraded without changing external pas-
sive component values. The TC7107A drives common 3
■ True Polarity Indication for Precision Null anode light emitting diode (LED) displays directly with 8mA
Applications per segment. A low-cost, high-resolution indicating meter
■ Convenient 9 V Battery Operation (TC7106A) requires only a display, four resistors, and four capacitors.
■ High Impedance CMOS Differential Inputs .... 1012Ω The TC7106A low power drain and 9V battery operation
■ Differential Reference Inputs Simplify Ratiometric make it suitable for portable applications.
Measurements The TC7106A/TC7107A reduces linearity error to less
■ Low Power Operation ..................................... 10mW than 1 count. Rollover error – the difference in readings for
equal magnitude but opposite polarity input signals – is
4
ORDERING INFORMATION below ±1 count. High impedance differential inputs offer
PART CODE TC710X X X XXX 1pA leakage current and a 1012Ω input impedance. The
differential reference input allows ratiometric measurements
6 = LCD
7 = LED } for ohms or bridge transducer measurements. The
15µVP–P noise performance guarantees a “rock solid” read-
A or blank* ing. The auto-zero cycle guarantees a zero display read-

R (reversed pins) or blank (CPL pkg only)


ing with a zero-volts input.
5
* "A" parts have an improved reference TC
Package Code (see below): 0.1µF
LCD DISPLAY (TC7106/A) OR
34 33 COMMON ANODE LED
+ DISPLAY (TC7107/A)
C REF C– REF
Package Temperature +
1MΩ
31
V+ 2–19 SEGMENT
IN 22–25 DRIVE
Code Package Pin Layout Range ANALOG
INPUT
0.01µF
20

6
30 –
V IN POL
– MINUS SIGN BACKPLANE
CKW 44-Pin PQFP Formed Leads 0°C to +70°C 21 DRIVE
ANALOG BP
32
CLW 44-Pin PLCC — 0°C to +70°C COMMON V+
1

CPL 40-Pin PDIP Normal 0°C to +70°C 24kΩ


28 V TC7106/A +
IPL 40-Pin PDIP Normal – 25°C to +85°C BUFF
TC7107/A 9V
47kΩ VREF
V+ 36 1kΩ
IJL 40-Pin CerDIP Normal – 25°C to +85°C 0.47µF
CAZ
REF
29 V–
REF
35 100mV
0.22µF
AVAILABLE PACKAGES 27
VINT V
– 26

OSC2 OSC3 OSC1


TO ANALOG
39 38 COSC 40

R OSC 100pF

100kΩ
COMMON (PIN 32)

3 CONVERSIONS/SEC
200mV FULL SCALE
7
40-Pin Plastic DIP 40-Pin CERDIP
Figure 1. TC7106/A/7/A Typical Operating Circuit

44-Pin Plastic Quad Flat


Package Formed Leads
44-Pin Plastic Chip
Carrier PLCC
TC7106/6A/7/7A-7 11/4/96
8
TELCOM SEMICONDUCTOR, INC. 3-183
3-1/2 DIGIT A/D CONVERTERS
TC7106
TC7106A
TC7107
TC7107A

ABSOLUTE MAXIMUM RATINGS* Analog Input Voltage (either input) (Note 1) ......... V+ to V–
Reference Input Voltage (either input) ................. V+ to V–
TC7106A Clock Input ....................................................... GND to V+
Supply Voltage (V+ to V–) ........................................... 15 V Power Dissipation (Note 2) (TA ≤ 70°C)
Analog Input Voltage (either input) (Note 1) ......... V+ to V– 40-Pin CerDIP Package ...................................2.29W
Reference Input Voltage (either input) ................. V+ to V– 40-Pin Plastic DIP ............................................. 1.23W
Clock Input ........................................................ Test to V+ 44-Pin PLCC .....................................................1.23W
Package Power Dissipation (Note 2) (TA ≤ 70°C) 44-Pin PQFP .................................................... 1.00W
CerDIP ..............................................................2.29W Operating Temperature
Plastic DIP ........................................................1.23W “C” Devices ............................................ 0°C to +70°C
PLCC ................................................................1.23W “I” Devices ........................................ – 25°C to +85°C
PQFP ................................................................1.00W Storage Temperature ............................ – 65°C to +150°C
Operating Temperature Lead Temperature (Soldering, 10 sec) ................. +300°C
“C” Devices ............................................ 0°C to +70°C
“I” Devices ........................................ – 25°C to +85°C *Static-sensitive device. Unused devices must be stored in conductive
Storage Temperature ............................ – 65°C to +150°C material. Protect devices from static discharge and static fields. Stresses
above those listed under Absolute Maximum Ratings may cause perma-
Lead Temperature (Soldering, 60 sec) ................... 300°C
nent damage to the device. These are stress ratings only and functional
TC7107A operation of the device at these or any other conditions above those
Supply Voltage indicated in the operational sections of the specifications is not implied.
Exposure to Absolute Maximum Rating Conditions for extended periods
V+ ................................................................................................ +6 V may affect device reliability.
V– ............................................................................................... – 9 V

ELECTRICAL CHARACTERISTICS (Note 3)


TC7106/A & TC7107/A
Parameters Test Conditions Min Typ Max Unit
Zero Input Reading VIN = 0.0 V – 000.0 ±000.0 +000.0 Digital
Full-Scale = 200.0mV Reading
Ratiometric Reading VIN = VREF 999 999/1000 1000 Digital
VREF = 100 mV Reading
Roll-Over Error (Difference in –
VIN = +V+IN ≅ 200mV –1 ±0.2 +1 Counts
Reading for Equal Positive and
Negative Reading Near Full-Scale)
Linearity (Max. Deviation From Full-Scale = 200mV –1 ±0.2 +1 Counts
Best Straight Line Fit) or Full-Scale = 2.000 V
Common-Mode VCM = ±1V, VIN = 0V, — 50 — µV/V
Rejection Ratio (Note 4) Full Scale = 200.0 mV
Noise (Pk – Pk Value Not VIN = 0 V — 15 — µV
Exceeded 95% of Time) Full-Scale = 200.0mV
Leakage Current @ Input VIN = 0 V — 1 10 pA
Zero Reading Drift VIN = 0 V
“C” Device = 0°C to +70°C — 0.2 1 µV/°C
VIN = 0 V
“I” Device = – 25°C to +85°C — 1.0 2 µV/°C
Scale Factor VIN = 199.0mV,
Temperature Coefficient “C” Device = 0°C to +70°C — 1 5 ppm/°C
(Ext. Ref = 0ppm°C)
VIN = 199.0mV — — 20 ppm/°C
“I” Device = – 25°C to +85°C
Supply Current (Does Not VIN = 0 — 0.8 1.8 mA
Include LED Current For TC7107/A)

3-184 TELCOM SEMICONDUCTOR, INC.


3-1/2 DIGIT A/D CONVERTERS
TC7106
TC7106A
1
TC7107
TC7107A

ELECTRICAL CHARACTERISTICS (Cont.) (Note 3)

Parameters Test Conditions


TC7106/A & TC7107/A
Min Typ Max Unit
2
Analog Common Voltage 25kΩ Between Common 2.7 3.05 3.35 V
(With Respect to Pos. Supply) and Pos. Supply
Temp. Coeff. of 25kΩ Between Common
Analog Common and Pos. Supply
(With Respect 0°C ≤ TA ≤ +70°C 7106A/7A 20 50 ppm/°C
to Pos. Supply) ("C", Commercial Temp. Range Devices) 7106/7 80 — ppm/°C
Temp. Coeff. of
Analog Common
25kΩ Between Common
and Pos. Supply
3
(With Respect – 25°C ≤ TA ≤ 85°C — — 75 ppm/°C
to Pos. Supply) (“I,” Industrial Temp. Range Devices)
TC7106A ONLY Pk – Pk V+ to V– = 9V 4 5 6 V
Segment Drive Voltage (Note 5)
TC7106A ONLY Pk – Pk V+ to V– = 9V 4 5 6 V
Backplane Drive Voltage (Note 5)
TC7107A ONLY
Segment Sinking Current (Except Pin 19)
V+ = 5.0V
Segment Voltage = 3V
5 8.0 — mA
4
TC7107A ONLY V+ = 5.0V 10 16 — mA
Segment Sinking Current (Pin 19) Segment Voltage = 3V
NOTES: 1. Input voltages may exceed the supply voltages provided the input current is limited to ±100µA.
2. Dissipation rating assumes device is mounted with all leads soldered to printed circuit board.
3. Unless otherwise noted, specifications apply to both the TC7106/A and TC7107/A at TA = 25°C, fCLOCK = 48 kHz. Parts are tested in the
circuit of Figure 1.
4. Refer to “Differential Input” discussion.
5. Backplane drive is in phase with segment drive for “OFF” segment, 180° out of phase for “ON” segment. Frequency is 20 times
conversion rate. Average DC component is less than 50mV.
5

8
TELCOM SEMICONDUCTOR, INC. 3-185
3-1/2 DIGIT A/D CONVERTERS
TC7106
TC7106A
TC7107
TC7107A

PIN CONFIGURATIONS

V+ 1 40 OSC 1 OSC 1 1 40 V +
NORMAL PIN REVERSE PIN
D1 2 CONFIGURATION 39 OSC 2 OSC 2 2 CONFIGURATION 39 D1
C1 3 38 OSC 3 OSC 3 3 38 C1
B1 4 37 TEST TEST 4 37 B 1
+ +
1's A1 5 36 V REF V REF 5 36 A 1 1's
F1 – –
VREF F1
6 35 VREF 6 35
+ +
CREF
G1 7 34 CREF 7 34 G1
– –
CREF
E1 8 33 CREF 8 33 E 1
9 32 ANALOG ANALOG 9 32 D2
D2 COMMON
COMMON
+ +
V IN
C2 10 31 V IN 10 31 C2
B 2 11 TC7106ACPL 30 V –
IN V– IN 11 TC7106AIJL 30 B 2
10's TC7107AIPL TC7107AIJL 10's
A 2 12 29 CAZ CAZ 12 29 A 2
F2 13 28 VBUFF VBUFF 13 28 F2
E 2 14 27 V INT V INT 14 27 E 2
D3 15 26 V – V – 15 26 D3
B 3 16 25 G G 2 16 25 B 3
2
100's 100's
F3 17 24 C 3 C 3 17 24 F3
100's 100's
E 3 18 23 A 3 A 3 18 23 E 3
1000's AB 4 19 22 G 3 G 3 19 22 AB 4 1000's
POL 20 21 BP/GND BP/GND 20 21 POL
(MINUS SIGN) (7106A/7107A) (7106A/7107A) (MINUS SIGN)
REF LO
REF HI

REF HI
OSC1

OSC2

OSC3

CREF

CREF

IN LO

BUFF
TEST

COM

IN HI

INT
A/Z
NC
C1

D1

V+
A1

B1

V–
6 5 4 3 2 1 44 43 42 41 40 44 43 42 41 40 39 38 37 36 35 34

F1 7 39 REF LO NC 1 33 NC

G1 8 38 CREF NC 2 32 G2

E1 9 37 CREF TEST 3 31 C3

D2 10 36 COMMON OSC3 4 30 A3

C2 11 35 IN HI NC 5 29 G3

NC 12 TC7106ACLW 34 NC OSC2 6 TC7106ACKW 28 BP/GND


TC7107ACLW TC7107ACKW
B2 13 33 IN LO OSC1 7 27 POL
(PLCC) (FLAT PACKAGE)
A2 14 32 A/Z V+ 8 26 AB4

F2 15 31 BUFF D1 9 25 E3

E2 16 30 INT C1 10 24 F3

D3 17 29 V– B1 11 23 B3

18 19 20 21 22 23 24 25 26 27 28 12 13 14 15 16 17 18 19 20 21 22
B3

F3

E3

AB4

POL

NC

BP/GND

G3

A3

C3

G2

A1

F1

G1

E1

D2

C2

B2

A2

F2

E2

D3

3-186 TELCOM SEMICONDUCTOR, INC.


3-1/2 DIGIT A/D CONVERTERS
TC7106
TC7106A
1
TC7107
TC7107A

PIN DESCRIPTION
Pin No.
40-Pin PDIP
Pin No.
40-Pin PDIP
2
(Normal) (Reverse) Symbol Description
1 (40) V+ Positive supply voltage.
2 (39) D1 Activates the D section of the units display.
3 (38) C1 Activates the C section of the units display.
4 (37) B1 Activates the B section of the units display.
5
6
(36)
(35)
A1
F1
Activates the A section of the units display.
Activates the F section of the units display.
3
7 (34) G1 Activates the G section of the units display.
8 (33) E1 Activates the E section of the units display.
9 (32) D2 Activates the D section of the tens display.
10 (31) C2 Activates the C section of the tens display.
11 (30) B2 Activates the B section of the tens display.
12
13
(29)
(28)
A2
F2
Activates the A section of the tens display.
Activates the F section of the tens display. 4
14 (27) E2 Activates the E section of the tens display.
15 (26) D3 Activates the D section of the hundreds display.
16 (25) B3 Activates the B section of the hundreds display.
17 (24) F3 Activates the F section of the hundreds display.
18 (23) E3 Activates the E section of the hundreds display.
19
20
21
(22)
(21)
(20)
AB4
POL
BP
Activates both halves of the 1 in the thousands display.
Activates the negative polarity display.
LCD Backplane drive output (TC7106A).
5
GND Digital ground (TC7107A).
22 (19) G3 Activates the G section of the hundreds display.
23 (18) A3 Activates the A section of the hundreds display.
24 (17) C3 Activates the C section of the hundreds display.
25 (16) G2 Activates the G section of the tens display.
26
27
(15)
(14)
V–
VINT
Negative power supply voltage.
Integrator output. Connection point for integration capacitor. See
6
INTEGRATING CAPACITOR section for more details
28 (13) VBUFF Integration resistor connection. Use a 47kΩ resistor for a 200mV full-
scale range and a 470kΩ resistor for 2V full-scale range.
29 (12) CAZ The size of the auto-zero capacitor influences system noise. Use a
0.47µF capacitor for 200mV full scale, and a 0.047µF capacitor for
2V full scale. See Paragraph on AUTO-ZERO CAPACITOR for more

30 (11) V –IN
details.
The analog LOW input is connected to this pin. 7
31 (10) V +IN The analog HIGH input signal is connected to this pin.
32 (9) ANALOG This pin is primarily used to set the analog common-mode voltage
COMMON for battery operation or in systems where the input signal is
referenced to the power supply. It also acts as a reference voltage
source. See paragraph on ANALOG COMMON for more details.
33 (8) C –REF See pin 34.

8
TELCOM SEMICONDUCTOR, INC. 3-187
3-1/2 DIGIT A/D CONVERTERS
TC7106
TC7106A
TC7107
TC7107A

PIN DESCRIPTION (Cont.)


Pin No. Pin No.
40-Pin PDIP 40-Pin PDIP
(Normal) (Reverse) Symbol Description
+
34 (7) C REF A 0.1µF capacitor is used in most applications. If a large common-
mode voltage exists (for example, the V –IN pin is not at analog
common), and a 200mV scale is used, a 1µF capacitor is recom-
mended and will hold the roll-over error to 0.5 count.

35 (6) VREF See pin 36.
+
36 (5) V REF The analog input required to generate a full-scale output (1999
counts). Place 100mV between pins 35 and 36 for 199.9mV
full-scale. Place 1V between pins 35 and 36 for 2V full scale. See
paragraph on REFERENCE VOLTAGE.
37 (4) Test Lamp test. When pulled HIGH (to V+) all segments will be turned on
and the display should read –1888. It may also be used as a negative
supply for externally-generated decimal points. See paragraph under
TEST for additional information.
38 (3) OSC3 See pin 40.
39 (2) OSC2 See pin 40.
40 (1) OSC1 Pins 40, 39, 38 make up the oscillator section. For a 48kHz clock
(3 readings per section), connect pin 40 to the junction of a 100kΩ
resistor and a 100pF capacitor. The 100kΩ resistor is tied to pin 39
and the 100pF capacitor is tied to pin 38.

GENERAL THEORY OF OPERATION where:


DUAL SLOPE CONVERSION PRINCIPLES VR = Reference Voltage
(All Pin Designations Refer to the 40-Pin DIP) TSI = Signal Integration Time (Fixed)
TRI = Reference Voltage Integration Time (Variable)
The TC7106A and TC7107A are dual slope, integrating
analog-to-digital converters. An understanding of the dual For a constant VIN:
slope conversion technique will aid in following the detailed T
VIN = VR RI
operation theory. TSI
The conventional dual slope converter measurement
cycle has two distinct phases: C
ANALOG
• Input Signal Integration INPUT
SIGNAL INTEGRATOR
– COMPARATOR
• Reference Voltage Integration (Deintegration) –
+
+
The input signal being converted is integrated for a fixed
time period (TSI). Time is measured by counting clock +/–
SWITCH
pulses. An opposite polarity constant reference voltage is DRIVER
CLOCK
then integrated until the integrator output voltage returns to REF PHASE
CONTROL
CONTROL
VOLTAGE LOGIC
zero. The reference integration time is directly proportional POLARITY CONTROL
to the input signal (TRI). (Figure 2A).
In a simple dual slope converter a complete conversion
COUNTER
DISPLAY
requires the integrator output to “ramp-up” and “ramp-
INTEGRATOR
OUTPUT

down.” VIN ≈ VFULL SCALE


A simple mathematical equation relates the input signal, VIN ≈ 1/2 VFULL SCALE

reference voltage and integration time:


FIXED VARIABLE
TSI SIGNAL
INTEGRATE
REFERENCE
INTEGRATE
1 VRTRI TIME TIME

RC 0 V IN(t)dt = RC
Figure 2A. Basic Dual Slope Converter

3-188 TELCOM SEMICONDUCTOR, INC.


3-1/2 DIGIT A/D CONVERTERS
TC7106
TC7106A
1
TC7107
TC7107A

The dual slope converter accuracy is unrelated to the Signal Integrate Cycle
integrating resistor and capacitor values as long as they are
stable during a measurement cycle. An inherent benefit is
noise immunity. Noise spikes are integrated or averaged to
When the auto-zero loop is opened, the internal differ-
+
ential inputs connect to V IN –
and VIN. The differential input
signal is integrated for a fixed time period. The signal
2
zero during the integration periods. Integrating ADCs are integration period is 1000 counts. The externally set clock
immune to the large conversion errors that plague succes- frequency is divided by four before clocking the internal
sive approximation converters in high-noise environments. counters. The integration time period is:
Interfering signals with frequency components at multiples
of the averaging period will be attenuated. Integrating ADCs 4
TSI = x 1000
commonly operate with the signal integration period set to a fOSC
multiple of the 50/60 Hz power line period. (Figure 2B) where: 3
fOSC = External Clock Frequency
30
The differential input voltage must be within the device
NORMAL MODE REJECTION (dB)

common-mode range (1V of either supply) when the con-


verter and measured system share the same power supply
20 common (ground). If the converter and measured system do

not share the same power supply common, VIN
tied to analog common.
should be

Polarity is determined at the end of the signal integrate


4
10 phase. The sign bit is a true polarity indication in that signals
less than 1 LSB are correctly determined. This allows
precision null detection, limited only by device noise and
T = MEASUREMENT PERIOD auto-zero residual offsets.
0
Reference Integrate Cycle
0.1/T 1/T
INPUT FREQUENCY
10/T


VIN
The final phase is reference integrate or de-integrate.
is internally connected to analog common and V IN +
is
5
Figure 2B. Normal-Mode Rejection of Dual Slope Converter
connected across the previously charged reference capaci-
ANALOG SECTION tor. Circuitry within the chip ensures that the capacitor will be
connected with the correct polarity to cause the integrator
In addition to the basic signal integrate and deintegrate output to return to zero. The time required for the output to
cycles discussed, the circuit incorporates an auto-zero return to zero is proportional to the input signal and is
cycle. This cycle removes buffer amplifier, integrator, and
comparator offset voltage error terms from the conversion.
A true digital zero reading results without adjusting external
between 0 and 2000 counts. The digital reading displayed is:

1000 x
VIN 6
potentiometers. A complete conversion consists of three VREF
cycles: an auto-zero, signal-integrate and reference-inte-
grate cycle. DIGITAL SECTION (TC7106A)
The TC7106A (Figure 3) contains all the segment driv-
Auto-Zero Cycle
ers necessary to directly drive a 3 -1/2 digit liquid crystal
During the auto-zero cycle the differential input signal is
disconnected from the circuit by opening internal analog
gates. The internal nodes are shorted to analog common
display (LCD). An LCD backplane driver is included. The
backplane frequency is the external clock frequency divided
by 800. For three conversions/second the backplane fre-
7
(ground) to establish a zero-input condition. Additional ana- quency is 60Hz with a 5V nominal amplitude. When a
log gates close a feedback loop around the integrator and segment driver is in phase with the backplane signal the
comparator. This loop permits comparator offset voltage segment is “OFF.” An out of phase segment drive signal
error compensation. The voltage level established on CAZ causes the segment to be “ON” or visible. This AC drive
compensates for device offset voltages. The offset error configuration results in negligible DC voltage across each
referred to the input is less than 10µV.
The auto-zero cycle length is 1000 to 3000 counts.
LCD segment. This insures long LCD display life. The
polarity segment driver is “ON” for negative analog inputs. If
+
V IN –
and VIN are reversed, this indicator will reverse.
8
TELCOM SEMICONDUCTOR, INC. 3-189
TC7107A
TC7107
TC7106A
TC7106
3-190

TYPICAL SEGMENT OUTPUT


+
V

0.5mA
SEGMENT
OUTPUT
LCD DISPLAY
2mA

TC7106A INTERNAL DIGITAL GROUND


BACKPLANE
21

CAZ CINT
CREF RINT
Figure 3. TC7106A Block Diagram

+ + – – + LCD SEGMENT DRIVERS


C REF VREF VREF C REF V BUFF V VINT

34 36 35 33 28 1 29 27
INTEGRATOR 7 SEGMENT
TO
7 SEGMENT 7 SEGMENT
DECODE
÷ 200
DECODE DECODE
– – DIGITAL
10 A/Z A/Z + SECTION
µA + + DATA LATCH

A/Z
+ 31
V IN COMPARATOR
DE DE THOUSANDS HUNDREDS TENS UNITS
INT (–) (+)

LOW
A/Z – TEMPCO TO SWITCH DRIVERS
VREF FROM COMPARATOR OUTPUT
+ 1
V+

3-1/2 DIGIT A/D CONVERTERS


32 DE (+) DE (–)
ANALOG CLOCK
COMMON V+– 3.0V fOSC
÷4 CONTROL LOGIC 6.2V
– 30 AZ & DE (±)
V IN 37
INT 26 TEST
TELCOM SEMICONDUCTOR, INC.

INTERNAL DIGITAL GOUND 500Ω


– VTH
V
= 1V
26
V–
40 39 38
OSC 1 OSC 2 OSC 3

ROSC
COSC
3-1/2 DIGIT A/D CONVERTERS
TC7106
TC7106A
1
TC7107
TC7107A

When the TEST pin on the TC7106A is pulled to V+, all • Signal Integrate: 1000 Counts
segments are turned “ON.” The display reads –1888. During
this mode the LCD segments have a constant DC voltage
impressed. DO NOT LEAVE THE DISPLAY IN THIS MODE
(4000 Clock Pulses)
This time period is fixed. The integration period is: 2
FOR MORE THAN SEVERAL MINUTES! LCD displays
may be destroyed if operated with DC levels for extended
TSI = 4000 [ ]1
fOSC
periods.
The display font and the segment drive assignment are Where fOSC is the externally set clock frequency.
shown in Figure 4. • Reference Integrate: 0 to 2000 Counts

DISPLAY FONT
(0 to 8000 Clock Pulses)
The TC7106A/7107A are drop-in replacements for the 3
7106/7107 parts. External component value changes are
not required to benefit from the low drift internal reference.
1000's 100's 10's 1's
Clock Circuit
Three clocking methods may be used:
1. An external oscillator connected to pin 40.
2. A crystal between pins 39 and 40.
3. An R-C oscillator using all three pins.
4
Figure 4. Display Font and Segment Assignment
÷4 TO
In the TC7106A, an internal digital ground is generated COUNTER
from a 6 volt zener diode and a large P channel source
follower. This supply is made stiff to absorb the large
40 39 38
capacitive currents when the backplane voltage is switched.

DIGITAL SECTION (TC7107A)


EXT
CRYSTAL
5
Figure 5 shows the TC7107A. It is designed to drive OSC RC NETWORK TC7106A
TC7107A
common anode LEDs. It is identical to the TC7106A except
that the regulated supply and backplane drive have been TO TEST PIN ON TSC7106A
TO GND PIN ON TSC7107A
eliminated and the segment drive is typically 8mA. The
Figure 6. Clock Circuits
1000's output (pin 19) sinks current from two LED segments,
and has a 16mA drive capability.
In both devices, the polarity indication is “ON” for nega-

tive analog inputs. If VIN +
and V IN are reversed, this indication
COMPONENT VALUE SELECTION
Auto-Zero Capacitor – CAZ
6
can be reversed also, if desired. The CAZ capacitor size has some influence on system
The display font is the same as the TC7106A. noise. A 0.47µF capacitor is recommended for 200mV full-
scale applications where 1 LSB is 100µV. A 0.047µF capaci-
System Timing tor is adequate for 2.0V full-scale applications. A mylar
The oscillator frequency is divided by 4 prior to clocking dielectric capacitor is adequate.
the internal decade counters. The three-phase measure-
ment cycle takes a total of 4000 counts or 16000 clock Reference Voltage Capacitor – CREF 7
pulses. The 4000 count cycle is independent of input signal The reference voltage used to ramp the integrator
magnitude. output voltage back to zero during the reference-integrate
Each phase of the measurement cycle has the following cycle is stored on CREF. A 0.1µF capacitor is acceptable
length: when VIN–
is tied to analog common. If a large common-mode
• Auto-Zero Phase: 1000 to 3000 Counts voltage exists (VREF–
≠ analog common) and the application
(4000 to 12000 Clock Pulses) requires 200mV full-scale, increase CREF to 1.0 µF. Rollover
For signals less than full-scale, the auto-zero phase is
assigned the unused reference integrate time period.
error will be held to less than 1/2 count. A mylar dielectric
capacitor is adequate.
8
TELCOM SEMICONDUCTOR, INC. 3-191
TC7107A
TC7107
TC7106A
TC7106
3-192

TYPICAL SEGMENT OUTPUT


+
V

0.5mA
SEGMENT
OUTPUT
LED DISPLAY
8mA

TC7107A INTERNAL DIGITAL GROUND

CAZ
Figure 5. TC7107A Block Diagram

CINT
CREF RINT
+ + – – + LCD SEGMENT DRIVERS
C REF VREF VREF C REF V BUFF V VINT

34 36 35 33 28 1 29 27
INTEGRATOR 7 SEGMENT 7 SEGMENT 7 SEGMENT
TO DECODE DECODE DECODE
– – DIGITAL
10 A/Z A/Z + SECTION
µA + + DATA LATCH

A/Z
+ 31
V IN COMPARATOR
DE DE THOUSANDS HUNDREDS TENS UNITS
INT (–) (+)

LOW
A/Z – TEMPCO TO SWITCH DRIVERS
VREF

3-1/2 DIGIT A/D CONVERTERS


FROM COMPARATOR OUTPUT 1
+
32 DE (+) DE (–) V+
ANALOG CLOCK
COMMON V+– 3.0V fOSC
AZ & DE (±) ÷4 LOGIC CONTROL
– 30
V IN 21
TELCOM SEMICONDUCTOR, INC.

INT 26 DIGITAL
DIGITAL GOUND GROUND
– 500Ω
V

40 39 38 37
OSC 1 OSC 2 OSC 3 TEST

ROSC
COSC
3-1/2 DIGIT A/D CONVERTERS
TC7106
TC7106A
1
TC7107
TC7107A

Integrating Capacitor – CINT Oscillator Components


CINT should be selected to maximize the integrator
output voltage swing without causing output saturation. Due
to the TC7106A/7107A superior temperature coefficient
ROSC (Pin 40 to Pin 39) should be 100kΩ. COSC is
selected using the equation: 2
0.45
specification, analog common will normally supply the differ- fOSC =
ential voltage reference. For this case a ±2V full-scale RC
integrator output swing is satisfactory. For 3 readings/
second (fOSC = 48kHz) a 0.22µF value is suggested. If a For fOSC of 48kHz, COSC is 100pF nominally.
different oscillator frequency is used, CINT must be changed Note that fOSC is divided by four to generate the TC7106A
in inverse proportion to maintain the nominal ±2 V integrator
swing.
An exact expression for CINT is:
internal control clock. The backplane drive signal is derived
by dividing fOSC by 800.
To achieve maximum rejection of 60Hz noise pickup,
3
the signal-integrate period should be a multiple of 60Hz.
1 VFS Oscillator frequencies of 240kHz, 120kHz, 80kHz, 60kHz,
(4000) ( )( ) 48kHz, 40kHz, etc. should be selected. For 50 Hz rejection,
fOSC RINT
CINT = oscillator frequencies of 200kHz, 100kHz, 66 2/3kHz, 50kHz,
VINT 40kHz, etc. would be suitable. Note that 40kHz (2.5 read-

Where:
ings/second) will reject both 50Hz and 60Hz.

Reference Voltage Selection


4
fOSC = Clock frequency at Pin 38
VFS = Full-scale input voltage A full-scale reading (2000 counts) requires the input
RINT = Integrating resistor signal be twice the reference voltage.
VINT = Desired full-scale integrator output swing
CINT must have low dielectric absorption to minimize Required Full-Scale Voltage* VREF
rollover error. A polypropylene capacitor is recommended.

Integrating Resistor – RINT


200.0mV
2.000V
* VFS = 2 VREF
100.0mV
1.000V 5
The input buffer amplifier and integrator are designed
with class A output stages. The output stage idling current In some applications a scale factor other than unity may
is 100µA. The integrator and buffer can supply 20µA drive exist between a transducer output voltage and the required
currents with negligible linearity errors. RINT is chosen to digital reading. Assume, for example, a pressure transducer
remain in the output stage linear drive region but not so large output is 400mV for 2000 lb/in2. Rather than dividing the
input voltage by two the reference voltage should be set to
that printed circuit board leakage currents induce errors. For
a 200mV full-scale, RINT is 47kΩ. 2.0V full-scale requires
470kΩ.
200mV. This permits the transducer input to be used
directly.
6
The differential reference can also be used when a
digital zero reading is required when VIN is not equal to zero.
Component Nominal Full-Scale Voltage This is common in temperature measuring instrumentation.
Value 200.0mV 2.000V A compensating offset voltage can be applied between

CAZ 0.47µF 0.047µF analog common and VIN . The transducer output is con-
+
RINT 47kΩ 470kΩ nected between V IN and analog common.
CINT
Note:1.
0.22µF
fOSC = 48kHz (3 readings/sec)
0.22µF The internal voltage reference potential available at
analog common will normally be used to supply the convert-
7
er's reference. This potential is stable whenever the supply
potential is greater than approximately 7V. In applications
where an externally-generated reference voltage is desired,
refer to Figure 7.

8
TELCOM SEMICONDUCTOR, INC. 3-193
3-1/2 DIGIT A/D CONVERTERS
TC7106
TC7106A
TC7107
TC7107A

V+ CI
V+ INPUT
V+ BUFFER
+ + RI
+ V+ –
VREF 6.8V – VI
ZENER 6.8kΩ VIN +

VREF INTEGRATOR
TC7106A 20k Ω
TC7107A –
TI
TC7106A
IZ
+
VREF VCM
VI =
RI CI
[
V CM – VIN [
TC04 Where:
TC7107A 4000
– 1.2V T I = INTEGRATION TIME =
VREF f OSC
REF
C I = INTEGRATION CAPACITOR
COMMON R I = INTEGRATION RESISTOR
(a) (b)

Figure 7. External Reference Figure 9. Common-Mode Voltage Reduces Available Integrator


Swing. (VCOM ≠ VIN)

DEVICE PIN FUNCTIONAL DESCRIPTION


full-scale swing. The integrator output will swing within 0.3V
Differential Signal Inputs of V+ or V– without increasing linearity errors.
(V+IN (Pin 31), V–IN (Pin 30))
The TC7106A/7017A is designed with true differential
Differential Reference
inputs and accepts input signals within the input stage + –
(V REF (Pin 36), VREF (Pin 35))
common mode voltage range (VCM). The typical range is V+
–1.0 to V– +1 V. Common-mode voltages are removed from The reference voltage can be generated anywhere
the system when the TC7106A/TC7107A operates from a within the V+ to V– power supply range.
battery or floating power source (isolated from measured To prevent rollover errors from being induced by large
– common-mode voltages, CREF should be large compared to
system) and VIN is connected to analog common (VCOM):
See Figure 8. stray node capacitance.
In systems where common-mode voltages exist, the The TC7106A/TC7107A circuits have a significantly
86dB common-mode rejection ratio minimizes error. Com- lower analog common temperature coefficient. This gives a
mon-mode voltages do, however, affect the integrator out- very stable voltage suitable for use as a reference. The
put level. Integrator output saturation must be prevented. A temperature coefficient of analog common is 20ppm/°C
worst-case condition exists if a large positive VCM exists in typically.
conjunction with a full-scale negative differential signal. The
negative signal drives the integrator output positive along
with VCM (Figure 9). For such applications the integrator
output swing can be reduced below the recommended 2.0V

SEGMENT
DRIVE LCD DISPLAY

MEASURED VBUF CAZ VINT POL BP


SYSTEM OSC1
V+IN
+
V
V –IN TC7106A
OSC3
V– GND OSC2
ANALOG – + +
COMMON VREF VREF V V–
V+ V – GND
POWER +
SOURCE 9V

Figure 8. Common-Mode Voltage Removed in Battery Operation with VIN = Analog Common

3-194 TELCOM SEMICONDUCTOR, INC.


3-1/2 DIGIT A/D CONVERTERS
TC7106
TC7106A
1
TC7107
TC7107A

Analog Common (Pin 32) Internal Voltage Reference Stability


The analog common pin is set at a voltage potential
approximately 3.0V below V+. The potential is guaranteed
The analog common voltage temperature stability has
been significantly improved (Figure 10). The “A” version of
2
to be between 2.7V and 3.35 V below V+. Analog common the industry standard circuits allow users to upgrade old
is tied internally to the N channel FET capable of sinking systems and design new systems without external voltage
20mA. This FET will hold the common line at 3.0V should an references. External R and C values do not need to be
external load attempt to pull the common line toward V+. changed. Figure 11 shows analog common supplying the
Analog common source current is limited to 10µA. Analog necessary voltage reference for the TC7106A/TC7107A.
common is therefore easily pulled to a more negative
voltage (i.e., below V+ – 3.0V).
The TC7106A connects the internal V IN +
and VIN –
inputs 200 3
to analog common during the auto-zero cycle. During the

TEMPERATURE COEFFICIENT (ppm/°C)


– 180 NO
reference-integrate phase, VIN is connected to analog com-
– MAXIMUM
mon. If VIN is not externally connected to analog common, 160 SPECIFIED NO MAXIMUM
a common-mode voltage exists. This is rejected by the SPECIFIED
140 TYPICAL
converter's 86dB common-mode rejection ratio. In battery

operation, analog common and VIN are usually connected, 120
removing common-mode voltage concerns. In systems where

VIN is connected to the power supply ground or to a given

100
MAXIMUM
NO MAXIMUM
SPECIFIED
4
voltage, analog common should be connected to VIN . 80 LIMIT TYPICAL
The analog common pin serves to set the analog section
reference or common point. The TC7106A is specifically 60
designed to operate from a battery or in any measurement TYPICAL
40
system where input signals are not referenced (float) with
respect to the TC7106A power source. The analog common 20
TC
potential of V+ – 3.0V gives a 6 V end of battery life voltage.
The common potential has a 0.001%/% voltage coefficient
and a 15 Ω output impedance.
0
7106A ICL7106 ICL7136
5
Figure 10. Analog Common Temperature Coefficient
With sufficiently high total supply voltage (V+ – V–
> 7.0V) analog common is a very stable potential with
excellent temperature stability—typically 20ppm/°C. This
potential can be used to generate the reference voltage. An
external voltage reference will be unnecessary in most
cases because of the 50ppm/°C maximum temperature
coefficient. See Internal Voltage Reference discussion. V–
1
V+ 24kΩ
6
Test (Pin 37) TC7106A
TC7107A
The TEST pin potential is 5V less than V+. TEST may be
+ 36
used as the negative power supply connection for external VREF 1kΩ
CMOS logic. The TEST pin is tied to the internally generated VREF
negative logic supply (Internal Logic Ground) through a – 35

7
VREF
500Ω resistor in the TC7106A. The TEST pin load should be
no more than 1mA . ANALOG 32
COMMON
If TEST is pulled to V+ all segments plus the minus sign
will be activated. Do not operate in this mode for more than SET VREF = 1/2 VFULL SCALE
several minutes with the TC7106A. With TEST = V+ the LCD
segments are impressed with a DC voltage which will
destroy the LCD.
The TEST pin will sink about 10mA when pulled to V+. Figure 11. Internal Voltage Reference Connection

8
TELCOM SEMICONDUCTOR, INC. 3-195
3-1/2 DIGIT A/D CONVERTERS
TC7106
TC7106A
TC7107
TC7107A

POWER SUPPLIES TC7107 Power Dissipation Reduction


The TC7107A is designed to work from ±5V supplies. The TC7107A sinks the LED display current and this
However, if a negative supply is not available, it can be causes heat to build up in the IC package. If the internal
generated from the clock output with two diodes, two capaci- voltage reference is used, the changing chip temperature
tors, and an inexpensive IC. (Figure 12) can cause the display to change reading. By reducing the
In selected applications a negative supply is not re- LED common anode voltage the TC7107A package power
quired. The conditions to use a single +5V supply are: dissipation is reduced.
• The input signal can be referenced to the center of the Figure 14 is a photograph of a curve-tracer display
common-mode range of the converter. showing the relationship between output current and output
• The signal is less than ±1.5V. voltage for a typical TC7107CPL. Since a typical LED has
• An external reference is used. 1.8 volts across it at 7mA, and its common anode is con-
The TSC7660 DC to DC converter may be used to nected to +5V, the TC7107A output is at 3.2V (point A on
generate – 5 V from +5 V (Figure 13). Figure 13). Maximum power dissipation is 8.1mA x 3.2V x
24 segments = 622mW.
+ Notice, however, that once the TC7107A output voltage
V
is above two volts, the LED current is essentially constant as
CD4009
output voltage increases. Reducing the output voltage by
V+
0.7V (point B in Figure 14) results in 7.7mA of LED current,
only a 5 percent reduction. Maximum power dissipation is
OSC1 only 7.7mA x 2.5 V x 24 = 462mW, a reduction of 26%. An
OSC2 0.047 1N914
µF output voltage reduction of 1 volt (point C) reduces LED
OSC3 10 +
current by 10% (7.3mA) but power dissipation by 38%!
µF –
(7.3mA x 2.2V x 24 = 385mW).
1N914
TC7107A
GND
V–

V– = –3.3V

Figure 12. Generating Negative Supply From +5 V

+5 V

1
+ + 36
V VREF
– 35
VREF
LED
DRIVE 32 Figure 14. TC7107A Output Current vs Output Voltage
COM

TC7107A
+ 31
VIN
Reduced power dissipation is very easy to obtain.
VIN
Figure 15 shows two ways: either a 5.1 ohm, 1/4 watt resistor
– 30
VIN
or a 1 Amp diode placed in series with the display (but not in
21 series with the TC7107A). The resistor will reduce the
– GND
V
8
TC7107A output voltage, when all 24 segments are “ON,” to
26
+
2 point “C” of Figure 14. When segments turn off, the output
5 (–5 V)
10µF 4
TC7660
voltage will increase. The diode, on the other hand, will result
3 *3-1/2 DIGIT ADC in a relatively steady output voltage, around point “B.”
+ 10µF
In addition to limiting maximum power dissipation, the
resistor reduces the change in power dissipation as the
Figure 13. Negative Power Supply Generation with TC7660 display changes. This effect is caused by the fact that, as
3-196 TELCOM SEMICONDUCTOR, INC.
3-1/2 DIGIT A/D CONVERTERS
TC7106
TC7106A
1
TC7107
TC7107A

fewer segments are “ON,” each “ON” output drops more APPLICATIONS INFORMATION
voltage and current. For the best case of six segments (a
“111” display) to worst case (a “1888” display) the resistor
will change about 230mW, while a circuit without the resistor Liquid Crystal Display Sources 2
will change about 470mW. Therefore, the resistor will re- Several LCD manufacturers supply standard LCD dis-
duce the effect of display dissipation on reference voltage plays to interface with the TC7106A 3-1/2 digit analog-to-
drift by about 50%. digital converter.
The change in LED brightness caused by the resistor is
almost unnoticeable as more segments turn off. If display
Manufacturer Address/Phone Part Numbers1
brightness remaining steady is very important to the de-
signer, a diode may be used instead of the resistor. Crystaloid
Electronics
5282 Hudson Dr.
Hudson, OH 44236
C5335, H5535,
T5135, SX440
3
Figure 15. Diode or Resistor Limits Package Power Dissipation 216/655-2429
AND 720 Palomar Ave. FE 0201,0701
APPLICATIONS INFORMATION Sunnyvale, CA 94086 FE 0203, 2201
408/523-8200 FE 0501
+5V IN –5V Epson 3415 Kashikawa St. LD-B709BZ
+ –
Torrance, CA 90505 LD-H7992AZ
24kΩ
1 MΩ

TP3
150Ω
Hamlin, Inc.
213/534-0360
612 E. Lake St. 3902, 3933, 3903
4
1kΩ
0.47
Lake Mills, WI 53551
µF 0.22 414/648-2361
100 0.01
pF µF µF Note: 1. Contact LCD manufacturer for full product listing/specifications.
TP5
TP2 0.1 DISPLAY
100 µF 47
kΩ TP1 kΩ Light Emitting Diode Display Sources
Several LED manufacturers supply seven segment
5
40 30 TP 21
4
TC7107A
digits with and without decimal point annunciators for the
TC7107A.
1 10 20

Manufacturer Address Display Type


DISPLAY
5.1Ω 1/4W
Hewlett-Packard 640 Page Mill Rd. LED
Components Palo Alto, CA 94304
1N4001
AND 720 Palomar Ave. LED
Sunnyvale, CA 94086
6

8
TELCOM SEMICONDUCTOR, INC. 3-197
3-1/2 DIGIT A/D CONVERTERS
TC7106
TC7106A
TC7107
TC7107A

Decimal Point and Annunciator Drive Ratiometric Resistance Measurements


The TEST pin is connected to the internally-generated The true differential input and differential reference
digital logic supply ground through a 500 Ω resistor. The make ratiometric reading possible. Typically in a ratiometric
TEST pin may be used as the negative supply for external operation, an unknown resistance is measured with respect
CMOS gate segment drivers. LCD display annunciators for to a known standard resistance. No accurately defined
decimal points, low battery indication, or function indication reference voltage is needed.
may be added without adding an additional supply. No more The unknown resistance is put in series with a known
than 1mA should be supplied by the TEST pin: its potential standard and a current passed through the pair. The voltage
is approximately 5V below V+. developed across the unknown is applied to the input and
the voltage across the known resistor is applied to the
reference input. If the unknown equals the standard, the
V+
display will read 1000. The displayed reading can be deter-
V+
mined from the following expression:
4049
R Unknown
TC7106A Displayed Reading = x 1000
R Standard
TO LCD
BP 21 DECIMAL
POINT The display will overrange for R Unknown ≥ 2 x R
37 GND standard.
TEST
TO LCD
BACK-
PLANE +
VREF V+
RSTANDARD V–REF

V+ +
V IN
LCD DISPLAY

V+ BP RUNKNOWN TC7106A


V IN
DECIMAL TO LCD ANALOG
POINT DECIMAL COMMON
TC7106A SELECT POINTS

Figure 17. Low Parts Count Ratiometric Resistance


Measurement
TEST 4030
GND

Figure 16. Decimal Point Drive Using TEST as Logic Ground

3-198 TELCOM SEMICONDUCTOR, INC.


3-1/2 DIGIT A/D CONVERTERS
TC7106
TC7106A
1
TC7107
TC7107A

+ 9V

VIN
IN4148
200mV
10kΩ
1µF
+

1 14
1
V+ V–
26
27
2
9MΩ 24kΩ
2V 0.02 2 13
1MΩ
µF TC7106A 29
3 12
900kΩ 1MΩ 36
20 V 1kΩ V+
REF
4 AD636 11
47kΩ – 28
35
90kΩ 1W 6.8µF 5 10 V–
REF
200 V 10% +
32

10kΩ

20kW
6
7
9
8
1MΩ 10%

0.01
31
ANALOG
COMMON
V+
IN
40 3
2.2µF µF
10% 30 38
COM V–
IN
C1 = 3–10pF VARIABLE, 26 39
C2 = 132pF VARIABLE V–

SEG BP
DRIVE

4
LCD DISPLAY

Figure 18. 3 1/2 Digit True RMS AC DMM

+ 9V + 9V

160kΩ 300kΩ 300kΩ


5.6kΩ 160kΩ
5
V+ V– V+ V–
– –
VIN 1N914 R1 VIN
20kΩ
1N4148 R1 + +
VIN VIN TC7106A
SENSOR TC7106A
50kΩ
VFS = 2V
0.7%/°C R2 +

6
R2 + R3 VREF
VREF PTC
50kΩ 20kΩ

– –
VREF VREF

COMMON COMMON

Figure 19. Temperature Sensor Figure 20. Positive Temperature Coefficient Resistor
Temperature Sensor
7

8
TELCOM SEMICONDUCTOR, INC. 3-199
3-1/2 DIGIT A/D CONVERTERS
TC7106
TC7106A
TC7107
TC7107A

9V

2 1
CONSTANT 5 V
V+ V+
V+REF

REF02 6 51kΩ 5.1kΩ TC911 50kΩ


TC7106A
VOUT R2 V–
REF
R4 R5

5 2 – VFS = 2.00V
ADJ NC 8
1
V–
IN
3 3 +
TEMP 4 VOUT =
1.86V @ V+
IN
TEMPERATURE 25°C
50kΩ
DEPENDENT 1.3k R1 COMMON
OUTPUT

GND V–
4 26

Figure 21. Integrated Circuit Temperature Sensor

TO PIN 1 TO PIN 1
SET VREF = 100mV SET VREF = 100mV
40 40
100kΩ 100kΩ
39 39
38 38
37 100pF 37 100pF
36 36
35 35 +5V
34 1 kΩ 22kΩ 34 1kΩ 22kΩ
0.1µF 0.1µF
33 1MΩ + 33 1MΩ +
32 32
31 0.01µF IN 31 0.01µF IN
TC7106A TC7107A 30
30
0.47µF + – 0.47µF –
29 29
47kΩ 47kΩ
28 9V 28
27 – 27
0.22µF 0.22µF
26 26 –5V
25 25
24 24
TO DISPLAY 23 TO DISPLAY
23
22 22
21 TO BACKPLANE 21

Figure 22. TC7106A Using the Internal Reference: 200mV Full- Figure 23. TC7107A Internal Reference (200mV Full-Scale,
Scale, 3 Readings-per-second (RPS). –
3RPS, VIN Tied to GND for Single Ended Inputs).

3-200 TELCOM SEMICONDUCTOR, INC.


3-1/2 DIGIT A/D CONVERTERS
TC7106
TC7106A
1
TC7107
TC7107A

V+
1 40 TO PIN 1

SET VREF = 1V
2
40
TO 100kΩ
LOGIC 39
VCC TO 38
LOGIC 37 100pF
GND 24kΩ
36
35 V+
TC7106A 34 25k Ω
0.1µF

TC7106A
33
32
31 0.01µF
1MΩ +

IN
3
V– 30
O/R TC7107A 0.047µF –
29
470k Ω
28
27 0.22µF
U/R 26 V–
20 21 25
24
CD4023 TO DISPLAY
23

4
OR 74C10
CD4077 O/R = OVERRANGE 22
U/R = UNDERRANGE 21

Figure 24. Circuit for Developing Underrange and Overrange Figure 25. TC7106A/TC7107A: Recommended Component
Signals from TC7106A Outputs. Values for 2.00V Full-Scale

TO PIN 1 TO PIN 1 5
40 40
100k Ω 100kΩ
39 SET VREF = 100mV 39 SET VREF = 100mV
38 38
37 100pF 37 100pF
36 10k Ω 10kΩ 36 10k Ω 10kΩ
+ +
35 V 35 V
34 1kΩ TC04 34 1 kΩ TC04
0.1µF 0.1µF
33
32
31
30
1.2V

0.01µF 1M Ω
+

IN
TC7107A
33
32
31
30
0.01µF
1.2V

1MΩ
+

IN
6
TC7107A 0.47µF 0.47µF –
29 – 29
47kΩ 47kΩ
28 28
27 27
0.22µF – 0.22µF
26 V 26
25 25
24 24
TO DISPLAY TO DISPLAY
23 23
22
21
22
21
7
Figure 26. TC7107A With a 1.2V External Band-Gap Reference. Figure 27. TC7107A Operated from Single +5V Supply. An

(VIN Tied to Common.) External Reference Must Be Used in This Application.

8
TELCOM SEMICONDUCTOR, INC. 3-201
This datasheet has been downloaded from:

www.DatasheetCatalog.com

Datasheets for electronic components.