OCT 2008 VOL 1.

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A Message from Director
“Mistakes are painful when they
happen. But year’s later collection
Congratulations to our team for successful completion of the
of mistakes is called experience,
which leads to success“ first phase of the VLSI Design Awareness program.

“The only way to know that We proudly announce the launch of the second phase of the
someone is trustworthy is to trust awareness program in which esteemed engineering colleges
him” will be attached for ASIC development and to present the
seminars in different colleges in VLSI domain
“Men are disturbed not by the
things that happen, but by their
(Topic Courtesy of IEEE Press)

opinion of the things that happen”

Tech Byte
Importance of Clock
A clock is an electric signal that oscillates between a high state and As just addressed, in today’s VLSI chip design environment
a low state. It is usually a square wave with a predetermined periodmost integrated circuits of sufficient complexity require clock signals
(frequency), as shown in Figure 1. In synchronous digital circuits, to synchronize different parts of the chip and to account for
the clock signals coordinate the actions of all the circuit propagation delays. However, as chips get more complex and clock
components on a chip. The circuits become active at either the speeds approach the gigahertz range, the task of supplying accurate
and synchronized clocks to all of the circuit components becomes
rising edge, the falling edge, or both edges of the clock signals for
synchronization. The issue associated with clock signals is the mostmore and more difficult. Furthermore, the voltage and current spikes
important design factor in any VLSI chip design. associated with clock switching csdcsd
become harder to control because
Synchronization is a task in timekeeping that requires the millions of components are switching at roughly the same time. As a
coordination of events to operate a system in a harmonic fashion. Inresult, the asynchronous self-clock circuit design approach has been
explored with great interest.
an electronic circuit in which millions of events occur every second,
the synchronization of these events is the key to achieving the Figure 2 shows the principal ideas of synchronous and
desired functions. During the process of synchronization, for some asynchronous design styles. In the synchronous design approach, the
applications, relative timing offsets between events must be known actions are coordinated by the clock signal as data is moved from
register to register. In contrast, in clock less asynchronous designs,
or determined. For others, only the order of the events is significant
the actions are coordinated by a handshake mechanism between the
Without synchronous design principles, or clocks, it is impossible to
construct the complicated SO chips that we build today blocks. When a block must initiate a data transfer, it first sends a
request signal (REQ). The
intended block issues an
sdvsv
Period or frequency acknowledge signal (ACK)
when it is ready for the
transfer. All of the data
Clock signal communication inside the
asynchronous block is
accomplished though certain
Rising edge falling edge handshake mechanisms
without using the clock. The
advantage of this method is
Fig 1: A clock signal waveform that it eliminates the design
The synchronous design principle can significantly simplify the overheads associated with clock structure. In some cases, the
implementation task in chip design. The design and verification asynchronous design approach can potentially increases the data
burden are eased greatly. This is especially true for large SoC throughput as well. It also provides the superior modularity that is
designs in which design complexity is dreadful. As an example, the preferred for SoC designs. Due to the clockless feature, it is more
synchronous design principle enables the technique of static time robust against the process, temperature, and voltage variations in
analysis (STA), which is an essential tool for achieving timing terms of wire delay. It definitely lessens the power supply noise by
closure. Synchronous design style also enables the method of reducing the current peak around the clock edges. The overall power
formal verification, which is an important approach for logic consumption is also trimmed since the clock-related power usage is
verification now nonexistent.
 R R R R
DATAIN E Combo E Combo E Combo E
logic logic logic
G G G G DATAOUT

CLK

Synchronous design style

ACK
ACK
R R R R
DATAIN E Combo E Combo E Combo E
logic logic logic DATAOUT
G G G G
REQ REQ

Asynchronous design style

Fig 2: Synchronous and asynchronous design styles.

However, the asynchronous design style cannot be easily Clock distribution
implemented in large designs due to the lack of the corresponding Quality of the clock signals is the most important factor for ensuring
EDA tools. Additionally, the testing of the asynchronous design isa chip’s successful operation. In a design netlist, there are hundreds of
more difficult than that of the synchronous circuit. Currently, there
thousands or millions of cells. Those cells can be classified as two
is a design approach called globally asynchronous locally types: combinational cells and sequential cells (including memories).
(Topic Courtesy of IEEE Press)

synchronous (GALS) that combines the advantages of both The sequential cells are used for storing information and they must
asynchronous and synchronous. Figure 3 presents this technique. Inoperate on clocks. After the placement stage of the design
this configuration, certain low-level blocks are synchronously implementation process, all of the cells, including the sequential cells,
designed. Then asynchronous wrappers with handshake are spread around the entire chip. The task of clock distribution is to
mechanisms are constructed around such blocks. At the chip level, distribute the clock signals to all of these sequential cells. This work
communication is accomplished through asynchronous
is commonly called clock tree synthesis.
interconnection. Figure 4 shows the principle idea of how a clock tree is constructed.
Clocks are also essential for certain types of analog circuits to As depicted, a clock network may be constructed in tree fashion.
function. For example, analog-to-digital converters and digital-to-
Starting from the clock source, the first level of clock buffers are laid
analog converters all work on clock signals. The internal circuitry
out, then the second level, then the third level, and so on. In most
of these converters, and thus the signal conversion, are triggered by
designs, there are many clock domains, and each domain has
the clock edge. hundreds or thousands of sequential cells
In summary, for a VLSI chip to function, reliable clock signals attached to it. This many cells cannot
must be provided one way or another. be driven by a single buffer from the
clock source, even with the strongest
buffer in the library. A tree structure
is used to deal with this problem by
letting each buffer drive only the
number of loads that it is allowed to
Synchronous Synchronous drive. As a result, the quality of the
Block Block clock signal, in term of slew rate (the
rising and falling time of the clock
edges), is not significantly degraded
Asynchronous Wrapper Asynchronous Wrapper
when it reaches the leaf sequential
cells. Figure 5 shows the commonly
used clock tree structures in the clock
distribution networks: trunk, branch-
tree, mesh, X-tree and H-tree. Figure
6 is an example of how a real clock
Synchronous Synchronous tree looks in a design block. In this
Block Block simple example, there is one level of
clock buffers between the clock root
and the leaves.
Asynchronous Wrapper Asynchronous Wrapper Another type of clock
distribution network is the clock grid.
In this approach, a grid of metal
structure, which covers the entire
Asynchronous interconnect chip, is dedicated to the distribution
of clock signals, as graphically shown
in Figure 7
Fig 3: A globally asynchronous locally synchronous (GALS) system.
 Root

Clock tree

Fig 4: A basic clock tree

H-tree
(Topic Courtesy of IEEE Press)

Mesh (grid)

X-tree

Branch-tree

Trunk

Fig 5: Commonly used tree structures in clock distribution networks.

Fig 6: An example of a clock tree in chip design.

 Clock
source

Clock Grid on
entire chip area
(Topic Courtesy of IEEE Press)

Fig 7: The clock grid on a chip...

A tree structure usually consumes less wiring and thus less
capacitance and less routing resources, which results in lower power
and less latency. However, a tree structure must be carefully tuned
and it is very load (placement) dependent. In contrast, a grid structure
uses significantly more routing resources and thus has large
capacitance and large latency, but it tends to be less load dependent as
any leaf cell can always find a nearby tapping point to connect to
directly. As a result, a grid structure clock distribution network is
typically used only for high-end applications, such as
microprocessors, whereas a tree structure is widely used for ASIC-
based designs. The clock distribution network consumes more than
10% of the total power used by the chip in large
Designs. During each clock cycle, the capacitance associated with
the entire clock structure must be charged to the supply voltage
and subsequently dumped to ground, with the stored energy lost
as heat. To ease this problem, resonant clock distribution has
been actively studied by some groups. In this method, the
traditional tree- or grid-driven clock structure is augmented with
on-chip inductors to resonate with the clock capacitance at the
clock’s fundamental frequency. The energy of the fundamental
frequency resonates back and forth between its electric and
magnetic form rather than being dissipated as heat. The clock
driver is only used for adding the energy lost during the
operation. This idea is depicted in figure 8

inductor

Clock
buffer chain Tree structure

Clock grid

Fig 8. The idea of a resonant clock network.

 Key Requirement for constructing a Clock tree
The key requirements for constructing a clock tree are clock skew
and insertion delay. Clock skew is the maximum timing
difference among the arrive times of the leaf cells in a clock
domain. In Figure 9, the result of a SPICE analysis of a clock tree
is demonstrated. A clock pulse is injected into the clock tree at
time 0 ns with a rise time of 1 ns. After traveling inside the tree,
the clock signal arrives at the leaves (also called clock sinks) at
approximately 3.4 ns. However, it is clear that the arrive times for
the leaves are not the same due to the different physical locations
of the leaf cells. They spread within a range of approximately 1
ns, which is defined as clock skew. In other words, the existence
of skew means that not all of the sequential cells in a particular
clock domain receive their clock
The key requirements for constructing a clock tree are clock skew
and insertion delay. Clock skew is the maximum timing difference
among the arrive times of the leaf cells in a clock domain. In Figure
9, the result of a SPICE analysis of a clock tree is demonstrated. A
clock pulse is injected into the clock tree at time 0 ns with a rise
time of 1 ns. After traveling inside the tree, the clock signal arrives
at the leaves (also called clock sinks) at approximately 3.4 ns.
However, it is clear that the arrive times for the leaves are not the
same due to the different physical locations of the leaf cells. They
spread within a range of approximately 1 ns, which is defined as
clock skew. In other words, the existence of skew means that not all
of the sequential cells in a particular clock domain receive their
clock

V
Skew
(Topic Courtesy of IEEE Press)

O
L Insertion delay
T
S
Clock signal
Clock signal at leaves
at source

nanosec

Figure 9. Clock skew and insertion delay.

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DIT, D.Doon
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