*** LogicWorks 5 for Windows - Version History *** LogicWorks 5.0.

2 2006-02-14 t Drawing: Fixed: Problem created in Model Wizard in 5.0.1 due to types no being save to subcct file correctly VHSim: Fixed: Bit order not correct in multi-bit concat & operation VHSim: Fixed: conv_integer not handling SIGNED type correctly VHSim: Added: Improved compile error checking VHSim: Added: Bring console window to the front on errors

LogicWorks 5.0.1 2006-01-03 - Drawing: Fixed: Not setting design default text style when Text Specs co mmand used - System: Fixed: Text frame styles were not copied to external clipboard pict - Drawing: Added: Accept an empty file as a valid empty design so Windows New command works - System: Fixed: Error in calculating window size for Float command on pr ivate dialog bar - System: Added: For text doc print settings, get default measurement uni t from global preferences - Librarian: Fixed: Bomb if library is deleted or moved externally while ope n in DW - Drawing: Fixed: Message 1009 when deleting a segment of a bundle connect ed by name - Drawing: Fixed: Don't allow bus pin changes when subcircuit is read-only - Drawing: Fixed: In bus pin info box, Delete Pins should be disabled when nothing selected - Timng: Fixed: Handle bad time res values better - Simulator: Fixed: Problems setting initial values on signals with stored d rive values (Tylavsky) - Simulator: Fixed: Not updating displayed values on schem when sim started - VHSim: Fixed: Sending an unpack notify every time sim starts causes ti ming to reset, now send only if file changed - Drawing: Fixed: Not reading pin numbers > 4 chars len correctly from fil e - DevEditor: Fixed: Not using default font in auto create symbol - Librarian: Fixed: Bomb if device that is selected in parts list is deleted using Lib Maint - Simulator: Fixed: Stop simulator if Cancel clicked on model error box - VHSim: Fixed: Use SYMBOL prim type for placeholders in VHDL-generated subcct so sim doesn't try to find models for them - DevEditor: Fixed: Not handling 8 char pin numbers correctly - Drawing: Fixed: Pin number edit control in Pin Info box not big enough f or 8 chars - Drawing: Fixed: Don't save type defs only used in temp circuits - System: Fixed: Bomb occurred in welcome dialog if system settings preven ted a MRU file list from being returned

LogicWorks 5.0 2004-07-07 - DevEditor: Fixed: ge when lib created or - VHSim: Fixed: - System: Added: In Save Part As box, Save button highlight does not chan opened Not showing VHSim doc icon on tabs in workbook view Warning box on Check for Updates

- Export: blanks - Drawing: ve when device - Simulator: closed - Simulator:

Fixed: $CONTSTART & $CONTEND not accepting leading or trailing Fixed: Device delays not correctly set up if simulator not acti is placed Fixed: Not invalidating name/pointer cache when subcct open and Fixed: Not handling signal names with slash character

LogicWorks 5.0 b12 - 2004-05-25 - Drawing: Fixed: Not copying READONLY status when subcircuit copied to ne w design - JScripter: Added: DWPin::isBundle/isBus DWPin::bundlePins/busPins DWPin::b undle/bus DWTypePin::isBundle/isBus - JScripter: Added: getAppVersion - Simulator: Added: Generalized batch file stuff to run circuit files - Simulator: Added: Separate console window for batch files - PromPla: Added: Allow editing of existing PROM & PLA devices - VHSim: Added: Handle arrays of bitvector - VHSim: Added: Check for device pin count limit - DevEditor: Fixed: Autosym wipes out type of bus internal pins associated w ith subcircuit LogicWorks 5.0 b11 - 2004-04-06 - System: Change: Switched to VS.NET & Stingray 8.0 - System: Change: Removed extra update put in for panel refresh - System: Added: -hide command line option - Drawing: Fixed: Spelling error Picture Ojbect - System: Fixed: Better message on attempt to paste bitmap in foreign for mat (e.g. screen copy) - Timing: Fixed: Export Timing not working - Timing: Fixed: Copy timing data had incorrect values for $DELAY - Timing: Added: INI entry RetainTime - Simulator: Added: Check for system memory < 10MB - Timing: Fixed: Horiz scroll bar 16-bit problem with large scroll ranges - Timing: Fixed: Trigger problems and re-implemented hold options - Simulator: Added: Allow single step from stop - System: Fixed: Exception when clicking in dialog items (e.g. part previ ew window) when bar is floated (WinView::OnLButton) - Timing: Added: Print horizontal scaling options - Timing: Added: INI keyword DefaultGroupRadix - Timing: Added: Better SHIFT/CTRL selection in label area - VHSim: Added: Improved searching for models, look in doc directory - VHSim: Added: Give line number of signal definition in consistency war nings - VHSim: Fixed: Bug causing element index to be wrong when connecting to structural ports - Drawing: Fixed: Bug causing bomb when creating a new attribute table for design - VHSim: Fixed: Delete key not doing delete-forward if nothing selected

LogicWorks 5.0b10 - VTiming: Fixed: Add Automatically setting ignored

- VTiming: Fixed: - VTiming: Added: - Drawing: Fixed: - Drawing: Added: - Simulator:Added: - VTiming: Fixed: - Drawing: Fixed: - VTiming: Fixed: - VTiming: Fixed: - VTiming: Fixed: - VTiming: Fixed: - Drawing: Fixed: - VHSim: Fixed: - VHSim: Added: - Drawing: Fixed: ht-clicked - Simulator:Added: - Simulator:Added: - Simulator:Added: ts

Error messages if timing window hidden Show Simulator Tools command Not saving signal values if simulator not running Print & Print Setup in cct popup Triggers menu item Losing groups on file load Not saving initial signal values Changed group values to upper case Not using INI label background colour Labels not updating on scroll Strange colours in group value text Not saving speed if RUN VHDL/Run Simulation command not working Allow comments in batch file # // -Display signal popup when the spine of a breakout is rig INI file options for model folders Dialog to search for lost models on model open Look for test vectors for structural files when sim star

LogicWorks 5.0b9 - Simulator:Fixed: Problem creating relative model paths - VHSim: Added: Conversion from LW signal values to bit or stdbit - VHSim: Added: Handle non-constant signal array index for access or ass ignment - VHSim: Added: Handle array of boolean signals & function params - System: Fixed: Move to Shared Tab from private floating window not work ing - VHSim: Added: Handle TRUE & FALSE constants - VHSim: Fixed: BIT data type should only have values 0 and 1 (no U) - VHSim: Added: to_bit, to_bitvector, to_stdlogic, to_stdulogic, to_stdl ogicvector, to_stdulogicvector - TestPanel:Fixed: Fixed spreadsheet init problem that caused batch files n ot to work - IOPanel: Fixed: Improved initialization and clearing when opening & clos ing docs - System: Fixed: Required entry point in SHELL32.DLL not found pre-Win200 0 - VTiming: Added: Print & Print Setup in wave popup - VTiming: Added: Print time range options - VTiming: Fixed: Line and font scaling in printing - VTiming: Fixed: Retain time setting not stored or used

LogicWorks 5.0b8 - DevEditor: Fixed: Losing pin types when autocreate is run on an existing pin l ist - VTiming: Added: Set radix for group value display - Librarian: Fixed: Hitting Enter caused the window to stop working - System: Fixed: Use shortcut name and not target file name in Help Docs menu - System: Fixed: Problem with "Close Current Tab" losing tab order and eve ntual bomb

- PLA: Fixed: Weirdness when editing a RAM with exactly 3 address lines - PLA: Fixed: Use rich edit for data entry so we can handle > 32K - VHSim: Added: LENGTH attribute for arrays - VHSim: Added: type conversions e.g. STD_LOGIC_VECTOR(x) - Librarian Fixed: Wasn't recalculating checksum on Rename - VHSim: Added: 80% of std_logic_arith - System: Fixed: Nested examples not showing up in Examples dialog - System: Added: File path variables %my documents% %program files% %windo ws% %desktop% - Simulator:Added: More warnings and checks when attaching a model - DevEditor:Added: Extract pins automatically when subcct attached - VHSim: Added: Recognize VHDL files with other file extensions - Drawing: Added: Double-click on text to open for editing - System: Fixed: Problem with weird chars when editing multiline text - Drawing: Fixed: Bad error message on trying to create too large a breakout - VHSim: Fixed: Problem with range types - VHSim: Added: NEXT statement - VTiming: Fixed: Import Timing bomb LogicWorks LogicWorks LogicWorks LogicWorks LogicWorks 5.0b7 5.0b6 5.0b5 5.0b4 5.0b3 not not not not not released released released released released publicly publicly publicly publicly publicly

LogicWorks 5.0b2

- first public release

CHANGES IN VERSION 5, RELATIVE TO 4 - VHDL: LogicWorks now allows you to create simulation models using a subset of the VHDL hardware description language. Please note that some parts of the language are not implemented in this version, so some VHDL models created on other systems may not run in LogicWorks without modification. A separate ReadMe file provided with the package provides more information on the specific limitations in this version. - Simulation values of signals can now be displayed directly on the schematic diagram as the simulation progresses. - All simulation values now use real time units, e.g. nanoseconds. - IOPnael tool allows you to display and modify simulation values and creae custom display panels for your models. - Many improvements to the symbol editor tool, including the ability to automatically display pin names with each pin. - TestPanel module allows you to specify a program of input values to apply to a circuit under test and compare the results to the expected values. - Many small new features and improvements.

LogicWorks is a trademark of Capilano Computing Systems Ltd.