ENGI 241

Experiment 5

Basic Logic Gates

OBJECTIVE This experiment will examine the operation of the AND, NAND, OR, and NOR logic gates and compare the expected outputs to the truth tables for these devices. The NOT function will be implemented using NAND and NOR gates. EQUIPMENT AND PARTS REQUIRED 1 Protoboard 1 DVM 1 Logic Probe 1 74LS00, 74LS02, 74LS08, 74LS32 2 each 1k resistors INTRODUCTION The NOT circuit or inverter performs the basic logic function of complementation. It may be identified by the presence of a bubble on the input or the output of the traditional logic symbol or a triangle on the IEEE/IEC logic symbol as seen in Figure 1. The inverter has one input and one output and the output is the complement of the input. Figure 1 contains the truth table for the NOT function. LOGIC DIAGRAM TRUTH TABLE A 0 1 Q 1 0

FIGURE 1 All logic gates have two or more inputs and one output. These logic gates accept digital logic levels on their inputs and will provide a digital logic level output which is dependent on the type of logic gate and the inputs applied to the gate. For the TTL logic family, any gate input that is not connected will be treated as if a logic 1 is present on that input. The number of different possible combinations of inputs is 2n where n is the number of inputs. Therefore, four unique combinations of inputs are possible for a two input gate. A B Q 0 0 1 1 0 1 0 1 0 0 0 1

FIGURE 2

The AND function is similar to the multiplication in mathematics, and provides a logic 1 output only when all the inputs of the gate are at logic 1, and logic 0 output for all other input combinations. Figure 2 contains the logic symbols and truth table for the AND function. The Boolean Equation for a 2 input AND gate, the Boolean Equation is: Q = AB <1>

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Experiment 5

Basic Logic Gates A B 0 0 1 1 0 1 0 1 Q 1 1 1 0

FIGURE 3

The NAND function is the complement of the AND function and the logic symbols have the inversion on the output. The NAND function provides a logic 0 on the output only when both inputs are logic 1, and a logic 1 output for all other combinations. The logic diagrams and the truth table are in Figure 3. The Boolean Equation for a NAND gate is: Q= AB <2> A B 0 0 1 1 0 1 0 1 Q 0 1 1 1

FIGURE 4

The OR function is similar to the mathematical function of addition and the output for the OR gate may be analyzed using the laws of addition. The logic operator for the OR function is a + sign. The output will be logic 0 only if all the inputs are logic 0, and the output will be logic 1 anytime any input is at logic 1. The logic symbols and the truth table for the OR gate may be found in Figure 4 and the Boolean Equation for this function is: Q=A+B <3> A B Q 0 0 1 1 0 1 0 1 1 0 0 0

FIGURE 5

The complement of the OR function is the NOR function and the logic symbol has the inversion present on the output. Figure 5 contains the logic diagram and the truth table for the NOR function and the Boolean Equation is: <4> Q= A + B If we take all the inputs of a NAND gate or a NOR gate and connect them together, we will have an inverter or NOT function. This may be useful in logic design when an inverter is required. If we have a NAND gate that is not used for the circuit and we need an inverter, we can construct the inverter by connecting all the inputs together and connecting the gate in the normal manner. The connection of the NAND gate and the NOR gate as an inverter may be found in Figure 6.

FIGURE 6

FIGURE 7

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Experiment 5

Basic Logic Gates

PROCEDURE 1. Draw the entire logic diagram with pin functions for the 74LS00, the 74LS02, the 74LS08, and the 74LS32. Label all pins and note their function. 2. Build the circuit of Figure 6 using the 74LS00. Fill in Table 1 with the logic levels using the logic probe, and the output voltage as measured with the DVM. 3. Build the circuit of Figure 6 using the 74LS02. Fill in Table 2 with the logic levels using the logic probe, and the output voltage as measured with the DVM. 4. Build the circuit of Figure 7 using the 74LS08. Fill in Table 3 with the logic levels using the logic probe, and the output voltage as measured with the DVM. 5. Build the circuit of Figure 7 using the 74LS00. Fill in Table 4 with the logic levels using the logic probe, and the output voltage as measured with the DVM. 6. Build the circuit of Figure 7 using the 74LS32. Fill in Table 5 with the logic levels using the logic probe, and the output voltage as measured with the DVM. 7. Build the circuit of Figure 7 using the 74LS02. Fill in Table 6 with the logic levels using the logic probe, and the output voltage as measured with the DVM. 8. Construct the circuit of Figure 8 using only the 74LS02. Fill in Table 7 with the logic levels and voltages. FIGURE 8 9. Construct the circuit of Figure 9 using only the 74LS00. Fill in Table 8 with the logic levels and voltages. 10. Leave one input of a 74LS08 unconnected and connect the other input to a logic level as indicated by the A input of Table 9. Fill in the table with the logic outputs observed. 11. Leave one input of a 74LS32 unconnected and connect the other input to a logic level as indicated by the A input of Table 10. Fill FIGURE 9 in the table with the logic outputs observed. 12. Leave one input of a 74LS00 unconnected and connect the other input to a logic level as indicated by the A input of Table 11. Fill in the table with the logic outputs observed. 13. Leave one input of a 74LS02 unconnected and connect the other input to a logic level as indicated by the A input of Table 12. Fill in the table with the logic outputs observed.

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Experiment 5

Basic Logic Gates

DATA TABLES INPUT A 0 1 TABLE 1 Q OUTPUT Voltage INPUT A 0 1 TABLE 2 Q OUTPUT Voltage

INPUT A 0 0 1 1 B 0 1 0 1 Q

OUTPUT Voltage

INPUT A 0 0 1 1 B 0 1 0 1 Q

OUTPUT Voltage

TABLE 3

TABLE 4

INPUT A 0 0 1 1 B 0 1 0 1 Q

OUTPUT Voltage

INPUT A 0 0 1 1 B 0 1 0 1 Q

OUTPUT Voltage

TABLE 5

TABLE 6

INPUT A 0 0 1 1 B 0 1 0 1 Q

OUTPUT Voltage

INPUT A 0 0 1 1 B 0 1 0 1 Q

OUTPUT Voltage

TABLE 7

TABLE 8

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Experiment 5

Basic Logic Gates

INPUT A 0 0 1 1 B 0 1 0 1 Q

OUTPUT Voltage

INPUT A 0 0 1 1 B 0 1 0 1 Q

OUTPUT Voltage

TABLE 9 INPUT A 0 0 1 1 B 0 1 0 1 TABLE 11 QUESTIONS 1. 2. 3. 4. 5. 6. 7. Q OUTPUT Voltage INPUT A 0 0 1 1 B 0 1 0 1

TABLE 10 OUTPUT Q Voltage

TABLE 12

Explain the behavior of a 2 input TTL gate when one input is left open? Draw the logic diagram of a 2 input NAND gate using only a 74LS02. Draw the logic diagram of a 2 input AND gate using only a 74LS02. Draw the logic diagram of a 2 input NOR gate using only a 74LS00. Draw the logic diagram of a 2 input OR gate using only a 74LS00. Draw the logic diagram and the truth table for a 4 input OR gate using only a 74LS32. Draw the logic diagram and the truth table for a 3 input AND gate using only a 74LS08.

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