PicoBlaze is an 8-bit microcontroller which can be synthesized in the Spartan 3 FPGA on the Digilent Starter Board.

PicoBlaze is similar in architecture to many small microcontrollers but it is specifically designed and optimized for implementation in an Xilinx FPGA. Note there are also larger microprocessors that can be synthesized into FPGAs such as the 32-bit MicroBlaze microprocessor. PicoBlaze (and MicroBlaze) are referred to as soft core processors as they are synthesized from an HDL and use only the Programmable Logic Blocks and Routing of an FPGA for their implementation. A second type of FPGA processor termed hard core, such as the PowerPC, are physically incorporated in the architecture of some FPGAs.

Introduction
The process of implementing any soft core microcontroller or microprocessor in an FPGA will be similar to that described below for PicoBlaze. This tutorial assumes that you have downloaded the PicoBlaze.zip files from the R: drive or web page and extracted all of the files into your working directory. These files include everything needed to synthesize the example program. PicoBlaze (see Figure 1) consists of two key parts: 1) The Processor Core: KCPSM3 ( which stands for Ken Chapman Programmable State Machine version 3 ) 2) The Program Memory ( from which instructions are fetched and executed by the processor core.) Note: that the program memory is referred to as an Instruction ROM or Program ROM in Xilinx PicoBlaze documentation since the processor core cannot write to the Program Memory.

Figure 1 Figure 1 shows the Input and Output Ports of KCPSM3, with their widths. These will usually correspond to internal signals within the top level module.

As a result, there are two corresponding VHDL files that are used to construct the complete PicoBlaze with program: i) The PicoBlaze file, KCPSM3.vhd is optimized for Spartan 3 by calling design primitives LUTs, MUX, FFs etc.) specific to Spartan 3 and, as a result, this VHDL file should not be modified by the user. The KCPSM3 requires approximately 96 slices in a Spartan3. The Program Memory file, name_rom.vhd on the other hand, is a VHDL ROM file which contains the users desired program to be executed by the PicoBlaze core. This ROM File is generated automatically by the Assembler ( pBlazIDE or KCPSM3.exe) from your assembly language program. ( .psm file ) Note that the prefix for the .psm file must be 8 characters or less.) This Program Memory is implemented in a single Block RAM in the FPGA configured to function as a 1K18-bit ROM.

ii)

The program to be executed is initialised in the Block RAM during the download of the overall design (including PicoBlaze and other user logic) and, as a result, is assembled prior to synthesis.

Figure 2 ISE PicoBlaze Project

Figure 3 PicoBlaze occupancy in an XC3S200 Figure 2 shows the Xilinx ISE Implementation Project Files for a simple PicoBlaze Project. These files are available in PicoBlaze.zip In addition to the PicoBlaze core file (kcpsm.vhd) and the ROM file (tut1_rom.vhd) there is a VHDL file to drive the seven segment display on the S3 Starter Board and the UCF file for the S3 Board. The toplevel file should be be mainly structural in content, instantiating the components and linking the processor to the ROM and the IO, but the Inputs and Outputs will require a Selection Statement. Figure 3 show how little space PicoBlaze takes up in the Spartan3 FPGA.

Figure 4 PicoBlaze.zip Files The Files provide .psm file and compile it into a VHDL ROM file it is best to use the application pBlazeIDE. The User Interface of this program is shown in Figure 5. This application is extremely useful as it allows the designer to fully simulate the assemble code and check its operation. In most cases the actual programmed processor will perform as the simulator predicts. myparts.vhd is a library file which contains the component declarations. S3_Board_UCF is the ucf file for the Board and maps the Ports of the VHDL entity onto the correct FPGAS pins.

Figure 5 pBlazeIDE User Interface Files

Programming PicoBlaze
Programming the processor in Assemble Language is interesting and informative. A Block diagram of PicoBlaze is given in Figure 6. You can see that the hardware resources are very limited. There are only 16 Registers and 2 Flags, There are however 256 x 8 bit I/O connections.
64 Byte Scratchpad RAM

The Instruction Set, which is also very limited (See Figure 7) can be split into seven groups:

Figure 6

Figure 7 PicoBlaze Instruction Set Files

Example .psm File

VHDL "S3_template_ROM.vhd", "tut1_rom.vhd", "tut1_rom"

This first line creates the VHDL rom file (tut1_rom.vhd) with the entity named, tut1_rom from the template rom file (S3_template_rom.vhd) and the psm file.

BUTTONS_port SWITCHES_port char21 char43 LEDS_port

DSIN DSIN

$02 $03

; this is the PORT_ID allocated to the Buttons ; this is the PORT_ID allocated to the Switches ; this is the PORT_ID allocated to two lower SSDs ; this is the PORT_ID allocated to two upper SSDs ; this is the PORT_ID allocated to the LEDs

DSOUT $04 DSOUT $05 DSOUT $06

The next set-of-lines allocate the I/O Port numbers to the input and output objects on the board. These must correspond with the associate ports in the top level VHDL file:

case port_id is when x"02" => in_port <= "0000" & btn; when x"03" => in_port <= swt; end case; if rising_edge(clk) then in_port_reg <= in_port; if (write_strobe='1') then case port_id is when x"04" => seg7chars(7 downto 0) <= out_port; when x"05" => seg7chars(15 downto 8) <= out_port; when x"06" => leds_reg <= out_port; end case; end if; Note the output (write strobe) port must be clocked. -- char21 -- char43 -- buttons -- switches

end if;

Figure 8 Setting the Port_ID using VHDL Case Statements in the Top Level Module

Here is a part of a program to Flash the LEDs six times:

rep05:

LOAD s9, $05 LOAD s2, $55 OUT s2, LEDS_port CALL CALL LOAD OUT CALL CALL delay100ms delay100ms s2, $AA s2, LEDS_port delay100ms delay100ms

; repeat 6x for flashing lights at start ; LOAD s2 with the hex number 55 ; OUTPUT 55 to the LEDs ; Note: 55 is one 'on', one 'off'

; LOAD s0 with the hex number AA ; OUTPUT AA to the LEDs ; Note: AA is two on, two off

SUB s9, $01 COMP s9, $00 JUMP NZ, rep05

; Subtract 1 from s9 for number of flashes ; COMPARE S9 WITH 0 ; Repeats if s9 NON ZERO

Here is a part to output the buttons to the LEDs and output the switch value to the SSD

start : IN s0, BUTTONS_port OUT s0, LEDs_port CALL delay100ms ; LOAD s1 with the number on the Switches (0 to FF) ? ; OUTPUT Switches to the lower two chars of SSD ; LOAD s0 with the number on the Buttons (0 to FF) ? ; OUTPUT s0 (Buttons) to the LED Display

IN s1, SWITCHES_port OUT s1, char21 CALL CALL delay100ms start

Here is a delay loop. ( As a 50 MHz Flash would be too quick for the eye.)

delay100ms: LOAD sA, 01 LOAD sB, 00 LOAD sC, $F8 delloop: ADD sA, 01 ADDC sB, 00 ADDC sC, 00 RET Z JUMP delloop

PicoBlaze Tutorial
This tutorial demonstrates a simple PicoBlaze processor implementation on the Digilent S3 Starter Board. You can use this as a learning exercise and as a basis for more complex designs.

Figure 9 Digilent S3 Starter Board Figure 11 PicoBlaze Project Tree 1. Download the picoblaze.zip file. This should contain all the file shown in Figure 10 below:

Figure 10 PicoBlaze.zip Files 2. Open up a New Project in the Xilinx ISE Environment. ADD all the files except the Template ROM and the psm files. The Project File tree should look like that shown in Figure 11.

Figure 11 PicoBlaze Project Tree

3.

Synthesise and Implement the Project as it is, downloading the bit into the XC3S200 FPGA on the Starter Board. After a dazzling display of flashing lights, the Lower two Seven Segment Display digits should light with the value on the Switches and the lower four LEDs should light when the corresponding buttons are pressed.

4.

Now the task: a. b. c. Open up the psm file tut1.psm using pBazeIDE. Change the assembly language code so that it can remember two numbers input from the Switches and add them together, displaying the result on the SSD. You can use the simulation capability of the pBlazeIDE to demonstrate the correct functionality. Once correct re-synthesise the Project and demonstrate the correct operation on the Board.

Figure 12 pBlazeIDE Assemble,Simulation and Run

Figure 13 Left: 6 is input using Btn 1 Middle: 3 is input using Btn 2 Right: Numbers are ADDed by pressing Btn3. (9) All LEDs light to indicate end of computation.

Appendix
Differences between pBlazeIDE Instructions and KCPSM3 Instructions: