Part 1: RL Design zeta=.

707, Ts=<1sec Using the scilab commands: syslin, Plot2d we created the RL design below Wn: undamped frequency= 4/(.707)(.75)=7.54 rad/s (Here we used 2% values for ts and set ts to .75 to give some room for the response)

Using the RL design technique and the scilab commands above we obtained a transfer function: Gc= 5 + s /7.18 + s K=200 Using the scilab function to_p obtained from Dr. Mandojanas website we calculated the closed-loop bandwidth to be: 12.95rad/s = 2.06Hz Part 2. FR Design using PM> 65 degrees and BW similar to that obtained in part 1. The PM for the system at the BW above already has plenty of Phase margin so we used a BW of 5.00 Hz. The Bode plot combined with the function margin we calculated that the compensator should add 6532-Safety Margin degrees where we assumed Safety Margin was 5 degrees.

(Screen capture of Bode plot for part 2.) Phimax=32 degrees = 3.25 Using these figures and the bisection method we obtained Wm=14.65 rad T=0.01198

Thus Gc=1+.0038s/1+0.01198S Using the to_p command at the Wm above we found K=1000 however simulation proved that K=500 is a better estimate. Graphs of the Frequency and Root Locus compensators are shown below

(Dashed line represents frequency domain compensator, solid line represents root-locus compensator) Part 3: Obtaining the Digital Counterparts of the above Compensators:

We had difficulty utilizing the methodology outlined in the class so we had to improvise and troubleshoot some new commands to simulate the digital version of the compensators above. The Scilab command dscr came in very handy and allowed us to use the digital methods to perform the required simulation. The Procedure was simple using the plots above and the zoom function we were able to find Rise time for Root Locus compensator= .01625 seconds Rise time for Frequency Domain compensator =0.049 seconds We took the sampling periods for both to be 1/20 of the rise time thus obtaining: Tsf= 0.0025s ,Tsrl=0.008125s Implementing the scilab code: Gfd=ss2tf(dscrs(tf2ss(Grld),Tsrl)) And Grld=ss2tf(dscrs(tf2ss(Gfd),Tsf)) gives respectively Gcrld= z-0.96/z-.943 Gcfd=- 2.986+3.17z/ - 0.8122 + z The results of simulation are shown in the graph below:

Digital Compensators

(Line with overshoot represents digital variation of Frequency Domain Compensator, Line without overshoot represents Digital Root Locus Compensator)

The simulation does show that the results agree with each other very well although the graph itself is less clean than we had hoped, there were some difficulties encountered getting the software to generate a dashed line in this case. Nonetheless, comparing to the graph of the continuous time simulations we can see the results are favorable. The main differences in the simulations are the time delay visible in the digital simulation vs. the analog simulation. This represents the effect of the ZOH whose function is to hold the value of the sample amplitude for the time between samples so that the plant can recognize an analog input. Part 4: Xcos simulation of the analog and digital controllers with comment on disturbance rejection: The Xcos internal block diagram of the electric car:

(Input 1: Armature Voltage(V), Input 2: Disturbance Torque(N*m), Output 1: Armature Current(A), Output 2: Velcity (m/s))

(Analog compensation block diagram)

With disturbance grounded

With unit step disturbance injected at time t=0

Digital Compensator Block Diagram

With disturbance grounded

With magnitude 5 step disturbance injected at time t=0

With Disturbance grounded

With a magnitude 2 disturbance injected at time t=0

Disturbance grounded

After magnitude 2 disturbance injected at time t=0 Conclusion: In the above graphs each situation was simulated individually to help illustrate the respective compensators performance in closed loop along with the disturbance rejection properties to a step. In the case of the digital compensators it is apparent that there is a distortion in the gain and time parameters due to the effects of the sample and hold. These effects would need to be accounted for, either in the forward or feedback paths to improve on each of these defects. Nonetheless, the basic performance of each compensator remains the same. The disturbance rejection is excellent in all cases as no major change in either the transient or steady-state response was changed. Overall, the digital compensation technique is a very good approximation to the analog type assuming an appropriate level of skill of the designer. The improvements to such designs could be made give a more expansive tool set of digital control design techniques.

Thomas Heideman 00914215 Date 05/05/2011

Simulation of Electric Car using Scilab

EE 368

Minnesota State University at Mankato

College of Electrical and Computer Engineering Technology