Basic Operational Characteristics and

parameters

• Digital components are called “Integrated circuits”. They

are implemented using transistors.
• In Digital electronics, transistors are always configured to
work in switching modes.
• The type of transistor being used defines the technology:
– TTL (transistor-transistor-logic) for bipolar transistors
– CMOS (complementary MOS) for MOSFET transistors.
• MOSFET = metal-oxide semiconductor field-effect transistor

• The following figure show an IC packages that contains

“NAND” gates.
IC Package containing NAND Gates.
 Logic Levels
• The concept of logic levels is used to
represent logic variables in digital electronic
circuits.
• There are four different logic-level
specifications:
– VIL (Voltage input Low)
– VIH (Voltage input high)
– VOL (Voltage output low)
– VOH (Voltage output high)

Figures show the CMOS and TTL logic Levels respectively.

Inputs and output logic
levels for CMOS
 Input and output Logic levels for TTL

Figures show clearly that these two technology don’t support all the
ranges of voltages. If an input falls into the unallowed region the
behavior of the circuit is unpredictable, therefore its output doesn’t
represent a valuable information
 Noise
• Noise is unwanted voltage that is included in
electrical circuits and can present a threat to a proper
operation of the circuit.
• Examples of noise:
– Thermal noise
– Electromagnetic noise
– Power-line voltage fluctuation noise
• In order not to be adversely affected by noise, a logic
circuit must have a certain amount of noise immunity.
• The following figure shows some of the
consequences of noise on a logic gate.
 • Noise – unwanted variations of voltages and
currents at the logic nodes
• from two wires placed side by side
– capacitive coupling v(t)

• voltage change on one wire can

influence signal on the neighboring wire
• cross talk
i(t)
– inductive coupling
• current change on one wire can
influence signal on the neighboring wire

VDD
• from noise on the power and ground supply rails
– can influence signal levels in the gate
 For robust circuits, we want the “0” and “1” intervals to be
a s large as possible
VDD VDD

VOHmin "1"
NMH = VOHmin - VIHmin
VIHmin
Noise Margin High
Undefined
VILmax Region
Noise Margin Low
NML = VILmax - VOLmax
VOLmax
"0"
Gnd Gnd
Gate Output Gate Input

 Large noise margins are desirable, but not sufficient …

 Noise Immunity
• Noise margin expresses the ability of a circuit to
overpower a noise source
– noise sources: supply noise, cross talk, interference, offset
• Absolute noise margin values are deceptive
– a floating node is more easily disturbed than a node driven
by a low impedance (in terms of voltage)

• Noise immunity expresses the ability of the system to

process and transmit information correctly in the
presence of noise

• For good noise immunity, the signal swing (i.e., the

difference between VOH and VOL) and the noise margin
have to be large enough to overpower the impact of
fixed sources of noise
 Static Gate Behavior
• Steady-state parameters of a gate – static behavior –
tell how robust a circuit is with respect to both variations
in the manufacturing process and to noise disturbances.
• Digital circuits perform operations on Boolean variables
x {0,1}
• A logical variable is associated with a nominal voltage
level for each logic state
1  VOH and 0  VOL

! = complement
VOH = ! (VOL)
V(x) V(y)
VOL = ! (VOH)

• Difference between VOH and VOL is the logic

or signal swing Vsw
 DC Operation
Voltage Transfer Characteristics (VTC)
 Plot of output voltage as a function of the input voltage

V(y) V(x) V(y)

f
VOH = f (VIL)
V(y)=V(x)

Switching Threshold
VM

VOL = f (VIH)

VIL VIH V(x)

 Mapping Logic Levels to the Voltage
Domain
 The regions of acceptable high and low voltages are
delimited by VIH and VIL that represent the points on the
VTC curve where the gain = -1

V(y)
"1" VOH Slope = -1
VOH
VIH

Undefined
Region
Slope = -1
VIL
VOL
"0" VOL
VIL VIH V(x)
 Directivity

• A gate must be undirectional: changes in an output

level should not appear at any unchanging input of the
same circuit
– In real circuits full directivity is an illusion (e.g., due to capacitive
coupling between inputs and outputs)

• Key metrics: output impedance of the driver and input

impedance of the receiver
– ideally, the output impedance of the driver should be zero
– input impedance of the receiver should be infinity
 Fan-In and Fan-Out
 Fan-out – number of load gates
connected to the output of the
driving gate
 gates with large fan-out are slower
N

 Fan-in – the number of inputs to

the gate M
 gates with large fan-in are bigger
and slower
 Logic Levels: Practical Scenario
• The two sets of levels are motivated by these
Valid
scenarios
input
VOHMIN VIHMIN Valid
RTH output Scenario 1:
Rline Source outputs logic
Vcc
RIN high at lowest threshold,
Vdrop VOHMIN
I

SOURCE SINK

Valid
input Vcc Scenario 2:
Valid
VOLMAX VILMAX
output
Source outputs logic low
RTHL
Rline at highest threshold,
RIN VOLMAX

SINK SOURCE
 DC Loading
• The output high and low limits are exceeded only if a device
output is heavily loaded. Logic device loading is specified by
– maximum current
– Fanout := max. number of similar devices that can be connected
to a load without exceeding high and low state current limits

Current Specs
IOHMAX Max source current for which VOH  VOHMIN (valid output high)

IOLMAX Max sink current for which VOL  VOLMAX (valid output low)

IIHMAX Max input current for VIH  VIHMIN (valid input high)

IILMAX Max input current for which VIL  VILMAX (valid input low)
 DC Loading: Current specs
• Scenario 1: Output high
Valid
connected to more than one
input IIHMAX1 sink. The current outputted
1
Vo > VOHMIN by the source increases with
the number of sinks.
Io < IOHMAX
Io = Iinj = nIin (for n similar
sinks)

n
IIHMAXn
• Scenario 2: Output low
Valid connected to more than one
input IILMAX1
1
sink. Note that the current
Vo < VOLMAX
now flows into the output
terminal (logic source
Io < IOLMAX becomes a current sink).
Again current increases with
the number of logic sinks.
n
Io = Iinj = nIin (for n similar
IILMAXn
sinks)
 DC Loading: Fanout
• Each gate input requires a Fanout calculation
certain amount of current to –Low state fanout, nFlow:= maximum
number of similar gates that can be driven
maintain it in the LOW state or low so that Vo < VOLMAX
in the HIGH state.
– IIL and IIH –High state fanout, nFhigh:= maximum
number of similar gates that can be driven
– These are specified by the high so that Vo > VOHMIN
manufacturer.
–Need to do current loading calculation for
non-gate loads (LEDs, termination
resistors, etc.)
 I OL maxdriver 
nFlow  
  I ILdriven 
Fanout, nF  minnFlow , nFhigh 
 I OH max driver 
nFhigh  
  IH driven 
I
 The Ideal Inverter
• The ideal gate should have
– infinite gain in the transition region
– a gate threshold located in the middle of the logic swing
– high and low noise margins equal to half the swing
– input and output impedances of infinity and zero, resp.

Vout

Ri = 

Ro = 0

g=- Fanout = 

NMH = NML = VDD/2

Vin
 Delay Definitions
Vin Vout

Vin
Propagation delay?
input
waveform

Vout

output
signal slopes?
waveform

t
 Delay Definitions
Vin Vout

Vin
Propagation delay
input 50% tp = (tpHL + tpLH)/2
waveform

t
tpHL tpLH
Vout
90%
output
50% signal slopes
waveform
10%
t
tf tr
 Modeling Propagation Delay
• Model circuit as first-order RC network

vout (t) = (1 – e–t/)V

R
where  = RC
vout
C
Time to reach 50% point is
vin
t = ln(2)  = 0.69 

Time to reach 90% point is

t = ln(9)  = 2.2 

• Matches the delay of an inverter gate

 Power and Energy Dissipation
• Power consumption: how much energy is consumed
per operation and how much heat the circuit
dissipates
– supply line sizing (determined by peak power)
Ppeak = Vddipeak
– battery lifetime (determined by average power dissipation)
p(t) = v(t)i(t) = Vddi(t) Pavg= 1/T  p(t) dt = Vdd/T  idd(t) dt
– packaging and cooling requirements
• Two important components: static and dynamic
• Propagation delay and the power consumption of a gate
are related
• Propagation delay is (mostly) determined by the speed
at which a given amount of energy can be stored on the
gate capacitors
– the faster the energy transfer (higher power dissipation) the
faster the gate

• For a given technology and gate topology, the product

of the power consumption and the propagation delay
is a constant
– Power-delay product (PDP) – energy consumed by the gate
per switching event
• An ideal gate is one that is fast and consumes little
energy, so the ultimate quality metric is
– Energy-delay product (EDP) = power-delay 2