Release 8.2i - xst I.31 Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.

--> Parameter TMPDIR set to ./xst/projnav.tmp CPU : 0.00 / 0.13 s | Elapsed : 0.00 / 1.00 s

--> Parameter xsthdpdir set to ./xst CPU : 0.00 / 0.13 s | Elapsed : 0.00 / 1.00 s

--> Reading design: topmul.prj

TABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Compilation 3) Design Hierarchy Analysis 4) HDL Analysis 5) HDL Synthesis 5.1) HDL Synthesis Report 6) Advanced HDL Synthesis 6.1) Advanced HDL Synthesis Report 7) Low Level Synthesis 8) Partition Report 9) Final Report 9.1) Device utilization summary 9.2) TIMING REPORT

=========================================================================

Synthesis Options Summary

========================================================================= ---- Source Parameters Input File Name Input Format : "topmul.prj" : mixed

Ignore Synthesis Constraint File : NO

---- Target Parameters Output File Name Output Format Target Device : "topmul" : NGC : xc3s100e-5-vq100

---- Source Options Top Module Name Automatic FSM Extraction FSM Encoding Algorithm FSM Style RAM Extraction RAM Style ROM Extraction Mux Style Decoder Extraction Priority Encoder Extraction Shift Register Extraction Logical Shifter Extraction XOR Collapsing ROM Style : lut : Yes : Auto : Yes : Auto : YES : YES : YES : YES : YES : Auto : topmul : YES : Auto

Mux Extraction Resource Sharing Multiplier Style

: YES : YES : auto : No

Automatic Register Balancing

---- Target Options Add IO Buffers Global Maximum Fanout Add Generic Clock Buffer(BUFG) Register Duplication Slice Packing : YES : YES : auto : YES : YES : 500 :8

Pack IO Registers into IOBs Equivalent register Removal

---- General Options Optimization Goal Optimization Effort Keep Hierarchy RTL Output Global Optimization Write Timing Constraints Hierarchy Separator Bus Delimiter Case Specifier Slice Utilization Ratio Slice Utilization Ratio Delta : Speed :1 : NO : Yes : AllClockNets : NO :/ : <> : maintain : 100 :5

---- Other Options lso Read Cores cross_clock_analysis verilog2001 safe_implementation : topmul.lso : YES : NO : YES : No

Optimize Instantiated Primitives : NO use_clock_enable use_sync_set use_sync_reset : Yes : Yes : Yes

=========================================================================

========================================================================= * HDL Compilation *

========================================================================= Compiling vhdl file "C:/Xilinx/123/1234.vhd" in Library work. Architecture fpupack of Entity fpupack is up to date. Architecture top1 of Entity topmul is up to date. Architecture rtl of Entity post_norm_mul is up to date. Architecture rtl of Entity serial_mul is up to date. Architecture rtl of Entity mul_24 is up to date. Architecture rtl of Entity pre_norm_mul is up to date.

========================================================================= * Design Hierarchy Analysis *

========================================================================= Analyzing hierarchy for entity <topmul> in library <work> (architecture <top1>).

Analyzing hierarchy for entity <pre_norm_mul> in library <work> (architecture <rtl>).

Analyzing hierarchy for entity <mul_24> in library <work> (architecture <rtl>).

Analyzing hierarchy for entity <serial_mul> in library <work> (architecture <rtl>).

Analyzing hierarchy for entity <post_norm_mul> in library <work> (architecture <rtl>).

Building hierarchy successfully finished.

========================================================================= * HDL Analysis *

========================================================================= Analyzing Entity <topmul> in library <work> (Architecture <top1>). WARNING:Xst:753 - "C:/Xilinx/123/1234.vhd" line 214: Unconnected output port 'ready_o' of component 'mul_24'. WARNING:Xst:753 - "C:/Xilinx/123/1234.vhd" line 226: Unconnected output port 'ready_o' of component 'serial_mul'. Entity <topmul> analyzed. Unit <topmul> generated.

Analyzing Entity <pre_norm_mul> in library <work> (Architecture <rtl>). Entity <pre_norm_mul> analyzed. Unit <pre_norm_mul> generated.

Analyzing Entity <mul_24> in library <work> (Architecture <rtl>). Entity <mul_24> analyzed. Unit <mul_24> generated.

Analyzing Entity <serial_mul> in library <work> (Architecture <rtl>). Entity <serial_mul> analyzed. Unit <serial_mul> generated.

Analyzing Entity <post_norm_mul> in library <work> (Architecture <rtl>). Entity <post_norm_mul> analyzed. Unit <post_norm_mul> generated.

========================================================================= * HDL Synthesis *

=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <pre_norm_mul>. Related source file is "C:/Xilinx/123/1234.vhd". WARNING:Xst:647 - Input <opb_i<31>> is never used. WARNING:Xst:647 - Input <opa_i<31>> is never used. Found 10-bit register for signal <exp_10_o>. Found 10-bit adder for signal <$addsub0000> created at line 830. Found 10-bit subtractor for signal <s_exp_10_o>. Found 10-bit adder for signal <s_expa_in>. Found 10-bit adder for signal <s_expb_in>. Summary: inferred 10 D-type flip-flop(s). inferred 4 Adder/Subtractor(s). Unit <pre_norm_mul> synthesized.

Synthesizing Unit <mul_24>. Related source file is "C:/Xilinx/123/1234.vhd". Found 24-bit adder for signal <$add0000> created at line 752. Found 48-bit adder for signal <$addsub0000>. Found 48-bit adder for signal <$addsub0001>. Found 24-bit adder for signal <$addsub0002>. Found 24-bit adder for signal <$addsub0003>. Found 6x6-bit multiplier for signal <$mult0000> created at line 738. Found 6x6-bit multiplier for signal <$mult0001> created at line 739. Found 6x6-bit multiplier for signal <$mult0002> created at line 740. Found 6x6-bit multiplier for signal <$mult0003> created at line 741. Found 1-bit 4-to-1 multiplexer for signal <$mux0000<0>>. Found 1-bit 4-to-1 multiplexer for signal <$mux0001<0>>. Found 1-bit 4-to-1 multiplexer for signal <$mux0002<0>>. Found 1-bit 4-to-1 multiplexer for signal <$mux0003<0>>. Found 1-bit 4-to-1 multiplexer for signal <$mux0004<0>>. Found 1-bit 4-to-1 multiplexer for signal <$mux0005<0>>. Found 1-bit 4-to-1 multiplexer for signal <$mux0006<0>>. Found 1-bit 4-to-1 multiplexer for signal <$mux0007<0>>. Found 3-bit up counter for signal <count>. Found 96-bit register for signal <prod2<0>>. Found 96-bit register for signal <prod2<1>>. Found 96-bit register for signal <prod2<2>>. Found 96-bit register for signal <prod2<3>>. Found 48-bit adder for signal <prod_a_b<4>>.

Found 24-bit register for signal <s_fracta_i>. Found 24-bit register for signal <s_fractb_i>. Found 1-bit register for signal <s_ready_o>. Found 1-bit xor2 for signal <s_sign_o>. Found 1-bit register for signal <s_signa_i>. Found 1-bit register for signal <s_signb_i>. Found 1-bit register for signal <s_start_i>. Found 1-bit register for signal <s_state<0>>. Found 96-bit register for signal <sum>. Summary: inferred 1 Counter(s). inferred 533 D-type flip-flop(s). inferred 6 Adder/Subtractor(s). inferred 4 Multiplier(s). inferred 8 Multiplexer(s). Unit <mul_24> synthesized.

Synthesizing Unit <serial_mul>. Related source file is "C:/Xilinx/123/1234.vhd". WARNING:Xst:646 - Signal <s_signa_i> is assigned but never used. WARNING:Xst:646 - Signal <s_signb_i> is assigned but never used. Found 1-bit register for signal <sign_o>. Found 48-bit register for signal <fract_o>. Found 1-bit register for signal <ready_o>. Found 48-bit adder for signal <$addsub0000> created at line 578. Found 48-bit shifter logical left for signal <$shift0000> created at line 576.

Found 48-bit shifter logical left for signal <$shift0001> created at line 576. Found 1-bit 24-to-1 multiplexer for signal <$varindex0000> created at line 568. Found 5-bit up counter for signal <s_count>. Found 48-bit register for signal <s_fract_o>. Found 24-bit register for signal <s_fracta_i>. Found 24-bit register for signal <s_fractb_i>. Found 1-bit register for signal <s_ready_o>. Found 1-bit xor2 for signal <s_sign_o>. Found 1-bit register for signal <s_start_i>. Found 1-bit register for signal <s_state<0>>. Summary: inferred 1 Counter(s). inferred 149 D-type flip-flop(s). inferred 1 Adder/Subtractor(s). inferred 1 Multiplexer(s). inferred 2 Combinational logic shifter(s). Unit <serial_mul> synthesized.

Synthesizing Unit <post_norm_mul>. Related source file is "C:/Xilinx/123/1234.vhd". WARNING:Xst:646 - Signal <s_opa_i<31>> is assigned but never used. WARNING:Xst:646 - Signal <s_opb_i<31>> is assigned but never used. WARNING:Xst:646 - Signal <s_frac3<24:23>> is assigned but never used. Found 32-bit register for signal <output_o>. Found 1-bit register for signal <ine_o>. Found 6-bit adder for signal <$add0000> created at line 82.

Found 6-bit adder for signal <$add0001> created at line 82. Found 6-bit adder for signal <$add0002> created at line 82. Found 6-bit adder for signal <$add0003> created at line 82. Found 6-bit adder for signal <$add0004> created at line 82. Found 6-bit adder for signal <$add0005> created at line 82. Found 6-bit adder for signal <$add0006> created at line 82. Found 6-bit adder for signal <$add0007> created at line 82. Found 6-bit adder for signal <$add0008> created at line 82. Found 6-bit adder for signal <$add0009> created at line 82. Found 6-bit adder for signal <$add0010> created at line 82. Found 6-bit adder for signal <$add0011> created at line 82. Found 6-bit adder for signal <$add0012> created at line 82. Found 6-bit adder for signal <$add0013> created at line 82. Found 6-bit adder for signal <$add0014> created at line 82. Found 6-bit adder for signal <$add0015> created at line 82. Found 6-bit adder for signal <$add0016> created at line 82. Found 6-bit adder for signal <$add0017> created at line 82. Found 6-bit adder for signal <$add0018> created at line 82. Found 6-bit adder for signal <$add0019> created at line 82. Found 6-bit adder for signal <$add0020> created at line 82. Found 6-bit adder for signal <$add0021> created at line 82. Found 6-bit adder for signal <$add0022> created at line 82. Found 6-bit adder for signal <$add0023> created at line 82. Found 6-bit adder for signal <$add0024> created at line 82. Found 6-bit adder for signal <$add0025> created at line 82. Found 6-bit adder for signal <$add0026> created at line 82. Found 6-bit adder for signal <$add0027> created at line 82.

Found 6-bit adder for signal <$add0028> created at line 82. Found 6-bit adder for signal <$add0029> created at line 82. Found 6-bit adder for signal <$add0030> created at line 82. Found 6-bit adder for signal <$add0031> created at line 82. Found 6-bit adder for signal <$add0032> created at line 82. Found 6-bit adder for signal <$add0033> created at line 82. Found 6-bit adder for signal <$add0034> created at line 82. Found 6-bit adder for signal <$add0035> created at line 82. Found 6-bit adder for signal <$add0036> created at line 82. Found 6-bit adder for signal <$add0037> created at line 82. Found 6-bit adder for signal <$add0038> created at line 82. Found 6-bit adder for signal <$add0039> created at line 82. Found 6-bit adder for signal <$add0040> created at line 82. Found 6-bit adder for signal <$add0041> created at line 82. Found 6-bit adder for signal <$add0042> created at line 82. Found 6-bit adder for signal <$add0043> created at line 82. Found 6-bit adder for signal <$add0044> created at line 82. Found 6-bit adder for signal <$add0045> created at line 82. Found 6-bit adder for signal <$add0046> created at line 67. Found 6-bit adder for signal <$add0047> created at line 67. Found 6-bit adder for signal <$add0048> created at line 67. Found 6-bit adder for signal <$add0049> created at line 67. Found 6-bit adder for signal <$add0050> created at line 67. Found 6-bit adder for signal <$add0051> created at line 67. Found 6-bit adder for signal <$add0052> created at line 67. Found 6-bit adder for signal <$add0053> created at line 67. Found 6-bit adder for signal <$add0054> created at line 67.

Found 6-bit adder for signal <$add0055> created at line 67. Found 6-bit adder for signal <$add0056> created at line 67. Found 6-bit adder for signal <$add0057> created at line 67. Found 6-bit adder for signal <$add0058> created at line 67. Found 6-bit adder for signal <$add0059> created at line 67. Found 6-bit adder for signal <$add0060> created at line 67. Found 6-bit adder for signal <$add0061> created at line 67. Found 6-bit adder for signal <$add0062> created at line 67. Found 6-bit adder for signal <$add0063> created at line 67. Found 6-bit adder for signal <$add0064> created at line 67. Found 6-bit adder for signal <$add0065> created at line 67. Found 6-bit adder for signal <$add0066> created at line 67. Found 6-bit adder for signal <$add0067> created at line 67. Found 6-bit adder for signal <$add0068> created at line 67. Found 6-bit adder for signal <$add0069> created at line 67. Found 6-bit adder for signal <$add0070> created at line 67. Found 6-bit adder for signal <$add0071> created at line 67. Found 6-bit adder for signal <$add0072> created at line 67. Found 6-bit adder for signal <$add0073> created at line 67. Found 6-bit adder for signal <$add0074> created at line 67. Found 6-bit adder for signal <$add0075> created at line 67. Found 6-bit adder for signal <$add0076> created at line 67. Found 6-bit adder for signal <$add0077> created at line 67. Found 6-bit adder for signal <$add0078> created at line 67. Found 6-bit adder for signal <$add0079> created at line 67. Found 6-bit adder for signal <$add0080> created at line 67. Found 6-bit adder for signal <$add0081> created at line 67.

Found 6-bit adder for signal <$add0082> created at line 67. Found 6-bit adder for signal <$add0083> created at line 67. Found 6-bit adder for signal <$add0084> created at line 67. Found 6-bit adder for signal <$add0085> created at line 67. Found 6-bit adder for signal <$add0086> created at line 67. Found 6-bit adder for signal <$add0087> created at line 67. Found 6-bit adder for signal <$add0088> created at line 67. Found 6-bit adder for signal <$add0089> created at line 67. Found 6-bit adder for signal <$addsub0000> created at line 411. Found 9-bit adder for signal <$addsub0001> created at line 447. Found 9-bit subtractor for signal <$addsub0002> created at line 406. Found 10-bit adder for signal <$addsub0003> created at line 362. Found 10-bit adder for signal <$addsub0004> created at line 362. Found 10-bit subtractor for signal <$addsub0005> created at line 368. Found 6-bit adder for signal <$addsub0006> created at line 67. Found 6-bit adder for signal <$addsub0007> created at line 82. Found 25-bit adder for signal <$addsub0008> created at line 436. Found 6-bit comparator greater for signal <$cmp_gt0000> created at line 411. Found 6-bit 4-to-1 multiplexer for signal <$mux0001> created at line 66. Found 6-bit 4-to-1 multiplexer for signal <$mux0047> created at line 81. Found 9-bit 4-to-1 multiplexer for signal <$mux0113>. Found 48-bit shifter logical right for signal <$shift0000> created at line 399. Found 48-bit shifter logical left for signal <$shift0001> created at line 401. Found 10-bit register for signal <s_exp_10_i>. Found 10-bit adder for signal <s_exp_10a>. Found 10-bit subtractor for signal <s_exp_10b>. Found 8-bit register for signal <s_expa>.

Found 8-bit register for signal <s_expb>. Found 9-bit register for signal <s_expo1>. Found 48-bit register for signal <s_frac2a>. Found 25-bit register for signal <s_frac_rnd>. Found 48-bit register for signal <s_fract_48_i>. Found 32-bit register for signal <s_opa_i>. Found 32-bit register for signal <s_opb_i>. Found 6-bit register for signal <s_r_zeros>. Found 2-bit register for signal <s_rmode_i>. Found 1-bit 4-to-1 multiplexer for signal <s_roundup>. Found 6-bit register for signal <s_shl2>. Found 6-bit register for signal <s_shr2>. Found 1-bit register for signal <s_sign_i>. Found 6-bit register for signal <s_zeros>. Summary: inferred 271 D-type flip-flop(s). inferred 101 Adder/Subtractor(s). inferred 1 Comparator(s). inferred 22 Multiplexer(s). inferred 2 Combinational logic shifter(s). Unit <post_norm_mul> synthesized.

Synthesizing Unit <topmul>. Related source file is "C:/Xilinx/123/1234.vhd". WARNING:Xst:1306 - Output <ready_o> is never assigned. WARNING:Xst:646 - Signal <mul_sign> is assigned but never used.

WARNING:Xst:1780 - Signal <post_norm_mul_output> is never used or assigned. WARNING:Xst:646 - Signal <serial_mul_fract_48> is assigned but never used. WARNING:Xst:1780 - Signal <post_norm_mul_ine> is never used or assigned. WARNING:Xst:646 - Signal <serial_mul_sign> is assigned but never used. Unit <topmul> synthesized.

========================================================================= HDL Synthesis Report

Macro Statistics # Multipliers 6x6-bit multiplier # Adders/Subtractors 10-bit adder 10-bit subtractor 24-bit adder 25-bit adder 48-bit adder 6-bit adder 9-bit adder 9-bit subtractor # Counters 3-bit up counter 5-bit up counter # Registers 1-bit register :6 :3 :3 :1 :4 : 93 :1 :1 :2 :1 :1 : 54 : 12 :4 :4 : 112

10-bit register 2-bit register 24-bit register 25-bit register 32-bit register 48-bit register 6-bit register 8-bit register 9-bit register # Comparators 6-bit comparator greater # Multiplexers 1-bit 24-to-1 multiplexer 1-bit 4-to-1 multiplexer 6-bit 4-to-1 multiplexer 9-bit 4-to-1 multiplexer # Logic shifters 48-bit shifter logical left 48-bit shifter logical right # Xors 1-bit xor2 :2

:2 :1 : 24 :1 :3 :4 :4 :2 :1 :1 :1 : 13 :1 :9 :2 :1 :4 :3 :1

:2

=========================================================================

========================================================================= * Advanced HDL Synthesis *

=========================================================================

Loading device for application Rf_Device from file '3s100e.nph' in environment C:\Xilinx. WARNING:Xst:2404 - FFs/Latches <prod2<3>_2<23:18>> (without init value) have a constant value of 0 in block <mul_24>. WARNING:Xst:2404 - FFs/Latches <prod2<3>_1<23:18>> (without init value) have a constant value of 0 in block <mul_24>. WARNING:Xst:2404 - FFs/Latches <prod2<3>_3<23:12>> (without init value) have a constant value of 0 in block <mul_24>. WARNING:Xst:2404 - FFs/Latches <prod2<0>_1<23:18>> (without init value) have a constant value of 0 in block <mul_24>. WARNING:Xst:2404 - FFs/Latches <prod2<0>_3<23:12>> (without init value) have a constant value of 0 in block <mul_24>. WARNING:Xst:2404 - FFs/Latches <prod2<0>_2<23:18>> (without init value) have a constant value of 0 in block <mul_24>. WARNING:Xst:2404 - FFs/Latches <prod2<1>_1<23:18>> (without init value) have a constant value of 0 in block <mul_24>. WARNING:Xst:2404 - FFs/Latches <prod2<1>_2<23:18>> (without init value) have a constant value of 0 in block <mul_24>. WARNING:Xst:2404 - FFs/Latches <prod2<1>_3<23:12>> (without init value) have a constant value of 0 in block <mul_24>. WARNING:Xst:2404 - FFs/Latches <prod2<2>_2<23:18>> (without init value) have a constant value of 0 in block <mul_24>. WARNING:Xst:2404 - FFs/Latches <prod2<2>_1<23:18>> (without init value) have a constant value of 0 in block <mul_24>. WARNING:Xst:2404 - FFs/Latches <prod2<2>_3<23:12>> (without init value) have a constant value of 0 in block <mul_24>. WARNING:Xst:1291 - FF/Latch <s_opa_i_31> is unconnected in block <post_norm_mul>. WARNING:Xst:1291 - FF/Latch <s_opb_i_31> is unconnected in block <post_norm_mul>. INFO:Xst:2261 - The FF/Latch <s_expb_7> in Unit <post_norm_mul> is equivalent to the following FF/Latch, which will be removed : <s_opb_i_30> INFO:Xst:2261 - The FF/Latch <s_expb_6> in Unit <post_norm_mul> is equivalent to the following FF/Latch, which will be removed : <s_opb_i_29>

INFO:Xst:2261 - The FF/Latch <s_expb_2> in Unit <post_norm_mul> is equivalent to the following FF/Latch, which will be removed : <s_opb_i_25> INFO:Xst:2261 - The FF/Latch <s_expb_1> in Unit <post_norm_mul> is equivalent to the following FF/Latch, which will be removed : <s_opb_i_24> INFO:Xst:2261 - The FF/Latch <s_opa_i_27> in Unit <post_norm_mul> is equivalent to the following FF/Latch, which will be removed : <s_expa_4> INFO:Xst:2261 - The FF/Latch <s_opa_i_30> in Unit <post_norm_mul> is equivalent to the following FF/Latch, which will be removed : <s_expa_7> INFO:Xst:2261 - The FF/Latch <s_opa_i_26> in Unit <post_norm_mul> is equivalent to the following FF/Latch, which will be removed : <s_expa_3> INFO:Xst:2261 - The FF/Latch <s_expb_0> in Unit <post_norm_mul> is equivalent to the following FF/Latch, which will be removed : <s_opb_i_23> INFO:Xst:2261 - The FF/Latch <s_opa_i_25> in Unit <post_norm_mul> is equivalent to the following FF/Latch, which will be removed : <s_expa_2> INFO:Xst:2261 - The FF/Latch <s_opa_i_29> in Unit <post_norm_mul> is equivalent to the following FF/Latch, which will be removed : <s_expa_6> INFO:Xst:2261 - The FF/Latch <s_expb_5> in Unit <post_norm_mul> is equivalent to the following FF/Latch, which will be removed : <s_opb_i_28> INFO:Xst:2261 - The FF/Latch <s_opa_i_28> in Unit <post_norm_mul> is equivalent to the following FF/Latch, which will be removed : <s_expa_5> INFO:Xst:2261 - The FF/Latch <s_opa_i_24> in Unit <post_norm_mul> is equivalent to the following FF/Latch, which will be removed : <s_expa_1> INFO:Xst:2261 - The FF/Latch <s_expb_4> in Unit <post_norm_mul> is equivalent to the following FF/Latch, which will be removed : <s_opb_i_27> INFO:Xst:2261 - The FF/Latch <s_opa_i_23> in Unit <post_norm_mul> is equivalent to the following FF/Latch, which will be removed : <s_expa_0> INFO:Xst:2261 - The FF/Latch <s_expb_3> in Unit <post_norm_mul> is equivalent to the following FF/Latch, which will be removed : <s_opb_i_26> WARNING:Xst:1710 - FF/Latch <prod2<1>_1_12> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<1>_1_13> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<1>_1_14> (without init value) has a constant value of 0 in block <mul_24>.

WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<1>_1_15> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<1>_1_16> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<1>_1_17> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<3>_1_12> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<3>_1_13> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<3>_1_14> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<3>_1_15> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<3>_1_16> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<3>_1_17> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<0>_1_12> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<0>_1_13> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<0>_1_14> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<0>_1_15> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<0>_1_16> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<0>_1_17> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<3>_2_12> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<3>_2_13> (without init value) has a constant value of 0 in block <mul_24>.

WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<3>_2_14> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<3>_2_15> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<3>_2_16> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<3>_2_17> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<2>_1_12> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<2>_1_13> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<2>_1_14> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<2>_1_15> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<2>_1_16> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<2>_1_17> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<1>_2_12> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<1>_2_13> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<1>_2_14> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<1>_2_15> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<1>_2_16> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<1>_2_17> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<2>_2_12> (without init value) has a constant value of 0 in block <mul_24>.

WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<2>_2_13> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<2>_2_14> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<2>_2_15> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<2>_2_16> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<2>_2_17> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<0>_2_12> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<0>_2_13> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<0>_2_14> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<0>_2_15> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<0>_2_16> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<0>_2_17> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<0>_0_11> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<0>_0_10> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<0>_0_9> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<0>_0_8> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<0>_0_7> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<0>_0_6> (without init value) has a constant value of 0 in block <mul_24>.

WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<0>_0_5> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<0>_0_4> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<0>_0_3> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<0>_0_2> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<0>_0_1> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<0>_0_0> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<3>_0_11> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<3>_0_10> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<3>_0_9> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<3>_0_8> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<3>_0_7> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<3>_0_6> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<3>_0_5> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<3>_0_4> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<3>_0_3> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<3>_0_2> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<3>_0_1> (without init value) has a constant value of 0 in block <mul_24>.

WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<3>_0_0> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<2>_0_11> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<2>_0_10> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<2>_0_9> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<2>_0_8> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<2>_0_7> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<2>_0_6> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<2>_0_5> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<2>_0_4> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<2>_0_3> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<2>_0_2> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<2>_0_1> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<2>_0_0> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<1>_0_11> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<1>_0_10> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<1>_0_9> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<1>_0_8> (without init value) has a constant value of 0 in block <mul_24>.

WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<1>_0_7> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<1>_0_6> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<1>_0_5> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<1>_0_4> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<1>_0_3> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<1>_0_2> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<1>_0_1> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <prod2<1>_0_0> (without init value) has a constant value of 0 in block <mul_24>. WARNING:Xst:1291 - FF/Latch <s_ready_o> is unconnected in block <i_mul_24>. WARNING:Xst:1291 - FF/Latch <s_ready_o> is unconnected in block <i_serial_mul>. WARNING:Xst:1291 - FF/Latch <sign_o> is unconnected in block <i_serial_mul>. WARNING:Xst:1291 - FF/Latch <ready_o> is unconnected in block <i_serial_mul>. WARNING:Xst:1291 - FF/Latch <fract_o_0> is unconnected in block <i_serial_mul>. WARNING:Xst:1291 - FF/Latch <fract_o_1> is unconnected in block <i_serial_mul>. WARNING:Xst:1291 - FF/Latch <fract_o_2> is unconnected in block <i_serial_mul>. WARNING:Xst:1291 - FF/Latch <fract_o_3> is unconnected in block <i_serial_mul>. WARNING:Xst:1291 - FF/Latch <fract_o_4> is unconnected in block <i_serial_mul>. WARNING:Xst:1291 - FF/Latch <fract_o_5> is unconnected in block <i_serial_mul>. WARNING:Xst:1291 - FF/Latch <fract_o_6> is unconnected in block <i_serial_mul>. WARNING:Xst:1291 - FF/Latch <fract_o_7> is unconnected in block <i_serial_mul>. WARNING:Xst:1291 - FF/Latch <fract_o_8> is unconnected in block <i_serial_mul>. WARNING:Xst:1291 - FF/Latch <fract_o_9> is unconnected in block <i_serial_mul>. WARNING:Xst:1291 - FF/Latch <fract_o_10> is unconnected in block <i_serial_mul>.

WARNING:Xst:1291 - FF/Latch <fract_o_11> is unconnected in block <i_serial_mul>. WARNING:Xst:1291 - FF/Latch <fract_o_12> is unconnected in block <i_serial_mul>. WARNING:Xst:1291 - FF/Latch <fract_o_13> is unconnected in block <i_serial_mul>. WARNING:Xst:1291 - FF/Latch <fract_o_14> is unconnected in block <i_serial_mul>. WARNING:Xst:1291 - FF/Latch <fract_o_15> is unconnected in block <i_serial_mul>. WARNING:Xst:1291 - FF/Latch <fract_o_16> is unconnected in block <i_serial_mul>. WARNING:Xst:1291 - FF/Latch <fract_o_17> is unconnected in block <i_serial_mul>. WARNING:Xst:1291 - FF/Latch <fract_o_18> is unconnected in block <i_serial_mul>. WARNING:Xst:1291 - FF/Latch <fract_o_19> is unconnected in block <i_serial_mul>. WARNING:Xst:1291 - FF/Latch <fract_o_20> is unconnected in block <i_serial_mul>. WARNING:Xst:1291 - FF/Latch <fract_o_21> is unconnected in block <i_serial_mul>. WARNING:Xst:1291 - FF/Latch <fract_o_22> is unconnected in block <i_serial_mul>. WARNING:Xst:1291 - FF/Latch <fract_o_23> is unconnected in block <i_serial_mul>. WARNING:Xst:1291 - FF/Latch <fract_o_24> is unconnected in block <i_serial_mul>. WARNING:Xst:1291 - FF/Latch <fract_o_25> is unconnected in block <i_serial_mul>. WARNING:Xst:1291 - FF/Latch <fract_o_26> is unconnected in block <i_serial_mul>. WARNING:Xst:1291 - FF/Latch <fract_o_27> is unconnected in block <i_serial_mul>. WARNING:Xst:1291 - FF/Latch <fract_o_28> is unconnected in block <i_serial_mul>. WARNING:Xst:1291 - FF/Latch <fract_o_29> is unconnected in block <i_serial_mul>. WARNING:Xst:1291 - FF/Latch <fract_o_30> is unconnected in block <i_serial_mul>. WARNING:Xst:1291 - FF/Latch <fract_o_31> is unconnected in block <i_serial_mul>. WARNING:Xst:1291 - FF/Latch <fract_o_32> is unconnected in block <i_serial_mul>. WARNING:Xst:1291 - FF/Latch <fract_o_33> is unconnected in block <i_serial_mul>. WARNING:Xst:1291 - FF/Latch <fract_o_34> is unconnected in block <i_serial_mul>. WARNING:Xst:1291 - FF/Latch <fract_o_35> is unconnected in block <i_serial_mul>. WARNING:Xst:1291 - FF/Latch <fract_o_36> is unconnected in block <i_serial_mul>. WARNING:Xst:1291 - FF/Latch <fract_o_37> is unconnected in block <i_serial_mul>.

WARNING:Xst:1291 - FF/Latch <fract_o_38> is unconnected in block <i_serial_mul>. WARNING:Xst:1291 - FF/Latch <fract_o_39> is unconnected in block <i_serial_mul>. WARNING:Xst:1291 - FF/Latch <fract_o_40> is unconnected in block <i_serial_mul>. WARNING:Xst:1291 - FF/Latch <fract_o_41> is unconnected in block <i_serial_mul>. WARNING:Xst:1291 - FF/Latch <fract_o_42> is unconnected in block <i_serial_mul>. WARNING:Xst:1291 - FF/Latch <fract_o_43> is unconnected in block <i_serial_mul>. WARNING:Xst:1291 - FF/Latch <fract_o_44> is unconnected in block <i_serial_mul>. WARNING:Xst:1291 - FF/Latch <fract_o_45> is unconnected in block <i_serial_mul>. WARNING:Xst:1291 - FF/Latch <fract_o_46> is unconnected in block <i_serial_mul>. WARNING:Xst:1291 - FF/Latch <fract_o_47> is unconnected in block <i_serial_mul>.

========================================================================= Advanced HDL Synthesis Report

Macro Statistics # Multipliers 6x6-bit multiplier # Adders/Subtractors 10-bit adder 10-bit subtractor 24-bit adder 25-bit adder 48-bit adder 6-bit adder 9-bit adder 9-bit subtractor # Counters :6 :3 :3 :1 :4 : 93 :1 :1 :2 :4 :4 : 112

3-bit up counter 5-bit up counter # Registers Flip-Flops # Comparators 6-bit comparator greater # Multiplexers 1-bit 24-to-1 multiplexer 1-bit 4-to-1 multiplexer 6-bit 4-to-1 multiplexer 9-bit 4-to-1 multiplexer # Logic shifters 48-bit shifter logical left 48-bit shifter logical right # Xors 1-bit xor2 :2 :2

:1 :1 : 762 : 762 :1 :1 : 13 :1 :9 :2 :1 :4 :3 :1

=========================================================================

========================================================================= * Low Level Synthesis *

========================================================================= WARNING:Xst:1710 - FF/Latch <s_expo1_8> (without init value) has a constant value of 0 in block <post_norm_mul>.

Optimizing unit <topmul> ...

Optimizing unit <serial_mul> ...

Optimizing unit <mul_24> ...

Optimizing unit <post_norm_mul> ...

Optimizing unit <pre_norm_mul> ...

Mapping all equations... WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_ready_o> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_start_i> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fracta_i_0> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fracta_i_1> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fracta_i_2> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fracta_i_3> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fracta_i_4> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fracta_i_5> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fracta_i_6> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fracta_i_7> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fracta_i_8> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fracta_i_9> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fracta_i_10> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fracta_i_11> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fracta_i_12> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fracta_i_13> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fracta_i_14> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fracta_i_15> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fracta_i_16> is unconnected in block <topmul>.

WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fracta_i_17> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fracta_i_18> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fracta_i_19> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fracta_i_20> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fracta_i_21> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fracta_i_22> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fracta_i_23> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fractb_i_0> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fractb_i_1> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fractb_i_2> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fractb_i_3> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fractb_i_4> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fractb_i_5> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fractb_i_6> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fractb_i_7> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fractb_i_8> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fractb_i_9> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fractb_i_10> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fractb_i_11> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fractb_i_12> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fractb_i_13> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fractb_i_14> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fractb_i_15> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fractb_i_16> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fractb_i_17> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fractb_i_18> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fractb_i_19> is unconnected in block <topmul>.

WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fractb_i_20> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fractb_i_21> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fractb_i_22> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fractb_i_23> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/sign_o> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_state_0> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/ready_o> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fract_o_0> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fract_o_1> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fract_o_2> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fract_o_3> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fract_o_4> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fract_o_5> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fract_o_6> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fract_o_7> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fract_o_8> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fract_o_9> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fract_o_10> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fract_o_11> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fract_o_12> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fract_o_13> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fract_o_14> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fract_o_15> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fract_o_16> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fract_o_17> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fract_o_18> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fract_o_19> is unconnected in block <topmul>.

WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fract_o_20> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fract_o_21> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fract_o_22> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fract_o_23> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fract_o_24> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fract_o_25> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fract_o_26> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fract_o_27> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fract_o_28> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fract_o_29> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fract_o_30> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fract_o_31> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fract_o_32> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fract_o_33> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fract_o_34> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fract_o_35> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fract_o_36> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fract_o_37> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fract_o_38> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fract_o_39> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fract_o_40> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fract_o_41> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fract_o_42> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fract_o_43> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fract_o_44> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fract_o_45> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fract_o_46> is unconnected in block <topmul>.

WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_fract_o_47> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/fract_o_0> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/fract_o_1> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/fract_o_2> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/fract_o_3> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/fract_o_4> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/fract_o_5> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/fract_o_6> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/fract_o_7> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/fract_o_8> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/fract_o_9> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/fract_o_10> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/fract_o_11> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/fract_o_12> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/fract_o_13> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/fract_o_14> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/fract_o_15> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/fract_o_16> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/fract_o_17> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/fract_o_18> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/fract_o_19> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/fract_o_20> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/fract_o_21> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/fract_o_22> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/fract_o_23> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/fract_o_24> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/fract_o_25> is unconnected in block <topmul>.

WARNING:Xst:1291 - FF/Latch <i_serial_mul/fract_o_26> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/fract_o_27> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/fract_o_28> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/fract_o_29> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/fract_o_30> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/fract_o_31> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/fract_o_32> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/fract_o_33> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/fract_o_34> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/fract_o_35> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/fract_o_36> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/fract_o_37> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/fract_o_38> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/fract_o_39> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/fract_o_40> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/fract_o_41> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/fract_o_42> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/fract_o_43> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/fract_o_44> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/fract_o_45> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/fract_o_46> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/fract_o_47> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_count_0> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_count_1> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_count_2> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_count_3> is unconnected in block <topmul>. WARNING:Xst:1291 - FF/Latch <i_serial_mul/s_count_4> is unconnected in block <topmul>.

WARNING:Xst:1291 - FF/Latch <i_mul_24/s_ready_o> is unconnected in block <topmul>. Building and optimizing final netlist ... INFO:Xst:2261 - The FF/Latch <i_mul_24/s_fracta_i_3> in Unit <topmul> is equivalent to the following FF/Latch, which will be removed : <i_post_norm_mul/s_opa_i_3> INFO:Xst:2261 - The FF/Latch <i_mul_24/s_fracta_i_2> in Unit <topmul> is equivalent to the following FF/Latch, which will be removed : <i_post_norm_mul/s_opa_i_2> INFO:Xst:2261 - The FF/Latch <i_mul_24/s_fractb_i_22> in Unit <topmul> is equivalent to the following FF/Latch, which will be removed : <i_post_norm_mul/s_opb_i_22> INFO:Xst:2261 - The FF/Latch <i_mul_24/s_fractb_i_6> in Unit <topmul> is equivalent to the following FF/Latch, which will be removed : <i_post_norm_mul/s_opb_i_6> INFO:Xst:2261 - The FF/Latch <i_mul_24/s_fractb_i_21> in Unit <topmul> is equivalent to the following FF/Latch, which will be removed : <i_post_norm_mul/s_opb_i_21> INFO:Xst:2261 - The FF/Latch <i_mul_24/s_fractb_i_17> in Unit <topmul> is equivalent to the following FF/Latch, which will be removed : <i_post_norm_mul/s_opb_i_17> INFO:Xst:2261 - The FF/Latch <i_mul_24/s_fractb_i_5> in Unit <topmul> is equivalent to the following FF/Latch, which will be removed : <i_post_norm_mul/s_opb_i_5> INFO:Xst:2261 - The FF/Latch <i_mul_24/s_fractb_i_20> in Unit <topmul> is equivalent to the following FF/Latch, which will be removed : <i_post_norm_mul/s_opb_i_20> INFO:Xst:2261 - The FF/Latch <i_mul_24/s_fractb_i_1> in Unit <topmul> is equivalent to the following FF/Latch, which will be removed : <i_post_norm_mul/s_opb_i_1> INFO:Xst:2261 - The FF/Latch <i_mul_24/s_fractb_i_16> in Unit <topmul> is equivalent to the following FF/Latch, which will be removed : <i_post_norm_mul/s_opb_i_16> INFO:Xst:2261 - The FF/Latch <i_mul_24/s_fractb_i_4> in Unit <topmul> is equivalent to the following FF/Latch, which will be removed : <i_post_norm_mul/s_opb_i_4> INFO:Xst:2261 - The FF/Latch <i_mul_24/s_fractb_i_0> in Unit <topmul> is equivalent to the following FF/Latch, which will be removed : <i_post_norm_mul/s_opb_i_0> INFO:Xst:2261 - The FF/Latch <i_mul_24/s_fractb_i_15> in Unit <topmul> is equivalent to the following FF/Latch, which will be removed : <i_post_norm_mul/s_opb_i_15> INFO:Xst:2261 - The FF/Latch <i_mul_24/s_fractb_i_11> in Unit <topmul> is equivalent to the following FF/Latch, which will be removed : <i_post_norm_mul/s_opb_i_11> INFO:Xst:2261 - The FF/Latch <i_mul_24/s_fractb_i_14> in Unit <topmul> is equivalent to the following FF/Latch, which will be removed : <i_post_norm_mul/s_opb_i_14> INFO:Xst:2261 - The FF/Latch <i_mul_24/s_fractb_i_10> in Unit <topmul> is equivalent to the following FF/Latch, which will be removed : <i_post_norm_mul/s_opb_i_10>

INFO:Xst:2261 - The FF/Latch <i_mul_24/s_fractb_i_19> in Unit <topmul> is equivalent to the following FF/Latch, which will be removed : <i_post_norm_mul/s_opb_i_19> INFO:Xst:2261 - The FF/Latch <i_mul_24/s_fractb_i_9> in Unit <topmul> is equivalent to the following FF/Latch, which will be removed : <i_post_norm_mul/s_opb_i_9> INFO:Xst:2261 - The FF/Latch <i_mul_24/s_fractb_i_3> in Unit <topmul> is equivalent to the following FF/Latch, which will be removed : <i_post_norm_mul/s_opb_i_3> INFO:Xst:2261 - The FF/Latch <i_mul_24/s_fractb_i_18> in Unit <topmul> is equivalent to the following FF/Latch, which will be removed : <i_post_norm_mul/s_opb_i_18> INFO:Xst:2261 - The FF/Latch <i_mul_24/s_fractb_i_2> in Unit <topmul> is equivalent to the following FF/Latch, which will be removed : <i_post_norm_mul/s_opb_i_2> INFO:Xst:2261 - The FF/Latch <i_mul_24/s_fractb_i_13> in Unit <topmul> is equivalent to the following FF/Latch, which will be removed : <i_post_norm_mul/s_opb_i_13> INFO:Xst:2261 - The FF/Latch <i_mul_24/s_fractb_i_12> in Unit <topmul> is equivalent to the following FF/Latch, which will be removed : <i_post_norm_mul/s_opb_i_12> INFO:Xst:2261 - The FF/Latch <i_mul_24/s_fractb_i_8> in Unit <topmul> is equivalent to the following FF/Latch, which will be removed : <i_post_norm_mul/s_opb_i_8> INFO:Xst:2261 - The FF/Latch <i_mul_24/s_fracta_i_22> in Unit <topmul> is equivalent to the following FF/Latch, which will be removed : <i_post_norm_mul/s_opa_i_22> INFO:Xst:2261 - The FF/Latch <i_mul_24/s_fractb_i_7> in Unit <topmul> is equivalent to the following FF/Latch, which will be removed : <i_post_norm_mul/s_opb_i_7> INFO:Xst:2261 - The FF/Latch <i_mul_24/s_fracta_i_21> in Unit <topmul> is equivalent to the following FF/Latch, which will be removed : <i_post_norm_mul/s_opa_i_21> INFO:Xst:2261 - The FF/Latch <i_mul_24/s_fracta_i_17> in Unit <topmul> is equivalent to the following FF/Latch, which will be removed : <i_post_norm_mul/s_opa_i_17> INFO:Xst:2261 - The FF/Latch <i_mul_24/s_fracta_i_20> in Unit <topmul> is equivalent to the following FF/Latch, which will be removed : <i_post_norm_mul/s_opa_i_20> INFO:Xst:2261 - The FF/Latch <i_mul_24/s_fracta_i_16> in Unit <topmul> is equivalent to the following FF/Latch, which will be removed : <i_post_norm_mul/s_opa_i_16> INFO:Xst:2261 - The FF/Latch <i_mul_24/s_fracta_i_12> in Unit <topmul> is equivalent to the following FF/Latch, which will be removed : <i_post_norm_mul/s_opa_i_12> INFO:Xst:2261 - The FF/Latch <i_mul_24/s_fracta_i_15> in Unit <topmul> is equivalent to the following FF/Latch, which will be removed : <i_post_norm_mul/s_opa_i_15> INFO:Xst:2261 - The FF/Latch <i_mul_24/s_fracta_i_11> in Unit <topmul> is equivalent to the following FF/Latch, which will be removed : <i_post_norm_mul/s_opa_i_11>

INFO:Xst:2261 - The FF/Latch <i_mul_24/s_fracta_i_7> in Unit <topmul> is equivalent to the following FF/Latch, which will be removed : <i_post_norm_mul/s_opa_i_7> INFO:Xst:2261 - The FF/Latch <i_mul_24/s_fracta_i_10> in Unit <topmul> is equivalent to the following FF/Latch, which will be removed : <i_post_norm_mul/s_opa_i_10> INFO:Xst:2261 - The FF/Latch <i_mul_24/s_fracta_i_6> in Unit <topmul> is equivalent to the following FF/Latch, which will be removed : <i_post_norm_mul/s_opa_i_6> INFO:Xst:2261 - The FF/Latch <i_mul_24/s_fracta_i_19> in Unit <topmul> is equivalent to the following FF/Latch, which will be removed : <i_post_norm_mul/s_opa_i_19> INFO:Xst:2261 - The FF/Latch <i_mul_24/s_fracta_i_5> in Unit <topmul> is equivalent to the following FF/Latch, which will be removed : <i_post_norm_mul/s_opa_i_5> INFO:Xst:2261 - The FF/Latch <i_mul_24/s_fracta_i_1> in Unit <topmul> is equivalent to the following FF/Latch, which will be removed : <i_post_norm_mul/s_opa_i_1> INFO:Xst:2261 - The FF/Latch <i_mul_24/s_fracta_i_18> in Unit <topmul> is equivalent to the following FF/Latch, which will be removed : <i_post_norm_mul/s_opa_i_18> INFO:Xst:2261 - The FF/Latch <i_mul_24/s_fracta_i_14> in Unit <topmul> is equivalent to the following FF/Latch, which will be removed : <i_post_norm_mul/s_opa_i_14> INFO:Xst:2261 - The FF/Latch <i_mul_24/s_fracta_i_4> in Unit <topmul> is equivalent to the following FF/Latch, which will be removed : <i_post_norm_mul/s_opa_i_4> INFO:Xst:2261 - The FF/Latch <i_mul_24/s_fracta_i_0> in Unit <topmul> is equivalent to the following FF/Latch, which will be removed : <i_post_norm_mul/s_opa_i_0> INFO:Xst:2261 - The FF/Latch <i_mul_24/s_fracta_i_13> in Unit <topmul> is equivalent to the following FF/Latch, which will be removed : <i_post_norm_mul/s_opa_i_13> INFO:Xst:2261 - The FF/Latch <i_mul_24/s_fracta_i_9> in Unit <topmul> is equivalent to the following FF/Latch, which will be removed : <i_post_norm_mul/s_opa_i_9> INFO:Xst:2261 - The FF/Latch <i_mul_24/s_fracta_i_8> in Unit <topmul> is equivalent to the following FF/Latch, which will be removed : <i_post_norm_mul/s_opa_i_8> Found area constraint ratio of 100 (+ 5) on block topmul, actual ratio is 214. Optimizing block <topmul> to meet ratio 100 (+ 5) of 960 slices : WARNING:Xst:2254 - Area constraint could not be met for block <topmul>, final ratio is 187. FlipFlop i_post_norm_mul/s_fract_48_i_1 has been replicated 2 time(s) FlipFlop i_post_norm_mul/s_fract_48_i_10 has been replicated 7 time(s) FlipFlop i_post_norm_mul/s_fract_48_i_11 has been replicated 8 time(s) FlipFlop i_post_norm_mul/s_fract_48_i_12 has been replicated 7 time(s)

FlipFlop i_post_norm_mul/s_fract_48_i_13 has been replicated 7 time(s) FlipFlop i_post_norm_mul/s_fract_48_i_14 has been replicated 4 time(s) FlipFlop i_post_norm_mul/s_fract_48_i_15 has been replicated 1 time(s) FlipFlop i_post_norm_mul/s_fract_48_i_16 has been replicated 2 time(s) FlipFlop i_post_norm_mul/s_fract_48_i_17 has been replicated 1 time(s) FlipFlop i_post_norm_mul/s_fract_48_i_18 has been replicated 1 time(s) FlipFlop i_post_norm_mul/s_fract_48_i_2 has been replicated 2 time(s) FlipFlop i_post_norm_mul/s_fract_48_i_3 has been replicated 2 time(s) FlipFlop i_post_norm_mul/s_fract_48_i_31 has been replicated 1 time(s) FlipFlop i_post_norm_mul/s_fract_48_i_32 has been replicated 2 time(s) FlipFlop i_post_norm_mul/s_fract_48_i_33 has been replicated 2 time(s) FlipFlop i_post_norm_mul/s_fract_48_i_34 has been replicated 3 time(s) FlipFlop i_post_norm_mul/s_fract_48_i_35 has been replicated 3 time(s) FlipFlop i_post_norm_mul/s_fract_48_i_36 has been replicated 4 time(s) FlipFlop i_post_norm_mul/s_fract_48_i_37 has been replicated 4 time(s) FlipFlop i_post_norm_mul/s_fract_48_i_38 has been replicated 4 time(s) FlipFlop i_post_norm_mul/s_fract_48_i_39 has been replicated 6 time(s) FlipFlop i_post_norm_mul/s_fract_48_i_4 has been replicated 4 time(s) FlipFlop i_post_norm_mul/s_fract_48_i_40 has been replicated 4 time(s) FlipFlop i_post_norm_mul/s_fract_48_i_41 has been replicated 5 time(s) FlipFlop i_post_norm_mul/s_fract_48_i_42 has been replicated 6 time(s) FlipFlop i_post_norm_mul/s_fract_48_i_43 has been replicated 2 time(s) FlipFlop i_post_norm_mul/s_fract_48_i_44 has been replicated 2 time(s) FlipFlop i_post_norm_mul/s_fract_48_i_45 has been replicated 2 time(s) FlipFlop i_post_norm_mul/s_fract_48_i_46 has been replicated 2 time(s) FlipFlop i_post_norm_mul/s_fract_48_i_5 has been replicated 2 time(s) FlipFlop i_post_norm_mul/s_fract_48_i_6 has been replicated 2 time(s)

FlipFlop i_post_norm_mul/s_fract_48_i_7 has been replicated 5 time(s) FlipFlop i_post_norm_mul/s_fract_48_i_8 has been replicated 2 time(s) FlipFlop i_post_norm_mul/s_fract_48_i_9 has been replicated 3 time(s)

Final Macro Processing ...

Processing Unit <topmul> : Found 2-bit shift register for signal <i_post_norm_mul/s_exp_10_i_1>. Found 2-bit shift register for signal <i_post_norm_mul/s_exp_10_i_2>. Found 2-bit shift register for signal <i_post_norm_mul/s_exp_10_i_3>. Found 2-bit shift register for signal <i_post_norm_mul/s_exp_10_i_4>. Found 2-bit shift register for signal <i_post_norm_mul/s_exp_10_i_5>. Found 2-bit shift register for signal <i_post_norm_mul/s_exp_10_i_6>. Found 2-bit shift register for signal <i_post_norm_mul/s_exp_10_i_7>. Found 2-bit shift register for signal <i_post_norm_mul/s_exp_10_i_8>. Unit <topmul> processed.

========================================================================= Final Register Report

Macro Statistics # Registers Flip-Flops # Shift Registers 2-bit shift register : 666 : 666 :8 :8

=========================================================================

========================================================================= * Partition Report *

=========================================================================

Partition Implementation Status -------------------------------

No Partitions were found in this design.

-------------------------------

========================================================================= * Final Report *

========================================================================= Final Results RTL Top Level Output File Name Top Level Output File Name Output Format Optimization Goal Keep Hierarchy : topmul.ngr : topmul

: NGC : Speed : NO

Design Statistics # IOs : 102

Cell Usage : # BELS : 6179

# # # # # # # # # # # # # # # # #

GND INV LUT1 LUT2 LUT2_D LUT2_L LUT3 LUT3_D LUT3_L LUT4 LUT4_D LUT4_L MULT_AND MUXCY MUXF5 VCC XORCY

:1 :3 : 52 : 218 : 22 : 23 : 812 : 106 : 52 : 2990 : 496 : 442 : 16 : 157 : 656 :1 : 132 : 674 : 300 : 288 : 13 :3 :3 : 66 :1 :8 :8

# FlipFlops/Latches # # # # # # # FD FDE FDR FDRE FDRS FDS FDSE

# Shift Registers # SRL16

# Clock Buffers # BUFGP

:1 :1 : 100 : 67 : 33 :4 :4

# IO Buffers # # IBUF OBUF

# MULTs # MULT18X18SIO

=========================================================================

Device utilization summary: ---------------------------

Selected Device : 3s100evq100-5

Number of Slices: Number of Slice Flip Flops: Number of 4 input LUTs: Number used as logic:

2739 out of 960 285% (*) 674 out of 1920 35% 5224 out of 1920 272% (*) 5216 8

Number used as Shift registers: Number of IOs: Number of bonded IOBs: Number of MULT18X18SIOs: Number of GCLKs: 102

101 out of 4 out of 1 out of 24

66 153% (*) 4 100% 4%

WARNING:Xst:1336 - (*) More than 100% of Device resources are used

========================================================================= TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE.

Clock Information: ----------------------------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load |

-----------------------------------+------------------------+-------+ clk_i1 | BUFGP | 682 |

-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information: ---------------------------------------No asynchronous control signals found in this design

Timing Summary: --------------Speed Grade: -5

Minimum period: 67.234ns (Maximum Frequency: 14.874MHz) Minimum input arrival time before clock: 10.408ns Maximum output required time after clock: 4.364ns Maximum combinational path delay: No path found

Timing Detail: -------------All values displayed in nanoseconds (ns)

========================================================================= Timing constraint: Default period analysis for Clock 'clk_i1' Clock period: 67.234ns (frequency: 14.874MHz) Total number of paths / destination ports: 3919977951538379 / 981 ------------------------------------------------------------------------Delay: Source: Destination: Source Clock: 67.234ns (Levels of Logic = 51) i_post_norm_mul/s_fract_48_i_0 (FF) i_post_norm_mul/s_r_zeros_5 (FF) clk_i1 rising

Destination Clock: clk_i1 rising

Data Path: i_post_norm_mul/s_fract_48_i_0 to i_post_norm_mul/s_r_zeros_5 Gate Cell:in->out Net

fanout Delay Delay Logical Name (Net Name)

---------------------------------------- -----------FD:C->Q 18 0.514 1.234 i_post_norm_mul/s_fract_48_i_0 (i_post_norm_mul/s_fract_48_i_0) LUT4:I2->O 8 0.612 0.951 i_post_norm_mul/_mux0049<1>1 (i_post_norm_mul/Madd__add0007_lut<1>) LUT4:I2->O 6 0.612 0.856 i_post_norm_mul/_mux0051<1>1 (i_post_norm_mul/Madd__add0005_lut<1>) LUT4_D:I3->O 3 0.612 0.774 i_post_norm_mul/_mux0053<1>1 (i_post_norm_mul/Madd__add0003_lut<1>) LUT4_D:I3->O 3 0.612 0.801 i_post_norm_mul/_mux0055<1>2 (i_post_norm_mul/N1006)

LUT4:I2->O 19 0.612 1.263 i_post_norm_mul/_mux0055<1>223 (i_post_norm_mul/_mux0055<1>_map9456) LUT4:I2->O 11 0.612 0.975 i_post_norm_mul/_mux0056<1>1 (i_post_norm_mul/Madd__add0012_lut<1>) LUT4:I3->O 14 0.612 1.039 i_post_norm_mul/Madd__add0011_cy<1>11_1 (i_post_norm_mul/Madd__add0011_cy<1>11) LUT4:I2->O 9 0.612 0.955 i_post_norm_mul/_mux0058<2>1 (i_post_norm_mul/Madd__add0010_lut<2>) MUXF5:S->O 7 0.641 0.909 i_post_norm_mul/_mux0063<2>11 (i_post_norm_mul/N425)

LUT4_D:I3->O 4 0.612 0.782 i_post_norm_mul/_mux0060<2>1 (i_post_norm_mul/Madd__add0014_lut<2>) LUT4:I3->O 1 0.612 0.000 i_post_norm_mul/_mux0062<2>225_F (N28093)

MUXF5:I0->O 6 0.278 0.853 i_post_norm_mul/_mux0062<2>225 (i_post_norm_mul/_mux0062<2>2_map8046) MUXF5:S->O (N33780) 1 0.641 0.684 i_post_norm_mul/Madd__add0016_xor<2>11_SW2

LUT4:I3->O 3 0.612 0.801 i_post_norm_mul/_mux0064<2>51 (i_post_norm_mul/_mux0064<2>_map8287) LUT4:I2->O 5 0.612 0.786 i_post_norm_mul/_mux0064<2>92 (i_post_norm_mul/Madd__add0018_lut<2>) LUT4:I3->O 3 0.612 0.000 i_post_norm_mul/_mux0065<2>105_F (N33997)

MUXF5:I0->O 43 0.278 1.632 i_post_norm_mul/_mux0065<2>105 (i_post_norm_mul/Madd__add0023_lut<2>) LUT4:I3->O 11 0.612 0.972 i_post_norm_mul/_mux0068<2>1 (i_post_norm_mul/Madd__add0020_lut<2>) MUXF5:S->O LUT4:I2->O LUT4:I3->O 5 0.641 0.813 i_post_norm_mul/_mux0073<2>11 (i_post_norm_mul/N428) 6 0.612 0.856 i_post_norm_mul/_mux0071<2>21 (i_post_norm_mul/N336) 1 0.612 0.000 i_post_norm_mul/_mux0072<2>269_F (N34105)

MUXF5:I0->O 6 0.278 0.883 i_post_norm_mul/_mux0072<2>269 (i_post_norm_mul/N636) LUT4_D:I2->O 3 0.612 0.801 i_post_norm_mul/Madd__add0026_xor<2>11 (i_post_norm_mul/_add0026<2>)

LUT4:I2->O 3 0.612 0.801 i_post_norm_mul/_mux0073<2>131 (i_post_norm_mul/Madd__add0027_lut<2>) LUT4:I2->O 2 0.612 0.748 i_post_norm_mul/_mux0074<2>92 (i_post_norm_mul/Madd__add0028_lut<2>) LUT4:I3->O 4 0.612 0.000 i_post_norm_mul/_mux0075<2>105_F (N27891)

MUXF5:I0->O 35 0.278 1.620 i_post_norm_mul/_mux0075<2>105 (i_post_norm_mul/Madd__add0033_lut<2>) LUT3:I2->O 7 0.612 0.909 i_post_norm_mul/Madd__add0033_cy<2>11 (i_post_norm_mul/Madd__add0033_cy<2>) LUT4:I3->O 3 0.612 0.774 i_post_norm_mul/_mux0076<3>1_SW1 (N30675)

LUT4:I3->O 3 0.612 0.771 i_post_norm_mul/_mux0078<3>1 (i_post_norm_mul/Madd__add0030_lut<3>) MUXF5:S->O 5 0.641 0.813 i_post_norm_mul/_mux0083<3>1123 (i_post_norm_mul/_mux0083<3>11_map6277) LUT4:I2->O 2 0.612 0.748 i_post_norm_mul/_mux0081<3>21_SW0 (N29743)

LUT4:I3->O 6 0.612 0.856 i_post_norm_mul/_mux0081<3>1 (i_post_norm_mul/Madd__add0035_lut<3>) LUT4:I3->O 21 0.612 1.288 i_post_norm_mul/Madd__add0035_cy<3>11 (i_post_norm_mul/Madd__add0035_cy<3>) MUXF5:S->O 1 0.641 0.750 i_post_norm_mul/_mux0082<4>285_SW4 (N31270)

LUT4_D:I1->O 5 0.612 0.786 i_post_norm_mul/_mux0082<4>129 (i_post_norm_mul/Madd__add0036_lut<4>) LUT4:I3->O 2 0.612 0.775 i_post_norm_mul/_mux0084<5>30_SW0 (N29845)

LUT4:I2->O 3 0.612 0.774 i_post_norm_mul/_mux0083<5>113 (i_post_norm_mul/Madd__add003710) LUT4:I3->O 1 0.612 0.000 i_post_norm_mul/_mux0084<5>87_F (N34101)

MUXF5:I0->O 2 0.278 0.748 i_post_norm_mul/_mux0084<5>87 (i_post_norm_mul/Madd__add003810) LUT4:I3->O 2 0.612 0.000 i_post_norm_mul/_mux0085<5>120_F (N33967)

MUXF5:I0->O 5 0.278 0.786 i_post_norm_mul/_mux0085<5>120 (i_post_norm_mul/Madd__add004310) LUT4_D:I3->O 3 0.612 0.774 i_post_norm_mul/_mux0087<5>1 (i_post_norm_mul/Madd__add004110)

LUT4:I3->O 1 0.612 0.684 i_post_norm_mul/_mux0090<5>114 (i_post_norm_mul/_mux0090<5>_map8445) LUT4:I3->O 1 0.612 0.000 i_post_norm_mul/_mux0090<5>207_G (N34304)

MUXF5:I1->O 4 0.278 0.782 i_post_norm_mul/_mux0090<5>207 (i_post_norm_mul/Madd__add004410) LUT4_D:I3->LO 1 0.612 0.103 i_post_norm_mul/_mux0092<5>26 (N35253)

LUT4:I3->O 1 0.612 0.681 i_post_norm_mul/_mux0110<5>148 (i_post_norm_mul/_mux0110<5>_map9892) MUXF5:S->O 1 0.641 0.711 i_post_norm_mul/_mux0110<5>183_SW0 (N30340)

LUT4_L:I2->LO 1 0.612 0.103 i_post_norm_mul/_mux0110<5>221 (i_post_norm_mul/_mux0110<5>_map9906) LUT4:I3->O 1 0.612 0.000 i_post_norm_mul/_mux0110<5>493 (i_post_norm_mul/_mux0110<5>) FD:D 0.268 i_post_norm_mul/s_r_zeros_5

---------------------------------------Total 67.234ns (29.830ns logic, 37.404ns route) (44.4% logic, 55.6% route)

========================================================================= Timing constraint: Default OFFSET IN BEFORE for Clock 'clk_i1' Total number of paths / destination ports: 1519 / 80 ------------------------------------------------------------------------Offset: Source: Destination: 10.408ns (Levels of Logic = 9) opa_i1<25> (PAD) i_post_norm_mul/Mshreg_s_exp_10_i_7 (FF)

Destination Clock: clk_i1 rising

Data Path: opa_i1<25> to i_post_norm_mul/Mshreg_s_exp_10_i_7 Gate Net

Cell:in->out

fanout Delay Delay Logical Name (Net Name)

---------------------------------------- -----------IBUF:I->O 3 1.106 0.923 opa_i1_25_IBUF (opa_i1_25_IBUF)

LUT4:I0->O 2 0.612 0.897 i_pre_norm_mul/_xor00014 (i_pre_norm_mul/_xor0001_map23) LUT2:I0->O 1 0.612 0.681 i_pre_norm_mul/s_opa_dn1 (i_pre_norm_mul/s_opa_dn)

MUXCY:CI->O 1 0.051 0.000 i_pre_norm_mul/Madd__addsub0000_Madd_cy<0> (i_pre_norm_mul/Madd__addsub0000_Madd_cy<0>) MUXCY:CI->O 1 0.051 0.000 i_pre_norm_mul/Madd__addsub0000_Madd_cy<1> (i_pre_norm_mul/Madd__addsub0000_Madd_cy<1>) XORCY:CI->O 3 0.699 0.923 i_pre_norm_mul/Madd__addsub0000_Madd_xor<2> (i_pre_norm_mul/Msub_s_exp_10_o_lut<2>) LUT4:I0->O 4 0.612 0.809 i_pre_norm_mul/Msub_s_exp_10_o_cy<3>11 (i_pre_norm_mul/Msub_s_exp_10_o_cy<3>) LUT4:I2->O 3 0.612 0.840 i_pre_norm_mul/Msub_s_exp_10_o_cy<6>11 (i_pre_norm_mul/Msub_s_exp_10_o_cy<6>) LUT3:I1->O 1 0.612 0.000 i_pre_norm_mul/Msub_s_exp_10_o_xor<8>11 (i_pre_norm_mul/s_exp_10_o<8>) SRL16:D 0.366 i_post_norm_mul/Mshreg_s_exp_10_i_8

---------------------------------------Total 10.408ns (5.334ns logic, 5.074ns route) (51.3% logic, 48.7% route)

========================================================================= Timing constraint: Default OFFSET OUT AFTER for Clock 'clk_i1' Total number of paths / destination ports: 33 / 33 ------------------------------------------------------------------------Offset: Source: Destination: 4.364ns (Levels of Logic = 1) i_post_norm_mul/ine_o (FF) ine_o1 (PAD)

Source Clock:

clk_i1 rising

Data Path: i_post_norm_mul/ine_o to ine_o1 Gate Cell:in->out Net

fanout Delay Delay Logical Name (Net Name)

---------------------------------------- -----------FDRS:C->Q OBUF:I->O 1 0.514 0.681 i_post_norm_mul/ine_o (i_post_norm_mul/ine_o) 3.169 ine_o1_OBUF (ine_o1)

---------------------------------------Total 4.364ns (3.683ns logic, 0.681ns route) (84.4% logic, 15.6% route)

========================================================================= CPU : 220.81 / 221.05 s | Elapsed : 220.00 / 221.00 s

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Total memory usage is 315088 kilobytes

Number of errors : 0 ( 0 filtered) Number of warnings : 335 ( 0 filtered) Number of infos : 62 ( 0 filtered)