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Unit III 8086 SYSTEMDESIGN

3.I 8086 SIGNALS
(lvlax nnde)

AD, ADu AD,: AD,, 4D,., AD,

AD,, A,"/S A'/S. A'/$ A''iE

ffirs,
MN/M

AD
AD6

AD AD.

11

E086 CPI.J

-10

TM rq-rdF" R-qeI
LOCKI s,

(Min rnde) (HOl-D) (ilLDA)

tfr-nr
(M/ i6) (Dr/T) tdF.St (Ar-E)

s, s,
aq,
NMI INT CT.K G

Qs, TEff
READY RESEl'

(ifriT)

Fig.3.l Pin Diagramaf 8086

A 40 pin DIP 8086microprocessor shownin Fig.3.l. 8086microprocessor operate can is pins24 to 3l havealternate in two modes: functions MinimummodeandMaximummode.The for every mode.
tO86 SystemDesign

3.3

Minimum mode MN/ IWK pin is connectedto +5V. Used in small systemsincluding only one CPU. Maximum mode MN/lvtK pin is connectedto ground. Used in large systemsand systemswith more than one processor. Minimum Mode Signals:

Address/data/statu s ADI5-ADO Address/data bus A19/S6-Al6/53 Address/status bus

Handshaking for data read/write

Bidirectional,-state 3 output,3-state

RD READY

Read from memory/IO Ready signal Select memory or IO Write to memory/IO Address latch enable Data transmit/receive Data bus enable Bus high enable

output,3-state input output,3-state output,3-state output output output output

M/a WR
ALE DT/R

DEN /s7 BtrE

INTR NMI RESET

Interrupt signals Interruptrequest Non-maskable interrupt Reset Interrupt acknowledge

B u s a c c e s sc o n t r o l

input input input output

TNTA
HOLD HLDA

Hold request Hold acknowledge

input output Others

TE-ST
MN/IVCK CLK

Testpin tested WAIT instruction by Minimum/maximum mode, 5V Clockpin for basic timingsignal +5 Powersupply, V Ground connection,0V

rnput input input

v..
GND

3.4

Mi cr opr ocesso r s an d Micr.o contr ollers

Maximum Mode Signals: Address/data/status

ADI5-ADO Ar9/S6-416/53

Address/data bus Address/status bus Handshaking for data read/write

Bidirectional,3-state output,3-state

RD
READY

Read from memory/IO Ready signal Bus high enable Status/handshake indicatingthe bits function ofthe current bus cvcle

output,3-state input output output

Bm/S7 v,sl,s0

Interrupt signals INTR NMI RESET Interruptrequest Non-maskable interrupt Reset

Bus access control

lnput input input

nolcr nolcro

Request/grant pins for bus access Used to lock the bus, activatedby LOCK prefix on any instruction

bidirectional output

meK
QS1,QSO

Others Queuestatus Testpin tested WAIT instruction by Minimum/maximum mode, 0V Clockpin for basictimingsignal Powersupply, ! +J Ground connection, 0V output input input input

IEST
MN/MK CLK

v..
GND

3.1.1ADDRESS/ DATA BUS (ADl5 _ADls) Themultiplexed Address/ Databusactsasaddress duringthe first partof machine bus cycle(Tl) anddatabus for the remaining part of the machine cycle. 3.1.2ADDRESS/STATUS (At9156,A18/SS,At7/54, 416153) During Tl theseare the four most significant address lines for memoryoperations. During I/O operations theselines are LOW During memoryand I/O op".utionr, status information available theselinesduringT2,T3, T*o,r,T4. The status the interrupt is on of
8O86System Design

3.5

enable FLAG bit (S5)is updated thebeginning eachCLK cycle.Function status at of of bits 53 and54 as shown below:

s4 s3
0 0 I I 0. I 0 I

Function
ES, Extra segment SS, Stack Segment CS or no segment DS, Data segment

3.1.3 Bus High Enable/Status (Bm/S7) During Tl the bus high enablesignal(Em ) shouldbe usedto enabledataonto the mostsignificant half of thedatabus,pinsD I 5+D8. Effi is LOW duringTl for read,write, andinterruptacknowledge cycleswhena byte is to be transferred the high portion of the bus. The 57 statusinformation is available on during T2,T3,andT4. BHE 0 0 I 1 AO 0 I 0 I
Characteristics

Wholeword Upperbyte from/to odd address Lower byte from/to evenaddress None

3.1.4 (m ) READ
This signalis usedto readdatafrom memoryor I/O devicewhich resideon the 8086 localbus. 3 . 1 . 5R E A D Y If this signalis low the 8086enters into WAIT state. The READY signalfrom memory/ IO is synchronized the 8284A Clock Generator form READY. This signal is active by to HIGH. 3.1.6 TNTERRUPT REQUEST (rNTR) It is a level triggeredmaskableinterruptrequest. A subroutineis vectoredvia an intenuptvectorlookuptablelocatedin system memory. canbe internallymasked software It by resetting interruptenable INTR is internallysynchronized. signalis activeHIGH. the bit. This 3 . 1 . 7T E S T This input is examined the "'Wait"instruction. the TEST input is LOW execution by If continues, otherwise processor the waitsin an "Idle" state. This inputis synchronized internally duringeachclock cycleon the leading edgeof CLK. 3.6
Miooprocessorsand Misoconffollers

3.1.8 NON-MASKABLE INTERRUPT (NMI) It is an edge triggered input which causesa type 2 interrupt. NMI is not maskable internally by software.A transition from LOW to HIGH initiates the interrupt at the end of thecurrentinstruction. 3 . 1 . 9R E S E T terminate to the This signalis usedto resetthe 8086.It causes processor immediately present The signalmustbe activeHIGH for at leastfour clock cycles.It restarts its activity. when RESETreturnsLOW. execution

3.1.r0 clocK (cLK)

and This signalprovidesthe basictiming for the processor bus controller.The clock on frequency may be 5 MHz or 8 MHz or l0 MHz depending the versionof 8086. 3.1.11 V.. It is a +5V power supplypin. 3.r.r2 GROUND (GND) MTNTMUM/MAXIMUM (MN/tDt) to Two pins (l and 20) areconnected groundie, 0 V power supply. 3.1.13 in. whatmodetheprocessor to operate The 8086canbe configured is This pin indicates modeusingthispin. in eitherminimummodeor maximum 3.1.14 Minimum Mode Signels: MEMoRY / Io (M/rd) M from an VO access. = HIGH, VO = LOW. It is usedto distinguisha memoryaccess WRITE(wR) It indicates that theprocessor performinga write memoryor write VO cyclc,depending is on the stateof the M/i6 signal. TNTERRUPT ACKNOWLEDGE (iFm) This signalindicates recognition an intemrptrequest. is usedas a readstrobefor of It interruptacknowledge cycles. ADDRESS LATCH ENABLE (ALE) This signalis usedto demultiplex AD0-ADI5 into A0-Al5 and D0-D15.It is a the HIGH pulseactiveduring Tl of any bus cycle. DATA TRANSMTT/RECETVE(DT/n) (8286/8287). is usedto control the This signaldesiresto usea databus transceiver It directionof dataflow throughthe transceiver. high signalon this pin indicates A that 8086is transmitting dataand low indicates the that 8086is receivingthe data.
EOE6 SystemDesign

3.7

DATA ENABLE(DEN) or to is (8286/8287) 8086 ready send roceive thatthe the informs transceivers Thissignal
data. HOLD the is (DMA or processor) requesting host master that another This signalindicates the 8086to handover systembus. HOLD ACKNOWLEDGE (HLDA) HLDA signalHIGH asan acknowledgement. On receivingHOLD signal8086outputs 3.1.15 MaximumMode Signals: of in differsfromminimummode thatsome thecontrolsignals operation Maximummode a circuitry,however, chip -the8288bus additional generated. requires This mustbe externally purpose available. is for controller-designed this ( STATUSS2, St, S0) lines cycleused.Thesestatus indicate typeof machine the signals These threestatus shownbelow: as are encoded

s2
0 0 0 0 I I I I

s1 s0
0 0 I I 0 0 I I 0 I 0 1 0 I 0 I

Machine cycle

Interruptacknowledge Memory read Memory write Halt Opcodefetch IO read IO write Passive

(Ro/Gm, RQ/Gr1) REQUESTiGRANT

to the processor to Thesepins are used by other local bus masters force RQ I m currentbuscycle.Eachpin is bidirectional release local bus at the end of theprocessor's the with RQ/Gft havinghigherpriority than RQI m

MTR
are This signalindicates that othersystem masters not to gaincontrolof thesystem bus by bus while LOCK is active LOW. The LOCK signal is activated the "LOCK" prefix This signalis active of instruction remains and activeuntil thecompletion thenextinstruction. LOW. 3.8
rro Micr oprocessors and Microcon llers

QUnUE STATUS (QSl, QS0) is The queuestatusis valid during the CLK cycle after which the queueoperation performed.eSl and QSo provide statusto allow externaltracking of the internal 8086 queue. instruction
QSl

QS0 0 I 0 I

Characteristics No Operation First Byte of Op Codefrom Queue Empty the Queue byte from Queue Subsequent

0 0 I 1

3.2. MIN/MAX MODE OF' OPERATION They are: o Intel 8086hastwo modesof operation. i. ii. o Minimum mode Maximummode

. o o

the system 8086is is When only 8086microprocessor to be usedin a microcomputer the issues In usedin the minimum mode of operation. this modethe microprocessor control signalsrequiredby memoryor I/O devices. in it system operates themaximum mode.In this mode,thecontrol In a multiprocessor by are signals issued Intel 8288buscontroller. modeof 8086. the Thepin MN/MX (33) decides operating When MN/ MX : 0, maximummodeof operation. : l, minimummodeof operation. Pins24 to 3l havedifferentfunctionsfor minimummodeandmaximummode. to MN/MX is connected V"" (+5 volts). For minimummodeof operation insidethe All control signalsfor controllingmemoryand VO devicesare generated 8086microprocessor. Pins24to3l havethefollowingfunctions: Pin24: mf Pin 25 = ALE pin26: DEN Pin 27 : DT/ F (InterruptAcknowledge) (AddressLatch Enable) (DataEnable) (DataTransmit/ Receive) 3.9

3.2.1Minimum Mode o o o

8o86SystemDesign

Pin 28 : M/IO (Memoryor VO) pin 29 = W[ (Write) Pin 30 = HLDA (HOLD Acknowledge) Pin 3l = HOLD (Hold) r o In this mode , peripheraldevicescan be usedwith the microprocessor without any special consideration. A single8086is in this mode.The remaining in components this modeare, Latches(8282\-3 numbers (8286)- 2 numbers Transceivers (8284) Clock generator Memory or VO devices. o The 8086 has multiplexedaddress/data signalsand address statussignals.Latches / are usedfor demultiplexing and thesclatches enabled using the ALE signal.3 are by (Intel 8282/8283) usedas address numbers latches of are latches. The data bus should be provided with data transceivers drive the data on the bus. to Transceivers controlledby two signals:m are , DT/[. The signal bF is usedas an outputenable signal.

r o e o o

The signalDT/ R is usedasdirectioncontrol.It indicates that valid datais available on the databus which indicates directionof dataie, from or to the processor. the Two numbers (Intcl 8286/8287)are usedas datatransceivers. octal bus transceivers generates clock from the Crystal Oscillatorand then shapes { clock generator the it and divides to make it more preciseso that it can be used as an accuratetiming reference the system. for (Intel 8284)doesthe following functions: Thc clock generator i. ii. Clock generation RESETsynchronization

iii. READYsynchronization iv. Peripheral clock generation A quartzcrystalof frequencyl5 MHz is connected X, and X, of 8284. to The statusof M/IO, ffi in Table 3.1. and W[ signalsdecides type of datatransferas shown the

3.10

Mio.'oprw ssorcand Mic.rocun tnollers

Teble 3.1 Rerd / Write oPeretion M/IO 0 0 I I

RD 0
I

WR
I 0 I 0

Operetion UO Read I/O Write MemoryRead Memory Write

0
I

like DMA controller. otherbusmasters HOLD andHLDA sisnalsareusedto interface . on by (InterruptAcknowledge)signalis issued the microprocessor recelvlng ffif anyinterruptsignal.Fig. 3.2 showstheminimummode8086system.
Crystal Oscillator
CLK MN/MX RESET

RAM EPFOM FromInterrupt Controllet ToInterrupt Controller FromDMA Controller ToDMA Controller
INTR INTA

l/O Devices Interrupt Controller

HOLD g0g6
HLDA

INTEL CPU

8286 Transceiver r 12)

dE
in syslem ninimum mode based computer Fig. 3.2 Intel 60E6

3,2.1.1

Minimum lllode Bus Timings

The timing diagramfor Readcycle is shownin Fig.3.3 and Write cycle is shownin Fig.3.4

EoE6 SystemDesign

3.11

CLK A,JS"-A,jS. and EFIE/S,

AD,5-ADo

ALE

M/io ilo
DT/F' DN

Read LOW= l/O Read, HIGH= Memory

Fig. 3.3. Mitrimunt Mode - Read Cycle

cycle oneBus f
CLK Address. BHEOUT A,JS.-A,JS3 and BHE/S, AD,u-ADo

DT/R------

Fig. 3.4: Minimum Mode Wnte Cqcle

3.12

Micr oproc ssorsand Microcuntrollers e

Read Operation : o latch enable(ALE) signal of The Read cycle beginsin T, with the assertion the address and also M/ IO signal. During the negativegoing edge of this signal, the valid addressis latchedon this bus. The BI{E and Ao Signals addresslow, high or both bytes. From T, to Tn the M/IO signal indicates memory or I/O operation. At T2, the addressis removed from the bus and is sent to the output. The bus is then tristated. device to enableits the The RD signal is activatedin Tr. This signal causes addressed data bus drivers. After RD goer lowJhe valid data is available on the data bus. After the data is accepted by the processor,RD is raised high at the beginning of To. At T, DEN is lowered to enable transceiver.At T4 OgN It raised to disable the transceiver. Write Operation : o o o o o of The Write cycle begins in T, with the assertion the ALE signal. The M/IO signal is assertedto indicate a memory or I/O operation. At Tl after sending the addressin T,, the processorsendsthe data to be written to the location. addressed The data on the bus remainsuntil middle of T, state. The WR signal becomesactive at the beginning of Tr. The BHE and Ao signals are used to select the proper type of memory or VO to be read or written. At T" DEN is lowered to enabletransceiver.At T4 it is raised to disable the transceiver. 3.2.2Maximum Mode o o For maximum mode of operationMN/ MX pin is grounded.Fig. 3.5 showsthe maximum mode 8086 system Pins 24 to 31 have the following functions:

o o o

Pins24 & 25 Pins 6,27 28 2 & Pin29 Pin 30 & 3l o

(Instruction Status) Queue QS1, QSO S 0 , S l , 5 2 ( S t a t us i g n a l s ) LOCK

/ RQ / GT, , RQ / Gq (Request Grant)

ask / Request Grant lines areusedfor local buspriority control. Otherprocessors the for the CPU throughtheselines to release local bus.The BHE - Ao characteristics these linesareshownrn Table3.2

Design 6086S),stem

3.13

Table 3.2 BHE -Ao cheracteristics

nqlGr nQlcr, nQlcr, nQlm, nqlcr,

BHE 0 0 I I

AO

Operation Word transfer Upperbyte transferfrom/to odd address Lower byte transfer from/to evenaddress None

0 I 0 I

8288 BUS Controller

RAM EPROM l/O Devices Inlerrupt Controller

;rviffi

i6'6[
RO / GTl

DEN DTiR ALE

-no I e-il
INTR

INTEL 8086 ALE CPU

BHE ADO-AD15 416-A1 9

DMA Controller

Fig. 3.5 Intel 8086 based computer syslem in maximum node a

an In maximummode8086basedsystem, externalBus Controller(Intel 8288)hasto generate bus controlsignals. be employed to the The importantsignalsare : MRDC - Memory ReadCommand

3.14

Miooproe ssor and Mbocontrollerc s

MWTC - Memory Write Command IORC - I/O Read Command IOWC - I/O Write Command AI\{WC-- Advanced Memory Write Command AIOWC - Advanced I/O Write Command The advancedsignals ( AMWC , AIOWC ) are activatedone clock pulse earlier.This
glve slow interfacesan extra clock cycle to preparethe input data.
a

Three numbers of 8 bit latches(Intel 8282) are employed to demultiplex the address by lines. The latchesare enabledby using the ALE signal generated the bus controller. The (Intel 8286) are used as data transceivers. Two numbersof octal bus transceivers by signals DEN and DT/R are generated the bus controller are used as enable and directioncontrol respectively. clock. reset and ready signalsfor The clock generator(Intel 8284) is usedto generate 8086. A quartzcrystal of frequency l5 MHz is connectedto 8284. Maximum Mode Bus Timings

3.2.2.1

The timing diagram for Read cycle is shown in Fig. 3.6 and Write cycle is shown rn

Fig.3.7.
One BusCycle

I
-q--s.
BHE, A,o-A,u

CLK

Address/Status------------.... and BHEIS, Address/data AD,"-ADo *ALE *MRDC or IORC *DT/R

Data lN D,u-Do

Bus ControllerOutputs
Fig.3.6 Ma.rinutmMode - ReaeiCycle

8O86System Design 15

3.15

One BusCycle

Address/Status-----'---------. and BHE/S .--..----...-.. Addressldata AD,u-ADo _: *ALE *AMWC

orA-i6We
*N/I\,VTC

ori6wc

*8288BusController aubuts
Fig. 3.7 Maxinrum Mode - Ihite Cycle

The status signals L , q and { are set at the begining of bus cycle. When = : = will output a pulse on its ALE and ), E q So 1, ( inactive-passive the bus controller to its DT/R pin at T,. apply a requiredsignal At Tl the bus controller will set DEN: 1, therefore transceiveris enabled.For an input, bus controller will activate MRDC or IORC . These signals are activateduntil To.For an output, it will activate AMWC or 4164y6 . These signals are activatedfrom T2 to T4 and 14qry3 or IOWC ts activated from T, to To. The status signals q , q and q inactive during T, and To. MEMORY ADDRESSING are remain active during T, and T, and become

o 3.3

of In 8086 the memory addressspacecan be viewed as a sequence one million bytes in bytes may contain rvhichany byte may contain an 8-bit dataelementand any two consecutive a l6-bit data element and there will not be constrarnton byte or word addressboundaries. The address spaceis physically connectedto a l6 bit data bus by dividing the addressspace into two 8 bit banks of upto 512 k bytes each,namely Bank 0 and Bank I as shown in figure 3" 8 .

3.16

Microprocessors and Microcontrollers

Bank 0 is connectedto the lower half of the 16 bit databus (Do-Dr) and contarnseven Bank I is connectedto the upper bytes ie, when A0 bit is low the bank is selected. address half of the data bus (Dr-D,r) and containsodd addressbytes, i.e. when A0 bit is high and A (Bus High Enable) is low, the odd bank is selected. specificbyte within eachbank is ffi lines A1-A19. selected address dy DataBus(Do-D,J

Bus Address (A,-A,n) in Addressing 8086 Fig.3.8Memory There are four possible ways to accessthe data from the memory. Together gHE and on A0 tell the interfacehow the data appears bus. The combinationsare shown in Table 3.3'

Table 3.3
rIo

Operation
8 bit data (byte) from Lower (EVEN) addressbank

BHE AO
I I

DataLines Used
Dr-Do
D'.-Do

0
1 I

2 . 8 bit data(byte) from Higher

(ODD) address bank
J.
a

0 0 0
I

l6 bit data(word)starting from EVEN address

l6 bit data (word) starting from ODD address

0
I 0

D , ,- D o D,r-Do in first byte from odd bank is transt'erred bYte operation D7-D0 in second from evenbank is transferred

4.

3.3.1Interfacing Methods l. 2. Memorymapped I/O I/O mappedI/O

8086System Design

3.17

Memory mapped I/O L Memory mapped I/O is treatedas memory location

I/O mapped UA I/O mapped I/O is not treated as memory loc'ation

2. -Microprocessor access devices It requiresspecial instruction to access can I/O by memory instruction like MOV AX, I/O deviceslike IN, OUT" No special instructions are tBX]. needed. 3 . 8 0 8 6 c a n a c c e s sI M B y t e m e m o r y locations or I/O Ports. 4. It requires20 addresslines 5. NTIEMR MEMW signalscan be used , to accessI/O devrces 6. It is suitable for a small system 3.3.2 Advantages of Memory mapped IiO i. 2. 3. 4. 5. Many CPU registerscan exchangedata with IIO devices. The port addresses 16 bit wide, therebyit provtdesriore input anCoutput ports. are The samepowerful memory type instructionsare used to accessI/O device. Speed high. is Reduction the CPU controllines. in 8086 can access K byte I/O ports. 64 It requires I 6 addresslines IOR, IOW signalsare used. It is suitable for a large system

3.3.3 Disadvantagesof Lemory mapped I/O L 2. 3. The numberof I/O ports connected limited by numberof availablememory locations. is The length of program is increased Becauseof wider port address, the rnterfacehardwareis also rncreased.

3.3.4 Advantages of I/O mapped I/O L 2. Programis simple. The I/O instructionstsolatememory and I/O, so that memory addressrs not atfectedby

UO. 3. 4. TheI/O typeinstructrons usually tharr are less memory typernstructions in memcry used mapped lr'O. Thecomplexrty thedevtce of address decoder depends only on tile lengthof thedevice address field in thei/O typeinsrructrons.
Microproce ssorsand Microcontrollers

3.18

3.3.5 Disadvantagesof I/O mapped l/O 1. 2. It is lesspowerful and less flexible than memory mappedI/O' Two additional control lines are neededfor issuing ffi and 161y signals.

3.3.6 Me'mory and I/O lnterfacing Fig. 3.9 showsa schematicdiagramto interfacememory (RAM, ROM, EPROM'...) or Severalmemory chips or IiO devicescan connectedto I/O devicesto 8086 microprocessor. decodingcircuit is usedto selectthe requiredI/O deviceor a An a microprocessor. address memory chip.

a o o o-

Fig.3.9 Schennlic diagram of Mentory and I/O interfacing

3.3.7Memory Interfacing Step I : Decodelogic for generationof I/O and memory control stgnalsas shown rn Fig.3.10

Fig.3. I 0 GeneratrottoJ Control Signals

8086 System Design

3.19

Step 2 : from the signals311g and Ao' encoding 8086memoryaccess

BID
0. I 0 0
1 I

AU ^ 0 0
1 I

Action
(Dr5-Do) (D?-Do) (Dr5-D8) (Drs-D8) (D.,-Do)

Access bit word 16 Access byte (EVEN address) byte (ODD address) Access Accessword (ODD address) Accessword (EVEN address)

I 0

Step 3: CPU statefollowing reset as given below:

CPU Flags IP CS DS SS ES Queue

Contents Clear 0000 FFFF 0000 0000 0000 Empty

address Therefore physical the FFFFH andIP contains 0000H. After reset contains CS is FFFF0H. Hereinstruction from FFFFO H. execution starts Example : Interface x 2K EPROMwith 8086. 4 Total 8K bytesof memoryrequires address linesAo to A,, [2'3: 8K] l3 8 K bytesmean0IFFF H bytes Therefore EPROMaddress startsfrom, FFFFF- 0IFFF = FE000H Address rangeof EPROMis from FE000H to FFFFFH. Step 4 : Decode unused address linesto mapthe memoryinterface a particular to memory the in the mlcroprocessor address space. Step 5 : Typeofaddress decoding : i. Full address decodins
Microprocessor and Microcon s rrollers

ii. iii

Partial addressdecoding Block addressdecodine

Full decoding : All the unusedlines are used. Purtial decoding : All the unusedlines are not used. Block decoding : Sameas full decodingexceptthat blocks of memory is enabledusing the unusedlines. 3.4 SYSTEM DESIGN USING 8086

The systemdesign starts with specifications.The specificationof the system includes the following: 1. 2. 3. 4. 5. 1. I/O devices Memory requirement Systemclock frequency Peripheraldevicesrequired Application

IiO devices:

The popular input device used in single board microcomputer systemis 8279 - keyboard and displaycontroller. The popular output devrcesare, LED display LCD Printer Floppy disk / CD CRT terminal Intel8279 is used for LED display. The LCD and printer are rnterfacedusing ports. Intel8272 or 82072 floppy disk controller and lnLel8275 CRT controller are popularly usedin 8086 system. 2. Memory Requirement :

The memory of the systemis splitted betweenEPROM and RAM. The memory capacity basedon the applicationsand work to be performed"The of EPROM and RAM are estimated popularEPROM usedin 8086basedsystem are2708(1K x 8), 2716 (2Kx8),2732 (4K x 8),
8086 System Design

3.2'|,

2764 (8K x 8) and 27256 (32Kx 8). The popular static RAM used in 8086 basedsystemare 6 2 0 8( l K x B ) , 6 2 1 6 ( 2 K x 8 ) , 6 2 3 2( 4 K x 8 ) , 6 2 6 4( B K x 8 ) a n d 6 z z s 6 ( 3 2 K x 8 ) . 3. System clock frequency :

The 8086 doesnot have an internal clock circuit. Hence clock has to be suppliedfrom an external device. The Intel 8284 clock generatoris employed to generatethe clock. An external quartz crystal has to be connectedto 8284 to generatethe clock signal. The frequency of quartzcrystal should be thrice the internal clock freouencvof g0g6. 4. Peripheral Devices :

The peripheraldevicesrequired for a systemdependson its applications.Someof the peripheraldevicesthat can be interfacedto g0g6 basedsystemare, * * * * * * 5. Intel 8253 - Programmable Interval Timer lntel 8251 - USART Intel 8255 - ProgrammableperipheralInterface Intel8279 - Keyboard / Display controller Intel 8257 - DMA controller ADC, DAC etc.

Application :

The specificationsof the microprocessoritself dependson the applications for the proposedsystemand the nature of work. The I/O device, memory, peripheral device are all dependson the nature of work to be performedby the system. 3.4.1 Nlemory Interfacing in 8086 based system Design Example l: Design an 8086 basedsystemr.viththe followine features: i. ii. iii. Solation : l' Wheneverthe 8086 is reset, its value is set to FFFF H and IP value is set to 0000H. This corresponds physical address to FFFFOH. Now 64 K byte EPROM rs to be interfacedwith g0g6. 64 K Bytes meansFFFF H bytes. Hence the EPROM memory should start from. FFFFF - FFFF = F0000 H 3.22
Micr oproce ssor s and Micr ocontr ollers

8086in minimummode 64 K Byte EPROM 64 K Byte RAM

and32 K byteswill be at ODD Of the 64 K bytes,32 K byteswill be at EVEN address (27256)are needed, address. eachof 32 K bytescapacityHencetwo EPROM chips bytes. one for storingbytes at EVEN address other for storingODD address and EPROMaddress range: F0000Hto FFFFFH EVEN address startsat F0000Hand ODD address startsat F0001H

2.
3.

To address K bytes,l5 address linesareneeded. 32 :2ts 32K = 32 x 1024: 32768 EachEPROMchip (27256)hasa chip selectCS, input. Whenthrs input is asserted low, the addressed byte in a devicewill be output on the data bus. The decoder (74LS138) makes surethat the CS inputof only oneEPROMdeviceat a time is low. (74LS138) enabled makingits G, and q inputslow and its G, If the decoder is by line inputhigh,thenonly oneoutputof thedevice will be low at a time.Address Al6 is connected the G, . to Theoutputthatwill be low is determined the3 bit address applied theC, B andA to by select inputs. If ABC = A,n A,, A,, = I I I, thentheY, outputwill be low andall theotheroutputs will be high.This will assert CS inputto EPROM the If ABC : A,n A,, A,, = 001, then the Y, outputwill be low and RAM will be selected. +Vcc

4.

5.

Arn A,, A,,

A B

, Y

Y ,
Y2 Y3 Yo

o
To RAM

A.^ RD

q
-G,

5
Y6

74LS138

Y'

ToEPROM

Fig.3.l I Decoder

8o86 System Design

3.23

\o

-s

(\
a< k1

v \ \o \ \ A<

v
\o

'!>

a\

a t t ' t
OUJOOOIJJE

*i
r,

f? i

Etsl3
@
@

3.24

Micr opro ce ssors o nd Mic r ocontr olbr s

t\t

tr
a)
H = r rYl

d a
*i t:
lr.

-6 ri

x cl i ) .r
rrE

.t) .t)

o t t ]

* o

t;i 6

*.

i:

X x Y

gg<

,\

O O O

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lines,A, to A,, lines areused'Ao As 32 K bytesEPROMandRAM need15 address and g11B are usedto selectevenand odd memorybanksrespectively. H range:00000H- 0FFFF RAM address startsat 00000H and EVEN address startsat 00001H ODD address

8086and EPROM,RAM memorychipsand between Fig.3.l2 showsthe interface for Table3.4 showsthe address memorychips. DesignExample 2: with thefollowingfeatures: system Designan 8086based i. ii. iii. iv. Solution: l. Z. 3. 8086shouldbe in Maximum Mode. is Sincea mathco-processor to be connected, with oscillatoris to be To get 8086 working at 4.77 MHz,8284A clock generator connected. of Two numbers 32 KB EPROM(EVEN and ODD) Two numbersof 32 KB RAM (EVEN and ODD) linesareused(2'5:32 KB) l5 For 32 KB EPROM/RAM, address lines : A,-A,, Address Ao and gffi 4. are usedto selectEVEN and ODD memorybanksrespectively' range= F0000H to FFFFFH EPROMaddress startsat F0000H and endsat FFFFEH EVEN address startsat F0001H andendsat FFFFFH ODD address 5. H range:00000H to OFFFF RAM address startsat 00000H andendsat OFFFEH EVEN address H startsat 00001H and endsat OFFFF ODD address 6 externallyusing bus controller In maximummodethe following signalsare decoded (8288) : / D T / R - D a t aT r a n s m t t R e c e t v e DEN 3.26 DataEnable
Mirrropr ocessor s an d Mict ocontr oller s

8086CPU workingat4.77MHz is 8087Math Co-processor connected 64 kB of EPROM for storingthe systemsoftware 64 k B of RAM

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3.28

Mirrroprocessorsond Micr. aontroller

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Address Latch Enable

M R D C . Memory Read Control MWTC -Memory Write Control IORC - I/O Read Control
IOWC - I/O Write Control 3.4.2 Memory and I/O Interfacing in 8086 based system Design Example 3: Desin a 8086 basedsystemfor memory and I/O interfacewith 16 KB EPROM and 16 KB RAM. The system require 8279 for Keyboard/Display interface and 8255 for I/O ports. Solution : The l6 KB EPROM is implementedin 2 x 8 KB. One of the 8 KB EPROM is mapped lines A,-A,3 are connectedto eachEPROM as evenbank and other as odd bank. The address IC (2764) to selectinternal locationsof EPROM. The 16 KB RAM is implementedin 2 x 8 KB. One of the 8 KB RAM is mappedas even bank and other as odd bank. The addresslines A,-A,3 are connectedto each RAM IC (6264) to selectthe internal locationsof RAM. The memory and I/O interfacein 8086 is shown in figure 3.14. The addressline Al of 8086 is connectedto addressline A0 of 8279 and the addresslines A, and A, of 8086 are 2 connected addresslines Ao and A, of 8255 to provide the required internal addresses. to to 4 decoders are used to generate69 signals.A,, and A,n as input and each decoderproduce four decodedoutput signals.One ofdecoder is enabledby addressline Ao and the ouput of this decoder are used as CS signal for even bank memory ICs, 8279 and 8255. The other decoderis enabledby the control signal g11B and the output ofthis decoderare usedas 6 signals for odd bank memory ICs. The addressesallotted to memory and I/O devices are shownin table 3.6. 3.5 MULTIPROCESSOR CONFIGURATIONS

Multiprocessor A multiprocessorsystemwill have two or more processorsthat can executetnstructions or perform operationssimultaneously. Need for Multiprocessor Systems : l. Due to limited datawidth and lack of floating point arithmetic instructions,8086 requiresmany instructronsfor computingeven single floating polnt operation.For (8087) can help 8086 processor. this Numeric Data Processor

8086SJstem Design

3.29

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Someprocessorlike DMA controllerscan help 8086 with low level operations, while the CPU can take care of the high level operations.

A d v a n t a g e s: l. 2. 3. 4. may be combinedto fit the needsof an applicationwhile Severallow cost processors avoiding the expenseof the unneeded capabilitiesof a centralizedsystem. It is easy to add more processorfor expansionas per requirement. When a failure occurs, it is easierto replacethe faulty processor. In a multiprocessor system implementation of modular processing of task can be achieved.

Basic Multiprocessor Configurations: 1. 2. 3. Co processorconfiguration Closelycoupledconfiguration Loosely coupledconfiguration

3.5.1 Coprocessor Configuration In coprocessor configuration both the CPU (8086) and external processor(Math Coprocessor8087) shareentire memory and I/O sub system.They also sharesamebus control logic and clock generator. 8086 is the masterand 8087 is the slave.
8086 Coprocessor 8086
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Fig. 3.15 Interaction between 8086 and Coprocessor

3.32

Microprocessorsand Microcontrollers

by to add Coprocessors instructions the instructionset.An instructionto be executed (ESC)prefix or instruction. the coprocessor indicatedby an escape is L 2. 3. 4. the The 8086fetches instructions. and capturesits own monitors the instruction sequence . The coprocessor instructions. simultaneously. by The ESCis decoded the CPUandcoprocessor of the The CPU computes 20 bit address memoryoperandand doesa dummy address ofthe dataandobtainscontrolofthe the read.The coprocessor captures bus to load or storeas needed. sends BUSY (high)to the fgsf The coprocessor pin. the The CPU goesto thenext instructionand if this is an 8086instruction, CPU in execute parallel. andcoprocessor the instruction occurs, 8086mustwait until BUSY goes coprocessor If another is this, a WAIT instruction put in active.To implement low ie, TEST pin become by front of most 8087instructions the Assembler. ie, The WAIT instructiondoesthe operations wait until the TEST pin is active. The coprocessor also makesuse of QueueStatus(QS'-QSr) of the 6086 queue. instructions

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8086and8087. Fig. 3.15shows interaction the between 3.5.2 Closely Coupled Configuration are configurations similarin that both the 8086and Coprocessor closelycoupled and (8089)share: the externalprocessor Memory I/O system BusandBuscontrollogic Clock generator processor shownin ts or The interactionbetween8086and coprocessor independent Fig.3.l6.
EoE6 SystemDesign

3.33

Coprocessor or Independent Processor

Configuratior, Coupled Fig.3.16Closely and The main differencebetweencoprocessor closely coupledconfiguration is, no special processor The communicationbetween8086 and independent instructionWAIT or ESC is used. is done through memory space. in As shown in Fig.3.17,the 8086 setsup a message memory and wakesup independent processorby sending command to one of its ports. The independentprocessor then accesses the memory to executethe task in parallel with the 8086. When task is completed the external processorinforms the 8086 about the completion of task by using either a statusbit or an lnterrupt request.

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3.34

Miooprocessors and Miqocantrollerc

3.5.3 Loosely Coupled Configuration In loosely coupled configuration a number of modulesof 8086 can be interfacedthrough a common systembus to work as a multiprocessorsystem.Each module in the loosely coupled microprocessor basedsystemwith its own clock source,and configurationis an independent its own memory and I/O devicesinterfacedthrough a local bus. Each module can also be a The block diagram ofa loosely closely coupledconfiguration ofa processoror coprocessor. in fig. 3.18. coupledconfigurationof 8086 is shown

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8086 SJstem Design

3.35

Advantages l. 2. Better systemthroughputby having more than one processor. The system can be expanded in modular form. Each processor is an independentunit and normally on a separatePC board. One can be added or removed without affecting the others in the system. A failure in one module normally does not affect the breakdown of the entire system and faulty module can be easily detectedand replaced. Each processormay has its own local bus to accessdedicatedmemory or IiO devices so that a greaterdegreeofparallel processingcan be achieved. Bus allocotion schemes: i. ii. iii. 3.5.3.1 Daisychaining Polling method IndependentPriority Daisy Chaining

3. 4.

In Daisy Chaining method all mastersmake use of the same line for bus request.In responseto a bus request,the controller sendsa bus grant if the bus is free. The bus grant signal serially propagates through eachmasteruntil it encounters first one that is requesting the accessto the bus. This master blocks the propagationof the bus grant signal, activatesthe busy line and gainscontrol of the bus. Thereforeany other requesting module will not receive the grant signal and hence cannot get the bus access. This bus allocation schemeis simple and cheaper. But failure of any one mastercauses the whole system to fail and arbitration is slow due to the propogation delay of bus grant signal is proportionalto the number of masters.

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Fig. 3.19 Daisy Chaining Method

3.5.3.2

Polling Method

In polling method, the controller sendsaddressof device to grant bus access.The number of addresslines required is dependon the number of mastersconnectedin the system. 3.36 Micr. ocessors Microcontrollers opr and

line is required.In response one address in are For example,if 3 masters connected the system, When the requesting master addresses. of a to a bus request,controller generates sequence it masterrecognizesthe address, activatesthe busy line and begins to use the bus. stored in the controller' The priority can be changedby altering the polling sequence of Another one advantage this method is, if one module fails entire systemdoesnot fail. The connectiondiagramfor polling methodis shown in figure 3.20.

Fig, 3.20 Polling Method

3.5.3.3

Independent PrioritY

In the independentpriority scheme each master has a separatepair of bus request (BRQ) and bus grant (BGR) lines and each pair has a priority asstgnedto it' The built in priority decoder within the controller selectsthe highest priority request and assertsthe bus grant signal. Synchronizationofclocks must be performed once a master corresponding Master will receivea common clock from one side and passit to the controller is recognized, which will derive a clock for transfer. Due to separatepairs of bus request and bus grant signals, arbitration is fast. The priority methodis shown in figure 3 '21. connectiondiagramfor independent
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Design 8o86System

3.37