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Sorter-Based Arithmetic Circuits for Sigma-Delta Domain Signal ProcessingPart II: Multiplication and Algebraic Functions
Hisato Fujisaka, Member, IEEE, Masahiro Sakamoto, Chang-Jun Ahn, Member, IEEE, Takeshi Kamio, and Kazuhisa Haeiwa, Member, IEEE

AbstractWe construct arithmetic modules for signal processing with sigma-delta modulated signal form which has advantage in signal quality over other pulsed signal forms. In the second part of this paper, multi-input multipliers are presented rst. Secondly, dividers and square root function modules with the multiplier on their internal feedback path are constructed. Combined use of the multipliers, dividers, and the square root functions creates various algebraic functions including polynomial and rational functions. Only two bit-manipulations, bit-permutation with sorting networks and bit-reversal with NOT gates, have built up all the algebraic operations on any form of SD modulated signals. These modules, together with transcendental functions presented in the rst part of this paper, organize an extensive module library for the sigma-delta domain signal processing. The multiplier output contains noise components which originate from quantization. The noise power can decrease in exchange for circuit complexity. A time-division multiplexing technique based on N-tone sigma-delta modulation is applied to the multipliers for reducing the complexity. Signal processing circuits built of nanometer-scale quantum effect devices must be equipped with fault tolerance of transient device error. By computer simulation of a multiplier built of single-electron tunneling devices, we found that the multiplier decreased its output SNDR from 43 to 27dB at as the device error rate increased from 0 to . an OSR of However, the multiplier was never functionally failed during the simulation. Index TermsAlgebraic function, fault tolerance, multiplier, sigma-delta modulation, single-electron tunneling, time-division multiplexing.

I. INTRODUCTION ECENT circuit integration technologies have shrunk electronic circuits to nanometer scale. Quantum discontinuous phenomena which appear in nanometer-scale make it difcult to construct analog circuits. Analog signal processing (ASP) circuits seem to disappear from nanoelectronic systems together with their long-historical design techniques. On the

Manuscript received May 16, 2011; revised September 19, 2011; accepted November 10, 2011. This paper was recommended by Associate Editor H. Gao. H. Fujisaka, T. Kamio, and, K. Haeiwa are with the Faculty of Information Sciences, Hiroshima City University, Hiroshima, 731-3194 Japan (e-mail: fujisaka@info.hiroshima-cu.ac.jp; kamio@info.hiroshima-cu.ac.jp; haeiwa@info.hiroshima-cu.ac.jp). M. Sakamoto is with the Faculty of Engineering, Saitama Institute of Technology, Saitama, 369-0293 Japan (e-mail: sakapon@sit.ac.jp). C.-J. Ahn is with the Faculty of Engineering, Chiba University, Chiba, 2638522 Japan (e-mail: junny@faculty.chiba-u.jp). Color versions of one or more of the gures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identier 10.1109/TCSI.2011.2180450

other hand, highly integrated and/or high performance digital circuits are expected to be constructed of the devices taking advantage of quantum effects. However, fault tolerance of highly frequent transient errors of the devices must be established for the digital circuits to be practical. Pulsed signal processing (PSP) is considered as a scheme which overcomes above raised two problems on nanometerscale analog and quantum effect digital circuits. That is, PSP circuits constructed based on ASP-like architecture can be faulttolerant. Sigma-delta domain signal processing (SDSP) [2][4] which employs high quality sigma-delta (SD) modulated signal forms [5], [6] has advantage in processing precision over other PSP schemes. In a companion paper, Part I [1], adders, piecewise-linear (PWL)-approximate transcendental functions, and ASP-like log-domain arithmetics all of which employ rst/second-order binary/multilevel SD modulated signal forms have been presented. A log-domain multiplier presented in Part I relies on PWL approximation which distorts outputs. Two-input multipliers which do not depend on PWL approximation have been proposed for SDSP [7][9]. However, the conventional multipliers have at least one of the following drawbacks: First, multiplication and multiplicand are limited to rst-order SD modulated signals. Secondly, many two-input multipliers are necessary for higher-order polynomial functions. Multi-input multipliers computing higher-order terms of polynomials are anticipated. In the second part of this paper, Part II, we will attempt to construct multi-input multipliers operating on rst/second-order SD modulated signals of arbitrary quantization steps without the PWL approximation scheme. In Part II, an adder and a multiplier will be constructed of single-electron tunneling (SET) devices [10] as examples of SDSP modules built of quantum effect devices. The latent fault tolerance of SDSP modules to transient device error will be revealed also in Part II by evaluating the output quality of the two arithmetic modules built of unreliable devices. The rest of Part II is organized as follows: In Section II, we will develop multi-input multipliers. In Section III, polynomials are constructed by using the multipliers. In addition, rational and radical functions are built by inverse function scheme [11] with the multiplier placed on their feedback path. The multiplier output contains noise components which originate from quantization. Section IV is devoted to the noise analysis. The analysis will show that the noise power will be able to decrease in exchange for circuit complexity. In Section V, a time-division

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When multiple inputs and an output of a multiplier archetype are -level signals represented by bit-streams, , , , , the output average should be

(3) exclusive-NOR funcThen, multiplier archetypes consist of tions and -level adders presented in Section III of Part I for summing the exclusive-NOR outputs. B. Attenuation of SD Modulation Noise
Fig. 1. Exclusive NOR circuits built of sorting networks and NOT gates.

multiplexing technique is applied to the multipliers for reducing their circuit complexity without increasing the noise power. In Section VI, arithmetic modules are built of SET devices and their fault-tolerant capabilities are evaluated. Finally, we conclude Part II in Section VII. II. MULTI-INPUT MULTIPLIERS

Mixing the inputs containing large SD modulation noise in high frequency band by the multiplier archetype generates products of the modulation noise components in low frequency signal band. The products of the noise components degrade multiplier outputs. We attempt to remove the modulation noise from the inputs by lters before the multiplication. We denote an input ltered with a nite impulse response (FIR) lter with coefcients by using the same notation as a locally averaged input as follows: (4)

A. Multiplier Archetype Using elemental bit-manipulators for SDSP, sorting networks, and NOT gates, we construct a multi-input multiplier archetype for SDSP. Let multiple inputs and output of a multiplier archetype be denoted by . , and . The local average of output should be equal to the products of the local averages of inputs, that is, (1) so that multiplication is carried out in SD domain. When we let , logic values {0, 1} represent binary integer values exclusive-NOR operation (2) is equivalent to multiplication of binary integer values. On the assumption that inputs are independent of one another, the multiplication with an exclusive-NOR circuit holds (1). Then, we use exclusive-NOR circuits as multiplier archetypes. Fig. 1(a), (b), and (c) shows exclusive-NOR functions built of sorting networks and NOT gates. Since we need only the center output, the sorter on the output-stage is substituted by a linear threshold gate (LTG) as shown in Fig. 1(d). We will use circuits of the same type with Fig. 1(d) as exclusive-NOR circuits in multipliers and algebraic modules to be presented in Part II. The ltered input is no more a SD modulated signal and multiplication after the ltering (5) is not SD domain operation any more. By expanding (5), we transform the products of input averages into weighted-sum-ofpartial-products form, as given by

(6) are computed with the Then, partial products multiplier archetypes and the weighted sum is executed with a network of adders similar to that used in PWL-approximate functions in Part I. Fig. 2 shows a multiplier operating according to (6) when the number of inputs is , signals are 4-level quantized, and the FIR lters have 3 taps. The coefcients of the lter described by (4) are , , . Then, weights in (6) are determined and weighted sum operation is executed with two 2-input and one 8-input Type-I adders. All the partial products are 4-level quantized with digital SD modulators with 9 input bits.

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Fig. 3. Sets of all the partial products for the outputs of cubic multipliers and subsets of partial products for the outputs of plane multipliers.

Fig. 2. Example of multiplier. (a) Circuit computing 4-level quantized partial product. (b) 4-level multiplier (sll the bold lines are bundles of 3-bit lines).

When FIR lters given by the following transfer function of order in the -domain are used,

(7) must be greater than the order of SD modulation, i.e., (8) for the lter to attenuate SD modulation noise sufciently. Filters of multipliers being presented in Part II will take or 3 for rst-order SD modulated signals and or 4 for second-order signals. We will see in Section IV that the lters with larger than these values do not always effectively improve the quality of multiplication. Since the noise power concentrates in higher frequency region centered at , : signal rate, should be even. For the lter not to attenuate signal components contained in , its cutoff frequency should be higher than signal band . Since , should satisfy the following inequality:

Fig. 4. Partial products organizing output sequences of two-input cubic and plane multipliers. (a) Partial products contributing to the output of a cubic multiplier. (b) Partial products contributing to the output of a plane multiplie.

(9) We will see in Section IV that lters with large is effective to improve the quality of multiplication. However, circuit complexity increases as is larger. In Sections III and IV, lters with , 8 will mostly be used. Signal rate is normalized as hereafter unless otherwise stated. C. Partial Product Set In the multiplication dened by (6), multiplier archetypes compute partial products of inputs with delay indices

. The partial products contributing to the multiplication are designated by points in the delay index coordinate system. When the number of inputs and 3, for example, the points are at the centers of unit squares and cubes shown in Fig. 3(a) and (c). In this paper, the multipliers weighting and summing all the partial products indicated by unit cubes in a -dimensional cube of side length are referred to as cubic multipliers. Large number of exclusive-NOR circuits and adders are necessary to build a cubic multiplier when large or is specied. We will reduce the number of partial products. Let us consider rst a simple multiplier with . Fig. 4(a) shows a product sequence outputted

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from a cubic multiplier and sets of partial products organizing the product sequence. The cubic multiplier makes same partial products involved in its output at several consecutive time steps. Fig. 4(b) shows an another product sequence and sets of partial products contributing to the product sequence. Each partial product belongs to only one of the sets without redundancy. Let a subset shown in Fig. 3(b) be denoted by

D. Weighted Sum Network We construct at and layer-structured adder networks for computing weighted sum of partial products in multi-input multipliers. The network shown in Fig. 2 has tree structure with an output at the root node and partial products at leaf nodes. The network has 2-input and 8-input Type-I adders between the root and four leaf nodes. Partial products at the leaf nodes connected to the 2-input adders are weighted by 1/16. Five leaf nodes are directly connected to the 8-input adder. Four partial products at the leaf nodes are weighted by 1/8. One partial product at the leaf node which connects to two inputs of the adder is weighted by 1/4. In this way any rational weight is given to each partial product with a tree-structured at network. However, it is not necessarily an easy task to determine network structure when it possesses large number of leaf nodes. Consider a layered cubic multiplier which applies the fol, : lowing lter to every input (18) Regarding each input as a function of different one of pendent time variables, we express a partial product inde-

(10) Then, each set organizing an output product in Fig. 4(b) at time is given by a union of subsets as follows: (11) , we take subsets of partial products as shown When in Fig. 3(d), that is,

(12) Three-input multipliers in which one partial product contributes to their outputs at only one time step compute weighted sum of partial products belonging to the following union of subsets:

(19) in the -dimensional -domain as

(13) -multiple multipliers compute weighted sum of partial products belonging to the following union of subsets : (14) (15) The subsets in (14) are

(20) Since each one of lters operates on different one of inputs, the weighted sum of partial products in the cubic multiplier is described in the -dimensional -domain by

(16)

(17) The number of partial products contained in the union given by (14) is in the order of while cubic multipliers use partial products. The multipliers without the redundancy of partial products are referred to as plane multipliers in this paper.

(21) In layer , , ltering is applied to the outputs from lower layer . Then, layered network of adders completes full ltering .A 2-input layered cubic multiplier is constructed as shown in Fig. 5(a) when , , and . In plane multipliers, weighted sum is computed for the partial products belonging to the union of . We describe the weighted sum of partial products in in the -domain as

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(26) The above equation implies that ltering characteristic. Similarly, for obtain has a lowpass -multiple multipliers, we (27) with the following symmetric characteristic:

(28) We build adder networks each of which executes and stack them up into a -layered network performing . In plane multipliers, weighted sum must be computed for the partial products belonging to the union given by (14). We then stack up one more layer where the outputs of the -layered networks are summed as follows:
Fig. 5. Layered cubic and plane multipliers. Li and PP respectively denote a circuit in layer i and a multiplier archetype computing a partial product. (a) Cubic multiplier. (b) Plane multiplier.

(29) A 2-input palne multiplier is constructed as shown in Fig. 5(b) when , , coefcients of are {1/4, 1/4, 1/4, 1/4}, and coefcients , , 1, 2, in (29) are {1/4, 1/2, 1/4}. We estimate output delay of the presented multipliers. It takes -bit duration in average for input signals to enter partial product computation circuits. One-bit duration is necessary for digital SD modulators to quantize partial products when multilevel signal form is employed. We saw in Section III of Part I that adder outputs delay by one-bit duration relatively to inputs. In each layer of the multipliers, an adder sums signals from lower layers. Thus, outputs of layer-structured cubic and plane multipliers delay respectively by and -bit durations. III. EXAMPLES OF ALGEBRAIC FUNCTIONS Polynomial functions whose outputs average by are given in

(22) For all the input terminals of a plane multiplier to be identical, the above operation must be invariant under any permutation of the elements of , that is, (23) . We determine the coefcients of so that it is equivalent to executed in a layer of cubic multipliers when either of their two inputs is xed, that is, Let (24) When , as follows: is obtained by using

(30) (25) 2, 3, and 4-input plane multipliers and are constructed of 2-input Type-II adders presented in Section III of Part I. The signal form of the polynomial functions and their internal arithmetic modules is rst-order binary SD modulated bit-stream. The parameters of the adder networks used for the multipliers are and . Fig. 6 shows their output averages when SD modulated sawtooth input is applied. The output

are determined so that where coefcients has the symmetric property given by (23). Then,

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Fig. 6. Averaged input and output waveforms of the second, third, and fourthorder polynomial functions. Small squares on the averaged output waveforms indicate ideal values.

Fig. 8. Square root circuit.

Fig. 9. Normalization module. Fig. 7. Divider circuit.

averages are obtained by 50-point moving average. The small squares in Fig. 6 indicate ideal values obtained from (30). The maximum errors of the output averages of the second, third, and fourth polynomials to the ideal values were 0.044, 0.047, and 0.081, respectively. We will build a simplest rational function module [7] whose output is the ratio of input to in average, (31) The module, divider, is indispensable to construct various rational function modules. In Part I, we built logarithmic function modules as inverse functions of exponential functions. We construct here a divider as an inverse function of multiplication in the same way. Fig. 7 shows a feedback circuit built of a sorting network, a digital SD modulator, and a multiplier on its negative feedback path. The sorting network with positive feedback loops operates as an integrator. The digital SD modulator converts sorted outputs into a SD modulated signal. Since the modulator inputs are sorted, smaller size of mergers are used instead of a sorting network in the modulator. The negative feedback loop makes the output of the multiplier track input . Thus, the feedback circuit functions as a divider described by (31). Note that the response of the feedback circuit has time lag since it is dynamical. According to the same inverse function technique, we construct a th root module with a -input multiplier. Fig. 8 shows a square root (SQRT) module with a two-input multiplier operating as a squarer. Since the negative feedback loop makes the output of the multiplier track input , the following equation is satised: (32)

is the square root of input Then, the module output in average. Using the dividers and the SQRT module, we construct a function module which normalizes vector input as follows:

(33) Fig. 9 shows the module. The magnitude of the vector input is computed with two multipliers operating as squarers, a Type-II adder, and a SQRT module. The two dividers normalize the vector in a way that . We built a normalization module with rst-order 4-level SD modulated signal form. The multipliers utilized as squarers and employed in the dividers and the SQRT module include an adder network of and . The size of sorting networks used for integrators in the dividers and the SQRT module are 30 bits. The center 24 output bits of the sorting networks are positively fed back and connected to the digital SD modulator in the modules. Fig. 10 shows behavior of the normalization module when SD modulated sinusoidal signals , are applied. The amplitude, frequency, and the phase of sinusoidal signals , , 2, are as follows: , , and , . The difference between obtained by 50-point moving average and the magnitude of the input vector was less than 0.027. Table I(a) shows the necessary numbers of unit delays, NOT gates, and LTGs to build the modules exemplied in this section. The table also shows the complexity of the modules in CMOS gate equivalent unit. The inputs and outputs of the modules are rst-order binary or 4-level SD modulated signals. As has been mentioned, parameters of the adder networks in the multiplier and those used for the modules are and . A 10-bit

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TABLE I CIRCUIT COMPLEXITY OF THE SDSP FUNCTION MODULES AND CONVENTIONAL MULTIBIT MODULES. (A) CIRCUIT COMPLEXITY OF THE FUNCTION MODULES IN SECTION III; (B) CIRCUIT COMPLEXITY OF CONVENTIONAL MULTIBIT MODULES

structure of multipliers. Multipliers to be analyzed will be limited to two-input multipliers. A. Decomposition of Output Noise Signals , , 2, inputted to a multiplier are expressed by the sum of signal and SD modulation noise components as follows: (34) and are internal quantization error sequences where of SD modulators formatting the inputs and , : integer, is an th-order difference operator. First and second-order SD modulation noises are expressed by

Fig. 10. Averaged input and output waveforms of the normalization module. (a) Inputs. (b) Outputs.

integrator and an 8-input digital SD modulator are used for the binary divider and SQRT module. The modules are used for the binary normalizer. Table I(b) shows complexity of multipliers, polynomial functions, a divider, a SQRT module, and a normalizer all of which are constructed in conventional multibit style. The multipliers are array-type Braun multipliers built of AND gates and full adders [12]. The second, third, and fourth-order polynomial functions are built by using 2, 3, and 4 multipliers. The divider and the SQRT module are constructed with a 16-bit integrator and a 16-bit multiplier on their feedback path in a similar way to those shown in Figs. 7 and 8. The normalizer in the table is constructed by using the two dividers, the SQRT module, and two 8-bit multipliers as shown in Fig. 9. Comparing Tables I(a) and (b), we see that it costs high for SDSP with high-order algebraic functions and high quality signal form. IV. OUTPUT QUALITY OF THE MULTIPLIERS In the previous sections, only exemplied modules with xed parameters are evaluated in output error. The evaluated error is the maximum value of the ltered noise and distortion components contained in the module outputs. In this section, we will evaluate directly the output noise and distortion components of multipliers, the essential modules for algebraic functions, and investigate their dependence on signal form and the

(35) We describe output of the multiplier as

(36)

(37)

(38) (39)

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Fig. 11. Output power spectra of plane multipliers. They are obtained by 2 -point FFT. (a) Signal form: 1st-order binary, Size of adder network: ; (b) Signal form: 1st-order binary, Size of adder network: , ; (c) Signal form: 1st-order 4-level, Size of adder network: , , . (d) Signal form: 2nd-order binary, Size of adder network:

, ;

For plane multipliers, many of the coefcients are given zero. Equation (36) shows that the multiplier output contains the following noise components in addition to signal component i) : ii) : Weighted sum of products of SD modulation noise components contained in inputs. iii) : Weighted sum of products of SD modulation noise and signal components contained in inputs. iv) : Weighted sum of SD modulation noise caused by digital SD modulators requantizing partial products (see Fig. 2(a)). v) : Quantization noise generated from an adder network computing weighted sum of partial products. Fig. 11 shows output power spectral density (PSD) of four 2-input multipliers operating on rst-order binary, rst-order 4-level, and second-order binary SD modulated signals. All the multipliers are plane multipliers with layered structure of or 4 and or 8. We see in Fig. 11 that the output PSDs increasing with frequency at a maximum ratio of 20 and 40 dB/decade are rst and second-order noise-shaped. Thus, and are the main components of the shaped noise in high frequency band. Noise is produced by mixing the attenuated input noise components with exclusive-NOR circuits. Therefore, the spectrum of spreads widely. The low frequency at noise oor observed in Fig. 11(a) and (d) is considered as the components of . Noise is decreased by employing an adder network of large parameter and multilevel signal form, which is realized by the comparison between Fig. 11(a) and (b) and between Fig. 11(b) and (c). Since the frequency components of and the components of do not exist in the same frequency band, the power of signal band components of is small. B. Noise and Distortion Power Versus OSR Figs. 12 to 16 show output noise power versus OSR curves obtained by computer simulation. Inputs to the multipliers are assumed to be SD modulated sinusoidal waves of amplitude 0.75 and frequencies and . The SD modulator shown in Fig. 3 in Section II of Part I is used for the second-order SD modulation of the inputs. Its coefcients are . Layered networks computing weighted sum of partial products in the evaluated multipliers consist of -input adders.

Fig. 12. Output noise power versus OSR curves for layer-structured plane multipliers with rst and second-order binary signal forms. The adder networks are , (rst-order), (second-order). of

Fig. 13. Output noise power versus OSR curves for layer-structured plane multipliers with rst-order binary, 4-level, and 6-level signal forms. The adder net, . works are of

Fig. 12 shows output noise of plane multipliers with rst and second-order SD modulated signal forms. From (9), OSR should be higher than . On this OSR condition, the slope can be steeper than 3 dB/octave. Therefore, we can say that the multiplier outputs are noise-shaped. When OSR is low, the

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Fig. 14. Output noise power versus OSR curves for layer-structured plane mul, 4, and 8 and . The signal form tipliers with adder networks of is rst-order binary form.

Fig. 15. Output noise power versus OSR curves for layer-structured plane muland , 2, 3, and 4. The signal form tipliers with adder networks of is rst-order binary form.

multiplier when OSR is low. Thus, to adopt second-order SD modulated signal form is effective in reducing output noise if OSR is limited to be low. As OSR becomes higher, the slope approaches to 3 dB/octave. This is due to the at oor of the noise spectral distribution shown in Fig. 11(b) and (d). In Fig. 13, output noise power of rst order plane multipliers is plotted against OSR for different numbers of quantization steps. Power spectral density of the SD modulation noise decreases by 9.5 and 14 dB when is increased from 1 to 3 and 5, respectively. In a low OSR region, the noise of the multiplier outputs is decreased by almost the same power. The power of , product of the SD modulation noises, decreases by 19 and 28 dB when is increased from 1 to 3 and 5. Since most of the noise components in the signal band are considered as the components of , the output noises of the multipliers with and 5 are considered to decrease in the same way in a high OSR region. Although the curves plotted in Fig. 13 do not decrease as estimated, it decreases more at high OSR than at low OSR. Fig. 14 shows output noise power of rst-order binary plane multipliers for several integer values . Increasing expands the area where the slope is steeper than 3 dB/octave. In addition, as increases, the noise power efciently decreases when OSR is high. The cutoff frequency of the lters described by (7) is inversely proportional to . Then, the power of rst-order SD modulation noise components in is inversely proportional to . The power of noise component of the multipliers is then proportional to . Therefore, output noise power is considered to decrease by 18 dB in a high OSR region as is doubled. In Fig. 14, the noise power evaluated by circuit simulation decreases by 10 to 15 dB. Fig. 15 shows output noise power versus OSR curves for various integer values . For the rst-order plane multipliers, increasing from 2 to 3 is effective in reducing the noise power. However, increasing from 3 does not decrease the noise power. This is simply because the characteristics of FIR lter in (22) hardly depends on when . Fig. 16 compares output noise power between cubic and plane multipliers with rst-order binary signal form. From the gure and Fig. 15, we realize that parameter should be 3 for the plane multiplier to be equivalent to the cubic multiplier in output quality. Even if , the network of adders for the plane multiplier can be smaller than that of the cubic multiplier with when . Thus, plane multiplier structure contributes to reducing hardware cost. C. Noise and Distortion Power versus Amplitude We saw in Section III of Part I that saturation of the integrators built of sorting networks distorts the outputs of second-order adders when SD modulated signals with large magnitude in local average are given to the adders. The multipliers with networks of second-order adders are also considered to output distorted products. We investigate the distortion by computer simulation. The multipliers to be investigated are 2-input binary plane multipliers. Their adder networks are of size and . In the experiments, second-order SD modulators with coefcients and are used so as to generate low distortion input signals. Frequencies of the inputs are

Fig. 16. Output noise power versus OSR curves for layer-structured cubic and plane multipliers with rst-order binary signal form. The adder networks are of , .

slopes of the curves can be almost as steep as those for rst and second-order SD modulated signals. That is, the decreasing rate of to OSR can be close to 9 and 15 dB/octave for the rst and second-order multipliers. The curve for the second-order multiplier is lower than that for the rst-order

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Fig. 18. N-tone SD modulator and its modulation noise spectrum. (a) Block diagram of rst-order N-tone SD modulator. (b) Spectral distribution of N-tone . SD modulated signals

Fig. 17. Output SNDR versus input power curves for second-order plane multipliers. Parameters , , , and are the numbers of lines which characterize adders for weighted sum of partial products (For the parameters, see Section III, , ; (b) the numbers of Part I). (a) The numbers of feedback lines: , . feedback lines:

and . Fig. 17 shows output SNDR plotted against input power at OSR of . We nd that the output SNDR of the multipliers can be higher when we construct the multipliers by using adders with larger sorting networks. However, compared to the SNDR versus amplitude curves presented in Section III in Part I for adders, the inuence of amplitude to the output SNDR is smaller. This is simply because the frequency components of are larger than distortion components. V. TIME-DIVISION MULTIPLEXING MODULATION
BY

N-TONE SD

The simplest way to improve output quality of multipliers is to rise signal rate or OSR. However, the decreasing ratio of the output noise power to OSR approaches to 3 dB/octave because of output noise component . Another way to increase output quality is to employ multilevel and/or higher-order signal forms. When both the rate and the form of signals are specied, constructing an adder network with large and is the only way to improve output quality. We saw in Section II-C that the number of partial products to be summed increases in polynomial order as increases. Then, the adder network must be constructed of large number of adders. Even though SDSP circuits are intended to be constructed of nanometer-scale quantum effect devices, it may be required to reduce the number of adders. One way of reducing it is time-shared use of small number of adders. In this section,

we will establish this time-division multiplexing (TDM) technique by N-tone SD modulation. The TDM technique can also be applicable to the adder networks of PWL-approximate function modules in Part I. Fig. 18(a) shows an N-tone SD modulator [13]. One and delay time steps of internal delay elements are only the difference between baseband and N-tone SD modulators. Let be the noise transfer function of a baseband SD modulator. The noise transfer function of the N-tone SD modulator is given by . Then, modulation noise contained in N-tone SD modulated signals has lobes in the frequency domain, as shown in Fig. 18(b). Thus, N-tone SD modulator can convert signals possessing equally spaced spectra around , , into one-bit or short-word digital signals. Consider a narrow band discrete-time signal sampled at a rate of . Decimating and down-sampling the signal by change its period of spectral distribution from to . The spectrum of the down-sampled signal locates between the lobes of N-tone SD modulation noise spectrum. Thus, N-tone SD modulators can successfully modulate the down-sampled signals. Moreover, one modulator can modulate down-sampled signals in turn for -step time interval, as shown in Fig. 19(a). However, the following output degradation should be noted: th-order -tone SD modulated signals contain in-band noise which is approximately times larger in power than that of general SD modulated signals, which we realize from (7) in Section II-A of Part I. Circuit modules for SDSP can be changed to TDM modules simply by replacing their internal unit delays with integer delays and adding multiplexers at their inputs and outputs. For example, a TDM adder is built as shown in Fig. 19(b). It carries out independent additions, , , for -step time interval. By making the adder operation times faster, the sum operations are carried out in one time step. This TDM technique can be adopted in part or whole of a SDSP system in order to reduce its circuit complexity. For example, we apply the TDM technique to the circuits in every layer of the plane multiplier shown in Fig. 5(b). An equivalent multiplier can be constructed with only one adder in each layer, as shown in Fig. 20. The total number of adders is reduced from

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FUJISAKA et al.: SORTER-BASED ARITHMETIC CIRCUITS FOR SIGMA-DELTA DOMAIN SIGNAL PROCESSINGPART II 11

Fig. 21. Linear threshold gate built of SET junctions.

respectively. The number of unit delays, 236, is not decreased. Note that the adders in layers L1 and L2 respectively operate at and in order to maintain operation speed and output quality. VI. SET CIRCUITRY AND FAULT TOLERANCE In this section, we will construct adder and multiplier modules of SET devices [10] rst. Quantum effect devices including SET devices are sensitive to various external and internal interferences, as mentioned briey in Section I of Part I. The sensitivities cause frequent transient device errors in digital circuits. Secondly, we will evaluate the capability of the two modules for fault-tolerance of transient device errors by numerical experiments. A. Circuit Modules Constructed of SET Junctions The SDSP modules presented in Part I are constructed of only three kinds of circuit cells, LTGs for sorting networks, NOT gates, and integer delays. Multipliers are constructed by using integer delays, exclusive-NOR circuits, and a network of adders. Exclusive-NOR circuits consist of LTG-based sorting networks and NOT gates, as shown in Section II-A. Thus, multipliers can also be built of the three circuit cells. However, simple exclusive-NOR gates may be necessary when large number of partial products are required for high quality outputs. Simple exclusive-NOR gates built of SET devices have been reported, for example in [14]. Referring to [15][17], we built the three circuit cells of SET devices as shown in Figs. 21, 22, and 23. An -input LTG circuit expressed by if if ,

Fig. 19. Time division multiplexing by N-tone SD modulation. (a) SD modu. (b) SD domain TDM adder. lation of down-sampled signals

(40) is constructed of SET junctions as shown in Fig. 21. Inputs and are weighted positively and negatively. The weights are functions of the capacitances in the circuit cell. Threshold level is determined by and . Fig. 22(a) shows what is called a single-electron transistor and its gate voltage versus drain-to-source current characteristic. The current peaks locate between the gate voltage regions in which the island between the two SET junctions holds integer number of excess electrons. Fig. 22(b) shows a dualgate single-electron transistor. When and

Fig. 20. A two-input binary plane multiplier employing TDM by N-tone SD modulation.

16 to 3. Removing adders decreases NOT gates and LTGs required to build the multiplier from 54 to 13 and from 144 to 39

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Fig. 24. Adder constructed of SET cells.

Fig. 22. Inverter buffer cell built of SET junctions. (a) Single electron transistor. (b) Dual gate single electron transistor. (c) Inverter buffer.

Fig. 25. Multiplier constructed of SET cells. (a) Flat-structured rst-order binary plane multiplier. (b) Exclusive-NOR circuit.

Fig. 23. Integer delay cell built of SET junctions and a clock set driving the delay cell.

, its versus curve shifts by horizontally. Let us take two dual-gate SET transistors through which drain current ow at different gate voltages for NMOS and PMOS transistors. Then, a SET counterpart of a CMOS inverter is constructed as shown in Fig. 22(c). In the modules, the inverters are used not only as NOT gates but also as buffers. Fig. 23 shows a delay cell built mainly of series tunnel junctions. The delay cell is driven by a four-phase clock set. Stimulated and synchronized with the clock signals, a single-electron tunnels through the series junctions one by one. A unit delay cell (D) has 7 series junctions. An integer delay is constructed by connecting additional junctions to the unit delay ( : integer). Fig. 24 shows a rst-order 2-input binary Type-I adder built of the three kinds of circuit cells [3], [4]. The adder consists of 63 SET junctions. Fig. 25 shows a at-structured plane multiplier with an adder network of , . Its inputs and output are in the form of rst-order binary SD modulated bit-stream. The multiplier consists of two 3-time-step delay cells, seven exclusive-NOR logic circuits, and eight two-input Type-I adders.

In this example, exclusive-NOR circuits are built of sorting networks and NOT gates faithfully to the proposed style of SDSP, that is processing bit-stream signals by bit-permutation and bitreverse. Approximately 770 SET junctions are used to construct the multiplier. In writing a netlist for circuit simulation with SIMON [18], the multiplier was divided into two blocks so that simulation for each separated block can be completed in a short time and total simulation time can be saved. We investigated the behavior of the adder and multiplier modules with SIMON under the following conditions: The clock rate is 10 MHz. Inputs to the two modules are generated by SD-modulating sinusoidal waves of full-span amplitude and frequencies and . While circuit simulation for functional verication is carried out, unintended electron tunneling through SET junctions must not be caused. Therefore, the operation temperature is set at 0 k. Fig. 26 presents output spectra of the two modules. We see that both spectra distributed highly in high frequency band are noise shaped. B. Fault Tolerance Evaluation Let a probability that an unintended single-electron passes through a SET junction for a clock period be denoted by . We assume that a circuit cell built of SET junctions outputs false signal at a probability for a clock period. The transient cell errors decrease the output SNDR of SDSP arithmetic modules. We evaluate SNDR of the outputs of the adder and multiplier modules in which circuit cells cause transient errors. Inputs are the same as the signals applied to the modules in circuit simulation with SIMON. The signal components contained in the

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FUJISAKA et al.: SORTER-BASED ARITHMETIC CIRCUITS FOR SIGMA-DELTA DOMAIN SIGNAL PROCESSINGPART II 13

Fig. 26. Output power spectra of the SET modules. The outputs are the results -point FFT of circuit simulation with SIMON. The spectra are obtained by of the outputs. (a) Adder. (b) Multiplier.

outputs of the adder and the multiplier are two frequency components of and respectively. Other frequency components are regarded as noise or distortion components. Fig. 27 shows output SNDR versus probability curves for the two modules at various OSR. Because of mixing SD modulation noises in inputs by exclusive-NOR circuits, the output SNDR of the multiplier is low. Although the output SNDRs of the two modules decrease as the error rate increases, the modules maintain their normal operations. The adder and the multiplier contain 63 and 770 SET junctions respectively. Then, one error is caused in average for one clock period in each arithmetic module when device error rates and 1/770. Nevertheless, the output SNDRs seem to be kept higher than 10 dB at around the error rate when OSR 16. We consider that this is due to the smoothing effect by the integrators in the adders and -attenuation effect by -input Type-I adders. From the discussion in Section II-A of Part I, noise power of a Bernoulli sequence in stochastic computing systems is 2/(3 OSR). We then realize that the adder output is higher than errorless Bernoulli sequence in quality even if internal devices of the adder cause error at . VII. CONCLUSIONS This paper has presented arithmetic modules for SDSP. In Part II, we have developed multi-input multipliers rst. Secondly, we have built divider and square root function modules with the multiplier on their internal feedback path. Combined use of the multipliers, dividers, and the square root functions creates various algebraic functions including polynomial and rational functions. Transcendental functions constructed in Part I include distortion components in their outputs because of PWL-approximation. On the other hand, the outputs of the algebraic functions presented in Part II are not distorted. The outputs contain another noise which originates from quantization. The noise can be decreased to less than 100 dB with networks of adders. This decrease is attained by virtue of intrinsic low in-band noise of SD modulated signals. However, the network size increases as output noise is specied to be lower. Even though SDSP circuits are intended to be constructed of nanometer-scale quantum effect devices, it may be required to reduce the network size. For

Fig. 27. Fault-tolerant characteristics of the adder and the multiplier. (a) Adder. (b) Multiplier.

the reduction, a TDM technique by N-tone SD modulation has been introduced. We saw in Section VI that the adder and multiplier circuits suffering from internal transient device errors decreased output quality but was not functionally failed. In addition, the decreased output quality was still higher than that of errorless Bernoulli sequences if the device error rate was not extremely high. In nanometer-scale circuit implementation, device defects are another concern. The SDSP modules must be equipped with fault tolerance not only of transient errors but also of permanent device defects, which is one of our future works. REFERENCES
[1] H. Fujisaka, T. Kamio, C.-J. Ahn, M. Sakamoto, and K. Haeiwa, Sorter-based arithmetic circuits for sigma-delta domain signal processingPart I: Addition, approximate transcendental functions, and log-domain operations, IEEE Trans. Circuits Syst. I, Reg. Papers, to be published. [2] V. F. Dias, Signal processing in the sigma-delta domain, Microelectron. J., vol. 26, pp. 543562, 1995. [3] T. Katao, Y. Suzuki, H. Fujisaka, T. Kamio, C.-J. Ahn, and K. Haeiwa, Single-electron arithmetic circuits for sigma-delta domain signal processing, in Proc. IEEE Conf. Nanotechnol., 2008, pp. 729732. [4] H. Fujisaka, Single-electron circuits for sigma-delta domain signal processing, in Cutting Edge Nanotechnology, D. Vasileska, Ed. Croatia: In-teh, 2010, pp. 347372. [5] , J. C. Candy and G. C. Temes, Eds., Oversampling Delta-Sigma Data Converters: Theory, Design, and Simulation. New York: IEEE Press, 1992. [6] J. M. de la Rosa, Sigma-delta modulators: Tutorial overview, design guide, and state-of-the-art survey, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 58, no. 1, pp. 121, 2011. [7] H. Fujisaka, R. Kurata, M. Sakamoto, and M. Morisue, Bit-stream signal processing and its application to communication systems, IEE Proc. Circuits, Devices, Syst., vol. 149, no. 3, pp. 159166, 2002. [8] C. W. Ng, N. Wong, and T. S. Ng, Bit-stream adders and multipliers for tri-level sigma-delta modulators, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 54, no. 12, pp. 10821086, 2007.

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[9] T. Katao, K. Hayashi, H. Fujisaka, T. Kamio, and K. Haeiwa, Sorterbased sigma-delta domain arithmetic circuits, in Proc. Eur. Conf. Circuit Theory Design, 2007, pp. 679682. [10] , H. Grabert and M. H. Devoret, Eds., Single Charge Tunneling: Coulomb Blockade Phenomena in Nanostructures. New York: Plenum, 1992. [11] R. Pallas-Areny and J. G. Webster, Analog Signal Processing. West Sussex, U.K.: Wiley, 1999. [12] I. S. Abu-Khater, A. Bellaouar, and M. Elmasry, Circuit techniques for CMOS low-power high-performance multipliers, IEEE J. Solid-State Circuits, vol. 31, no. 10, pp. 15351546, 1996. [13] E. Saberinia and A. H. Tewc, N-tone sigma-delta UWB OFDM transmitter and receiver, in Proc. IEEE Int. Conf. Acoust., Speech, Signal Process., 2003, vol. 4, pp. 129132. [14] Y. Takahashi, A. Fujiwara, K. Yamazaki, H. Namatsu, K. Kurihara, and K. Murase, A multi-gate single-electron transistor and its application to an exclusive-OR gate, in Tech. Dig. 1998 Int. Electron Devices Meet., pp. 127130. [15] C. Lageweg, S. Cotofana, and S. Vassiliadis, A linear threshold gate implementation in single-electron technology, in Proc. IEEE Comput. Soc. VLSI Workshop, 2001, pp. 9398. [16] J. R. Tucker, Complementary digital logic based on the coulomb blockade, J. Appl. Phys., vol. 72, no. 9, pp. 43994413, 1992. [17] M. W. Keller, J. M. Martinis, N. M. Zimmerman, and A. H. Steinbach, Accuracy of electron counting using a 7-junction electron pump, Appl. Phys. Lett., vol. 69, pp. 18041806, 1996. [18] C. Wasshuber, H. Kosina, and S. Selberherr, SIMON-a simulator for single-electron tunnel devices and circuits, IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 16, no. 9, pp. 937944, 1997. Hisato Fujisaka (M00) received the Dr.Eng. degree from Keio University, Japan, in 1994. From 1994 to 1997, he was with the Department of Optical Communications, Osaki Electric Co. Ltd., Japan. Since 1997, he has been an Associate Professor in the Faculty of Information Science, Hiroshima City University, Japan. His research interests include analysis and synthesis of nonlinear signal processing and communication circuits. Dr. Fujisaka is a member of IEICE.

Chang-Jun Ahn (M01) received the Ph.D. degree from Keio University, Japan, in 2003. From 2001 to 2003, he was a Research Associate in the Department of Information and Computer Science, Keio University. From 2003 to 2006, he was with the National Institute of Information and Communications Technology. From 2006 to 2010, he was with the Faculty of Information Science, Hiroshima City University. In 2010, he joined the Faculty of Engineering, Chiba University, Japan. Currently, he is an Associate Professor in the Department of Electrical and Electronic Engineering. His current research interests include OFDM, digital communication, channel coding, and signal processing for telecommunications. Dr. Ahn has received many award including the ICF research grant award for Young Engineers. He is a member of IET, IEICE, and the Korean Institute of Communication Science (KICS).

Takeshi Kamio received the B.E., M.E., and Ph.D. degrees from Shizuoka University, Japan, in 1994, 1996, and 1999, respectively. From 1996 to 1999, he was a Research Fellow with the Japan Society for the Promotion of Science. In 1999, he joined the Faculty of Information Science, Hiroshima City University, Japan. Currently, he is a Lecturer in the Department of Systems Engineering. His research interests are intelligent signal processing including neural networks. Dr. Kamio is a member of IEICE.

Masahiro Sakamoto received the B.E., M.E., and Ph.D. degrees from Saitama University, Japan, in 1994, 1996, and 2003, respectively. From 1996 to 2004, he was with the Faculty of Information Science, Hiroshima City University. In 2004, he joined the Faculty of Engineering, Saitama Institute of Technology, Japan. Currently, he is an Associate Professor in the Department of Information Systems. His research interests include both hardware and software for high performance computation and computer interface. Dr. Sakamoto is a member of IEICE.

Kazuhisa Haeiwa (M11) graduated from the Department of Electrical Engineering, Tokushima University, Japan, in 1970 and received the Dr.Eng. degree from the University of Tokyo, Japan, in 1988. In 1970, he joined Japan Broadcasting Corporation and engaged in the design and development of broadcasting transmitters. Since 2004, he has been a Professor in the Faculty of Information Science, Hiroshima City University. Dr. Haeiwa has received many awards including the Development Award from the Image and Information Media Society. He is an IEICE Fellow Member.