A NOVEL FREQUENCY COMPENSATION TECHNIQUE FOR TWO-STAGE CMOS OPERATIONAL AMPLIFXERS

M Taherzadeh-Sani, Lo@, and 0. R. Shoaei

IC Design Lab., ECE Department, Faculty of Engineering, University of Tehran, Tehran, Iran Taherzadeh@ece.ut.ac.ir,http://www.eng.ut.ac.irilCLab/

ABSTRACT
In this paper, a novel compensation technique for twostage CMOS operational amplifiers (op-amps) is presented. This method employs a smaller total capacitance compared to that of the traditionalcompensation approaches with similar frequency response. As this capacitor is not placed in the path of the signal, the large signal settling behavior and so the total settling time of the op-amp is improved. HSPICE simulations reveal that the proposed approach, compared to cascode-compensated counterpart, would reduce the total compensation capacitor and the settling time as high as 36% and lo%, respectively.

combining the proposed approach with traditional cascode compensation technique [l] can reduce the total capacitor employed for the compensation of the twostage op-amp. In this paper, first, the systematic and mathematical fundamentals of the proposed approach are addressed. Then the general schematic as well as the practical implementation of the new coinpensation technique in a two-stage op-amp is presented. Furthermore design considerations and practical limitations are discussed. HSPICE simulation results for a two-stage op-amp employing the proposed compensation technique and a class AB output stage confirming the effkctiveness of the proposed approaches are followed.

2. PROPOSED APPROACH
1. INTRODUCTION
The increasing demand for mobile or battery-operated electronic equipment as well as the continuing trend of technology scaling has made the supply voltage of integrated circuits to scale down. Although the voltage scaling leads to less power consumption for the digital ICs, it makes the design of analog and mixed-signal circuits more challenging. One of the most important challenges in the design of low-voltage CMOS analog circuits is the realization of operational amplifiers (opamps). Op-amps have become of the most important building blocks in analog integrated circuits [l] such as high-speed A/D converters. One of the commonly-used CMOS operational amplifiers in low voltage applications is the two-stage op-amps, owing to its high gain and wide output swing. However in such structures, to guarantee the stability of the op-amp, some forms of compensation is required. There have been several methods for ffequency compensation of two-stage op-amps [1][2][3][4]. Although some of these methods improve the ffequency behavior of the op-amp with even a smaller capacitor [l] compared to the earlier compensation methods, they use the compensation capacitor through the signal path which limits the slewing behavior of the op-amp. To overcome this problem, this paper presents a new method to compensate the op-amp with a smaller capacitor not placed in the signal path. It is shown that The traditional compensation techniques such as Miller [2],cascode [l], improved Ahuja style 1 3 , and nested 11 Miller [4] utilize a capacitor to reduce the first pole of the op-amp as well as to enlarge the second one. This pole displacement leads to a bigger phase: margin which results in a higher stability for the op-amp when it is used in a feedback configuration. The approach presented here is based on the tachometer (velocity) feedback control systems [5].Fig. 1 shows the general schematic of a system employing a tachometer feedback. Considcring a two-pole system, A(s) in Fig. 1, it can be shown that by using the tachometer feedback, the wholi: system transfer function is obtained fiom
I 1

LI

Figure 1. Tachometer feedback control system

0-7803-8163-7/03/$17.00 IEEE 0 2003

ICECS-2003

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Figure 2. Proposed approach

4s) ) = l+B(s).A(s)
-

A,

(l)

where A($) and B(s) are as d&ned in Fig. 1 . Considfling p2 >>PI, which is usually the case in commonly used opamps, it can be shown that the first and the second poles of the whole system are approximated by
I

This voltage across A and B is amplified through M 2 . The input signal is also amplified through MI.Then these two signals i.e. feedback and input are subtracted at the drain of M2. As mentioned before, in order to have a tachometer feedback, the derivative of the output must be subtracted fiom the input. Hence, by using the proposed structure of Fig. 2 the tachometer feedback is provided. It can be shown that VB can be referred to the input of the total op-amp as
Vinput re+zrred

= --

c, -dV6ut gm2 gml

(4)

gmb

dt

P I

= -

1+P,&
~~

PI

and p2 = p2 + p l P z k A V

(2)

Using (2),plis obtained from

This pole splitting leads to more stability for the new system, similar to what resulted in Miller-compensation method as well as other traditional compensation techniques. Such an approach can be applied to any amplifier to improve its stability. Fig. 2 shows a possible implementation of the approach presented here, exploited in a two-stage op-amp. This figure shows a two-stage op-amp with a folded cascade as the first stage followed by a common source amplifier which is a practical structure in low-voltage high-gain applications [6]. Also shown are the bias circuit for nodes A and B. The Compensation network includes two capacitors, CT, connected between the outputs and nodes A and B. In the traditional op-amps, node A and B are connected to each other and then connect to a bias network which is usually a diode connected transistor. But in the new structure, nodes A and B are separately biased with two distinct diode connected transistors. However this bias network must provide the same bias voltage to both nodes of A ana B. As it is obvious, the bias network of nodes A and B can be modeled as a resistor with the value of l / g d connected to an ideal voltage source. So if the resistor is small, the compensation network provides the derivative of the outputs at nodes A and B. The magnitude of the voltage exerted to nodes A and B can be obtained fiom (3)

provided that pl>>l/kAv. In the Miller- or cascodecompensated op-amp, the first pole can be written as
1 gm1 A cc V where Cc is the Miller capacitance. So the proposed compensation technique shifts the first pole in a frequency similar what happens in traditional compensation techniques. However the value of the compensation capacitor can be chosen smaller because of multiplied factor of gm2/&,b. If the circuit uses both the proposed and the traditional technique, using (5) and (6), it can be shown that the first pole is obtained fiom
p1=--

(7)

Of course, such a feedback can be applied to nodes A and B instead of A and B in Fig. 2, and similar equations can be derived. Note that in such a circuit, the bias network of A and B must be separated as well.

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Figure 3. Proposed op-amp The main advantage of this approach is that Cc can be reduced using a small capacitor of CTleading to less chip area as well as better slewing behavior of the op-amp. Furthermore, note that C, is not placed in the path of the signal. For example, if the value of Cc required for the compensation of an op-amp with traditional methods is about 5pF, it can be easily replaced with C e 3 p F and Cr0.2pf with a ratio of g,,,')./g,,,b equal to 10. Consequently, using this technique a smaller total compensation capacitance can be employed while the first pole frequency and therefore the noise band-width are identical. The main drawback of the method presented here is revealed in (3). As mentioned in deriving (3), it was assumed that l/gmb and CT are small enough to have an exact derivative of the output at nodes A and B. However, as it is obvious in (7), reducing l/gmband CT would enlarge the first pole leading to the instability of the op-amp. The other drawback arises fTom the parasitic capacitances of node A and B which prevent the exact derivative of the output. To overcome these problems, the values of CT and l/&b have to be reduced. On the other hand this reduction leads to enlarged first pole. Therefore, in some cases we have to use a combination of both traditional and proposed approach to achieve a small first pole, as calculated in the previously-mentioned example and illustrated in Fig. 3. Fig. 3 shows an op-amp with a class AI3 output stage compensated with the combination of both proposed approach and cascode compensation technique. For a two-stage op-amp it should be noted that the slew rate is determined by not only the bias current of the input stage but also that of the output stage [7]. Therefore employing a class-A/AB amplifier as the second stage can lead to power saving when the load capacitor is large [7]. The classAB output stage utilized in the op-amp works as follows. Consider the output stage of Fig. 3 redrawn also in Fig. 4. The capacitor CLSis charged with the bias voltage of the PMOS current source minus the gate-to-source bias voltage of the nMOS amplifylng device in the sampling phase when the op-amp is idle (in the sampling phase of switched capacitor circuits). In the amplifylng phase the switch is disconnected and assuming close to no charge leakage for the capacitor, the PMOS current source is biased with a suitable voltage that is signal-dependent as well. When the signal goes down, C acts as a level shifter and the gate voltage of , the PMOS current source also goes down so that it will source enough current in order to quickly charge the output capacitance. In order to ensure that the voltage across the level-shifting capacitor remains unchanged, the capacitor value is choseri enough larger than the parasitic capacitance at the :gate node of the PMOS device of Fig. 4 equal to 5pF in our design.

vo

Figure 4. The proposed swit(:hed-capacitor class-&

output slage The class-AI3 output stage enhimces the slewing behavior of the output and eliminates thr: dependency of the output slew rate on the output-stage bias currant. So, only the first-stage bias current and CC determine the slewing behavior of the total op-amp as SR = Ial!Cc ti (8) So decreasing Cc directly affects the slevv-rate of the opamp. As the proposed approach results in reduced CC, the op-amp would have a better slewing behavior leading to a smaller settling time.

3. SIMULATION RESULTS
The op-amp presented in Fig. 3 is utilized in the charge redistribution sample and hold architecture depicted in Fig. 5. The simulation is performed with HSPICE using 0.25um n-well CMOS technollogy at 1.5V power supply. This sample and hold is aimed to be used in a 65Msamples/sec 12-bit pipelined analog-to-digital converter. HSPICE simulatitm of the op-amp using

258

BSIM3 models, confirms the effectiveness of the presented technique. Fig. 6 shows the fi-equency response of the proposed opamp of Fig. 3 driving a 8pF load. To compensate the opamp the capacitors are chosen as Cd=3pF and C ~ 0 . 2 p F . As it can be seen, a low-frequency gain more than 78dB and a phase margin of 67 with a feedback factor of 112 is achieved. Also the fkequency response of the op-amp when it is compensated only with the cascode compensation technique employing CySpF, is very similar to what shown in Fig. 6 and the same phase margin and unity-gain bandwidth are obtained. Fig. 7 presents the step response of the two above opamps. One uses the cascode compensation technique utilizing Cc5pF. The other uses combination of the cascode and proposed compensation techniques depicted in Fig. 3 utilizing C e 3 p F and C ~ 0 . 2 p F As mentioned . before, the test structure is a sample and hold where some of the switches are of bootstrapping type, and the feedback and sampling capacitors are chosen equal to 5pF. The improvement in the slew rate and so settling behavior is evident. The proposed op-amp would settle within 0.24% of the final value of 2VplD.d8 output signal in less than 7.211s which is about 10% better than the previously-mentioned cascode compensated counterpart. Table 1 shows the comparison results between the proposed op-amp and the cascode-compensated op-amp.
I

Table 1. Comparison Results

CascadeGain Phase Margin (p0.5) Total current consumption Total compensation capacitance Settling time
6mA

6mA 5PF 8ns

3.2pF 7.21~

,
I~

. ,Gx

. im

.
I
F8L-i

,
>ox ,b,,LITL,
119

Figure 6. Frequency response of the proposed op-amp

4. CONCLUSION
A novel technique to compensate two stage op-amps is presented. This method employs smaller total capacitance compared to the traditional compensation approaches with similar frequency-compensation characteristics such as the unity-gain bandwidth and phase margin. Although the frequency responses are the same, the step response of the proposed approach especially in the large signal settling interval, is better than that of the traditional techniques and the total settling time is reduced as well. HSPICE simulations show that using the proposed approach compared to the cascode-compensated counterpart resulted in a reduction of the total compensation capacitors and the settling time as high as 36% and lo%, respectively.

rm h, ,,,ME,

i6n

Figure 7 The step response of the (a) propose op-amp . and (b) cascode-compensatedop&np

5. ACKNOWLEDGMENT
This work was supported in part by a grant of Iran Telecommunication Research Center.

6. REFERENCES
[l] K. Ahuja, An improved fkquency compensation technique for CMOS operational amplifiers, in IEEE Journal o Solidf State Circuits, vol.SC-18, pp.629-33, Dec. 1983. f [2] B. Razavi, Design o analog CMOS integrated circuits, McGraw-Hill, 2000. [3] L. Yao, M. Steyaert, and W. Sansen, Fast-settling CMOS two-stage operational transconductance amplifiers and their systematic design, IEEE Symposium on Circuits and Systems, vol. 2, pp 839- 842, May 2002. [4] R. G. H. Eschauzier and J. H. Huijsing, Frequency
Compensation Techniques for Low-Power Operational Amplifiers,Boston, MA: Kluwer, 1995. [5] B. C. .Kuo, Automatic Control Systems, 8th Edition, Prentice

in

v-

Figure 5. The SHA configuration employed in this paper

(the switches represented in boxes are bootstrapping type).

Hall, 2002. [6] M. Abo, P. R. Gray, A 1.5-V IO-bit, 14.3MSh CMOS Pipeline Analog-to-Digital Converter, in IEEE Journal o f Solid-state Circuits, ~01.34, pp.599-606, May 1999. [7] S. Rabii, B. Wooley, A 1.8-V digital-audio sigma-delta modulator in 0.8-um CMOS, in IEEE Journal of Solid-state Circuits, ~01.32, pp.783-796, Jun.1997.

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