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The GH VHDL Library

An

www.OpenCores.org

Project

ghuber@opencores.org

The GH VHDL Library

Revision History

Revision

Date

Author

Description

1.0

3

Sept 2005

G

Huber

Initial Revision

1.1

10

Sept 2005

G

Huber

Add parts, fix some typo’s

2.0

17

Sept 2005

H

LeFevre

1. Add LFSR’s

   

2. Add gh_ prefix to the name of some parts.

(See chapter 4 for explanation on this change) 3 Mod parts to use gh_ parts (where required)

2.1

18

Sept 2005

G

Huber

Add decoder/mux, clock divider, and NCO

2.2

24

Sept 2005

S

A Dodd

Add pulse generator

2.3

1

Oct 2005

G

Huber

Add sweep generator

2.4

4

Oct 2005

H

LeFevre

Add Random Number Generator/CASR

3.0

8

Oct 2005

G

Huber

Reorganize library, add a couple of shift registers

3.1

15

Oct 2005

S

A Dodd

Add parity generator, FIFO’s, integer counters

3.2

23

Oct 2005

G

Huber

Add programmable LFSR’s

3.3

29

Oct 2005

G

Huber

Add Configuration Registers

3.4

13

Nov 2005

S

A Dodd,

Add some memory parts

 

G

Huber

3.5

14

Jan 2006

G

Huber

Add delay lines

3.6

21

Jan 2006

S

A Dodd

Add Control Registers

 

G

Huber

Add a fixed delay line for a bus

3.7

28

Jan 2006

H

LeFevre

Add a baud rate generator

3.8

4

Feb 2006

S

A Dodd

Add FIFO with sync clear

H

LeFevre

Add an In Place Multiplier

3.9

11

Feb 2006

H

LeFevre

Add two more In Place Multipliers (one has both inputs unsigned and the other both inputs are signed)

 

G

Huber

Add another shift register (shifts left)

3.10

18

Feb 2006

G

Huber

Add another shift register (also shifts left) Finished adding the gh_ prefix to all parts

3.11

25

Mar 2006

H

LeFevre

Add one more In Place Multiplier

 

S

A Dodd

Mod gh_sincos to use Cordic + 45

3.12

13

May 2006

S

A Dodd

Add FIR Filter

3.13

26

May 1006

G

Huber

Add debounce, stretch low

3.14

16

Sept 2006

G

Huber

Add a counter, 18 bit multipliers

3.15

23

Sept 2006

SA Dodd

Add complex math parts

3.16

23

Dec 2006

H

LeFevre

Replace async FIFO (to use gray code)

3.17

27

Dec 2006

G

Huber

Add Gray code converters

 

HL/SD

Update FIFO’s

3.18

13

Jan 2007

H

LeFevre

add async FIFO’s with ¼. ½, and ¾ full flags

3.19

27

Jan 2007

SA Dodd

add digital attenuator

3.20

3

Feb 2007

H

LeFevre

add parallel FIR Filter

3.21

10

Feb 2007

H

LeFevre

add FIR Filters of odd order, negative symmetry

The GH VHDL Library

3.22

9

June 2007

G

Huber

add programmable delay bus, FASM dual port Ram with reset, 3 multipliers with generics

SA Dodd

3.23

30

June 2007

H

LeFevre

add 2 in-place multipliers, with all data bits out

 

G

Huber

add MAC with full generics and an unsigned array divider

3.24

15

July 2007

S

A Dodd

add a FIR filter and Pulse time/width module

3.25

12

Aug 2007

S

A Dodd

mod/add filter

3.26

16

Aug 2007

S

A Dodd

add (two clock multiply) complex multipliers

3.27

14

Oct 2007

H

LeFevre

add some filters w/o multipliers

3.28

21

Oct 2007

S

A Dodd

Add rev A of rectangular to polar (CORDIC application) – increases pipelining

 

G

Huber

add 4 byte memory

3.29

22

Nov 2007

H

LeFevre

add VMEbus Slave Interface Module parts

3.30

25

Nov 2007

H

LeFevre

add FIR filter, rev A for NCO

3.31

8

Dec 2007

G

Huber

add VME read Modules

3.32

30

Dec 2007

H

LeFevre

add 3 multiplier complex multipliers

3.33

3 May 2008

H

LeFevre

Add random number scalar (serial multiplier)

3.33a

4 May 2008

 

Add random number scalar (parallel multiplier)

3.34

24

May 2008

H

LeFevre

Add two asynchronous fifo’s (with UART style flags)

3.35

27

May 2008

G

Huber

Add programmable delay line using generics

3.36

1

June 2008

S

A Dodd

3 complex multipliers, with an extra register delay for higher operating frequency Data Mux(2:1) /DeMux (1:2) set

3.37

4

July 2008

G

Huber

Add some NCO type accumulators

3.38

1

Sept 2008

H

LeFevre

Add versions of a couple frequency syntheses parts

3.39

20

Sept 2008

H

LeFevre

Add programmable Stretch parts, add init to some of the memory parts

3.40

27

Sept 2008

H

LeFevre

Add 4 byte GPIO

3.41

04

Oct 2008

H

LeFevre

Add Burst Generator

3.42

11

Oct 2008

H

LeFevre

Add CORDIC’s with 28 bit atan functions

3.43

26

Oct 2008

H

LeFevre

Add Sin Cos ROM’s

The GH VHDL Library

Table of Contents

1 Introduction

1

1.1 Purpose

1

1.2 What the Library is Not

1

1.3 GH VHDL License

1

2 Basic Registers and Gates

3

2.1 D Flip Flop

3

2.2 JK Flip Flop

3

2.3 Basic Register and Latch

4

2.4 XOR Bus

4

2.5 Comparators

5

2.6 Decoders

6

2.7 Multiplexers

6

2.8 Shift Registers

7

2.9 Four Byte Configuration Registers

8

3 Counters

9

3.1 Binary Counters

9

3.2 Modulo Counter

10

3.3 Integer Counters

10

4 Custom MSI Parts

11

4.1 Pulse Stretcher

11

4.2 Edge Detector

12

4.3 Clock Divider

12

4.4 Pulse Generator

13

4.5 Parity Generator

13

4.6 Delay Lines

14

4.7 Baud Rate Generator

15

4.8 Control Registers

16

4.9 A Switch de-bouncer

17

4.10 An Edge Detector for changing Clock Domains

17

4.11 Gray code converters

18

4.12 Pulse Width/Time Measurement

18

4.13 Lower Rate Clock Mirror

19

4.14 Data DeMux 1 to 2

19

4.15 Data Mux 2 to 1

20

4.16 Four Byte GPIO

20

4.17 Burst Generator

21

5 Math Functions

22

5.1 Accumulator

22

5.2 Multipliers

22

5.3 Multipliers using Generics

23

5.4 Multiplier Accumulator

23

5.5 Random Number Generation

24

5.5.1 The Linear Feedback Shift Register (LFSR)

24

5.5.2 CASR and Random Number Generator

25

The GH VHDL Library

5.5.3 Programmable LFSR’s

26

5.5.4 Random Number Scalars

27

5.6 In Place Multipliers

28

5.7 Unsigned Array Divider

29

5.8 Complex Math

30

5.9 Digital Attenuator

32

6 Memory

33

6.1 Synchronous RAM

33

6.2 FIFO’s

34

6.2.1 Synchronous FIFO

34

6.2.2 Asynchronous FIFO

35

6.2.3 Asynchronous FIFO’s with UART Style Flags

36

6.3

Four Byte Dual Port RAM

37

7 Frequency Synthesis

38

7.1

The DDS (also known as the NCO, or DCO)

38

7.1.1

NCO Style Accumulators

39

7.2

Sweep Generator

40

7.2.1

Simulation of the Sweep Generator

43

7.3

CORDIC Rotation Algorithm

44

7.3.1 Theory of the CORDIC

45

7.3.2 Applications for the CORDIC

47

7.4

Sin Cos ROM Lookup Tables

48

8 Filters

49

8.1 CIC Filter

49

8.2 Time–Varying Fractional Delay Filters

52

8.2.1 The Lagrange Interpolator

52

8.2.2 Time–Varying Control

53

8.2.3 TVFD Application Notes

53

8.3 A single MAC FIR Filter

54

8.4 Symmetrical, parallel FIR Filters

55

8.4.1

FIR Filter Architecture

56

8.5

FIR Filters Without Multipliers

57

9 VMEbus [VXIbus] Interface Modules

58

9.1 VME Slave Modules

59

9.2 VME Chip Select Modules

61

9.3 VME Read Modules

61

10 Library Notes

62

The GH VHDL Library

1

Introduction

The GH VHDL Standard Parts Library is a collection of basic VHDL parts that may be included in larger designs. There is nothing wrong with modifying library parts so that they will meet the system requirements.

1.1 Purpose

Educational – this is a set of design examples that demonstrate some of the more important language constructs.

To have a set of building blocks to aid in the building of a VHDL design – Large designs can be broken up into smaller blocks. When there are common functions in these blocks, time can be saved when these common functions can be designed once and reused many times.

Note: The library is setup as a collection of design files – this makes it easy to examine the design of each part. Some may want to put them together as a “proper” VHDL library.

1.2 What the Library is Not

A VHDL language reference.

Complete – Contributions are encouraged, which may be added the library (or ignored) at our discretion.

Perfect. Look for ways to improve it – even if we do not like your “improvements,” if they make your life easier, use them anyway.

1.3 GH VHDL License

Copyright (c) 2005, 2006, 2007, 2008 by George Huber

Permission is hereby granted, free of charge, to any person obtaining a copy of this OpenCores Project and associated documentation (the "lesser IP"), to use it in the in

larger designs (the “greater IP”) without restriction, subject to the following conditions:

1. The copyright notice is retained in the source files, and if they are modified, the Revision block must updated to identify the changes.

2. The lesser IP itself may not be sold, but this restriction is limited to the lesser IP itself, not to any greater IP that it may be used in. (Inclusion on a distribution CD of, for example, OpenSource Projects is not considered a “sale”)

3. Any greater IP which uses the lesser IP, when distributed as source code or synthesized net list, must include in the documentation an acknowledgement of using the GH VHDL Library (This acknowledgement is not required for the

The GH VHDL Library

distribution of a fuse map or other hardware implementation in CPLD, FPGA, ASIC or other form of custom IC).

4. THE LESSER IP IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED.

5. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY ARISING FROM, OR IN CONNECTION WITH THE USE OF THE LESSER IP.

The GH VHDL Library

2 Basic Registers and Gates

Here are the basic parts that make up many larger systems. For some of these, it may be argued that it is more work to instantiate them than it is to rewrite the function. However, a number of design entry tools allow the use of Block diagrams. When using block diagrams, it is useful to have these parts available.

2.1 D Flip Flop

The D Flip Flop is almost too simple to be in the library, but it is here anyway.

I/O

Function

CLK

I

Clock, rising edge is used

rst

I

Asynchronous Reset, active high

D

I

Input Data

Q

O

Output Data

File name: gh_DFF.vhd

 

2.2

JK Flip Flop

I/O

Function

CLK

I

Clock, rising edge is used

rst

I

Asynchronous Reset, active high

J

I

J Input

K

I

K Input

Q

O

Output Data

File name: gh_JKFF.vhd

Truth Table for the JKFF

CLK

rst

J

K

Q

X

1

X

X

0

0

1

0

1

0

0

1

0

0

1

1

toggle

0

0

0

no change

The GH VHDL Library

2.3 Basic Register and Latch

These parts have the generic “size” which sets the data width.

I/O

Function

CLK

I

Clock, rising edge is used

rst

I

Asynchronous Reset, active high

LE

I

Latch enable (1 = transparent D to Q 0 = hold Q)

CE

I

Clock enable

D(size-1 downto 0)

I

Input Data

Q(size-1 downto 0)

O

Output Data

Parts

C

r

L

C

D

Q

comments

L

s

E

E

K

t

gh_latch.vhd

   

x

 

x

x

 

gh_register.vhd

x

x

   

x

x

 

gh_register_ce.vhd

x

x

 

x

x

x

 

2.4 XOR Bus

This is just a XOR gate with a programmable length (using the generic “size”). Its purpose is to make it easier to combine two LFSR’s (of different length), or a LFSR with a CASR (Cellular Automata Shift Register), to improve the characteristics of the generated random numbers.

I/O

Function

A(size downto 1)

I

Size number of bits from LFSR A

B(size downto 1)

I

Size number of bits from LFSR B

Q(size downto 1)

O

output

File name: gh_xor_bus.vhd

The GH VHDL Library

2.5 Comparators

While Comparators are not strictly gates, they are included here because they are simple enough that some people will find it easier to rewrite the code, than it is to instantiate a component.

I/O

Function

 

A (size-1 downto 0)

I

A input vector

 

B (size-1 downto 0)

I

B input vector

 

min (size-1 downto 0)

I

 

max (size-1 downto 0)

I

 

D

(size-1 downto 0)

I

 
 

AGB

O

ABS of A is greater than the ABS of B when high

AEB

O

ABS of A is equal to the ABS of B when high

ALB

O

ABS of A is less than the ABS of B when high

AS

O

A sign bit

 

BS

O

B sign bit

 

ABS_A(size-1 downto 0)

O

ABS of A

 

ABS_B(size-1 downto 0)

O

ABS of B

 

Y

O

Y

= ‘1’ when D is between min and max

 

Parts

A

B

 

m

m

D

A

A

A

A

B

A

A

Y

Comments

i

a

G

E

L

S

S

B

B

n

x

B

B

B

S

S

 

_

_

A

B

gh_compare.vhd

x

x

     

x

x

x

         

Unsigned

data

gh_compare_ABS.vhd

x

x

     

x

x

x

x

x

x

x

 

Signed

data

gh_compare_BMM.vhd

     

x

x

x

             

x

Unsigned

 

data

gh_compare_ABS_reg.vhd (clk and rst inputs added)

x

x

     

x

x

x

x

x

x

x

 

Signed

data- adds

 

pipeline

registers

The GH VHDL Library

2.6 Decoders

The design of the decoders is based on the 75LS138, except that the outputs, when active, are high.

I/O

Function

 

A

 

I

Address/select input

G1

 

I

Output enable, active high

G2n

 

I

Output enable, active low

G2n

 

I

Output enable, active low

Y(8 or 16 downto 0)

   

O

Output bus, only 1 output is active (high) at a time- when all enables are active

Parts

 

A

G

G

G

Y

Comments

1

2

3

n

n

gh_decoder_2to4.vhd

   

x

x

x

x

4

bits

 

Output bit, which corresponds with value of A, is high

gh_decoder_3to8.vhd

   

x

x

x

x

8

bits

 

Output bit, which corresponds with value of A, is high

gh_decoder_4to16.vhd

   

x

x

x

x

16 bits

 

Output bit, which corresponds with value of A, is high

2.7

Multiplexers

I/O

Function

 

sel

 

I

Selects which input becomes the output

A - P

 

I

Data inputs

 
 

A

input sel = 0, B input sel =1,

C

input sel = 2, D input sel =3 etc

Y

 

O

Output

 

Parts

sel

 

Data

 

Y

Comments

gh_mux_2to1.vhd

1

bit

 

A, B

 

x

 

gh_mux_2to1_bus.vhd

1

bit

 

A, B

 

x

Uses generic size to set width of data bus

gh_mux_4to1.vhd

2

bits

 

A – D

 

x

 

gh_mux_4to1_bus.vhd

2

bits

 

A – D

 

x

Uses generic size to set width of

gh_mux_8to1_bus.vhd

3

bits

 

A – H

 

x

data bus

gh_mux_16to1_bus.vhd

4

bits

 

A - P

 

x

The GH VHDL Library

2.8 Shift Registers

These are just a simple shift registers – the input D is loaded into Q(0) [when shifting right] with each clock edge. The data Q(n) is shifted to Q(n+1) at the same time [or Q(n+1) is shifted to Q(n) when shifting left]. The Shift Register’s have the generic “size” which sets the number of bits to be shifted.

It should be noted the “shift left” and “shift right” refers to shifting the data as if it is

lined up: q0 q1 q2 q3 q4…qn. Default for this library is shift right (_sl in the name

means it shifts left, _slr means it can shift either left or righ).

I/O

Function

 

CLK

I

Clock, rising edge is used

rst

I

Asynchronous Reset, active high

srst

I

Synchronous reset, active high

LOAD

I

Parallel Load command

SE

I

Shift enable

MODE

I

Mode Bits : 00 hold (do nothing)

01

shit right (Q i = Q i-1 )

10

shift left (Q i = Q i+1 )

11

Parallel Load

DSL

I

Serial data in for shift left

DSR

I

Serial data in for shift right

D

or D(size-1 downto 0)

I

Data bit(s) to be shifted and/or loaded

Q(size-1 downto 0)

O

Shifted bits out

Parts

C

r

s

L

S

M

D

D

D

Q

Comments

L

s

r

O

E

O

S

S

K

t

s

A

D

L

R

t

D

E

gh_shift_reg.vhd

x

x

           

x

x

 

gh_shift_reg_rs.vhd

x

x

x

         

x

x

Reset can be changed to Preset w/generic

gh_shift_reg_PL.vhd

x

x

 

x

x

     

x

x

Parallel Load, shift right

gh_shift_reg_PL_sl.vhd

x

x

 

x

x

     

x

x

Parallel Load, shift left

gh_shift_reg_PL_SLR.vhd

x

x

     

x

x

x

x

x

Parallel Load, shift left or right

gh_shift_reg_se_sl.vhd

x

x

x

 

x

     

x

x

 

The GH VHDL Library

2.9 Four Byte Configuration Registers

Here is a collection of registers intended for use as configuration/control - set up so that they may be initialized by byte, word, or long word access on a 32 bit data buss.

With FPGA gate counts of over 3 million, how many configuration bits are required?

I/O

Function

 

clk

I

 

Clock, rising edge is used

rst

I

Asynchronous Reset, active high

CSn

I

 

Chip Select, active low

WR

I

Write strobe, active high

BE(3 downto 0)

I

Byte enable bits

A

I

Address bits (Long Word addressing, BE is used to identify which byte)

D(31 downto 0)

I

Data buss in

RD(31 downto 0)

O

Read Configuration Data

Q

O

 

Configuration Bits

Parts

C

r

C

W

B

A

D

R

Q

Comments

L

s

S

R

E

D

K

t

n

gh_4byte_reg_32.vhd

x

x

 

x

x

 

x

 

x

Used on larger parts

gh_4byte_reg_64.vhd

x

x

x

x

x

x

x

x

x

 

gh_4byte_reg_128.vhd

x

x

x

x

x

x

x

x

x

 

gh_4byte_reg_256.vhd

x

x

x

x

x

x

x

x

x

Used on larger parts

gh_4byte_reg_512.vhd

x

x

x

x

x

x

x

x

x

 

gh_4byte_reg_768.vhd

x

x

x

x

x

x

x

x

x

 

gh_4byte_reg_1024.vhd

x

x

x

x

x

x

x

x

x

 

gh_4byte_reg_1536.vhd

x

x

x

x

x

x

x

x

x

 

gh_4byte_reg_2048.vhd

x

x

x

x

x

x

x

x

x

 

The GH VHDL Library

3

Counters

3.1 Binary Counters

All of these counters use standard logic vectors and use the generic “size” to set the number of bits used in the counter.

I/O

Function

 

CLK

 

I

Clock, rising edge is used

 

rst

 

I

Asynchronous Reset, active high

srst

 

I

Synchronous Reset, active high

CE

 

I

Count enable, active high

 

LOAD

 

I

Parallel load control

 

UP_D

 

I

Up/down control

 

D(size-1 downto 0)

 

I

Parallel load Data

 

TC

 

O

Terminal Count

 

one

 

O

Active when Count = 1

 

Q(size-1 downto 0)

 

O

Count value out

 

Parts

C

r

s

C

L

U

D

T

o

Q

comments

L

s

r

E

O

P

C

n

K

t

s

A

e

_

t

D

D

gh_counter.vhd

x

x

 

x

x

x

x

x

 

x

Universal Up/down counter

gh_counter_up_sr_ce.vhd

x

x

x

x

         

x

Up counter

gh_counter_up_ce.vhd

x

x

 

x

         

x

Up counter

gh_counter_up_ce_tc.vhd

x

x

 

x

     

x

 

x

Up counter

gh_counter_up_ce_ld.vhd

x

x

 

x

x

 

x

   

x

Up counter

gh_counter_up_ce_ld_tc.vhd

x

x

 

x

x

 

x

x

 

x

Up counter

gh_counter_down_ce_ld.vhd

x

x

 

x

x

 

x

   

x

Down counter

gh_counter_down_ce_ld_tc.vhd

x

x

 

x

x

 

x

x

 

x

Down counter

gh_counter_down_one.vhd

x

x

 

x

x

 

x

x

x

x

Useful as an event counter

gh_counter_fr.vhd

x

x

               

A free running binary counter

Why have so many counters in the library, when the first one is a super set of (most) the rest? After all, the synthesis tools will remove the excess logic. Logic verification is the

If a code coverage (and/or toggle coverage) tool is used to verify the design, some of the excess logic will show up as untested.

answer.

The GH VHDL Library

3.2 Modulo Counter

The Modulo counter is a specialized counter. It is incremented by the input N, and will roll over at the generic modulo. It will increment by the specified value even as it rolls over. The terminal count will go active the clock period before the roll over, for all values of N.

I/O

Function

 

CLK

 

I

Clock, rising edge is used

Rst

 

I

Asynchronous Reset, active high

CE

 

I

Count enable, active high

N(size-1 downto 0)

 

I

Increments by this value

TC

 

O

Terminal Count

Q(size-1 downto 0)

 

O

Count value out

Parts

C

r

C

N

T

Q

comments

L

s

E

C

K

t

gh_counter_modulo.vhd

x

x

x

x

x

x

Note: size must be large enough to count up to modulo

3.3 Integer Counters

The Integer Counters us integers, rather than standard logic vectors for holding the count values. They have one generic, max_count. The chief advantage this counter have is that they can be set to count to any value, without having a vector size to set.

I/O

Function

 

clk

 

I

Clock, rising edge is used

rst

 

I

Asynchronous Reset, active high

LOAD

 

I

Parallel load control

CE

 

I

Count enable, active high

D

 

I

Parallel load Data

Q

 

O

 

Count value out

Parts

C

r

C

L

D

Q

comments

L

s

E

O

K

t

A

D

gh_counter_integer_up.vhd

x

x

x

x

x

x

Counts up to max _count

gh_counter_integer_down.vhd

x

x

x

x

x

x

Counts down to zero, rolls over to max_count

The GH VHDL Library

4 Custom MSI Parts

This is a collection of parts that have functions that are not normally found in Standard MSI parts, but are not particularly complex in design.

4.1 Pulse Stretcher

The fixed Pulse Stretchers have the generic “stretch_count” which sets the number of clock periods that the pulse will be stretched. The programmable Pulse Stretches use the generic “size” the set the number of bits used to control the stretch count.

I/O

Function

CLK

I

Clock, rising edge is used

rst

I

Asynchronous Reset, active high

D

(Dn)

I

Input pulse to be stretched

stretch(size -1 downto 0)

I

Number of clocks to stretch pulse by

Q

(Qn)

O

Stretched pulse out

For the fixed Pulse Stretchers, an integer Variable is used to control the pulse stretching. This means only one generic is needed to be control the stretch time. If a STD_LOGIC_VECTOR had been used, the number of bits in the vector would also need

to be adjustable.

Parts

C

r

D(n)

stretch

Q

Comments

L

s

K

t

gh_stretch.vhd

x

x

x

 

x

stretches a high pulse

gh_stretch_low.vhd

x

x

x

 

x

stretches a low pulse

gh_stretch_programmable.vhd

x

x

x

x

x

stretches a high pulse

gh_stretch_programmable_low.vhd

x

x

x

x

x

stretches a low pulse

The GH VHDL Library

4.2 Edge Detector

This part will detect edges on the data input. When the input is asynchronous, the “s” outputs should be used to avoid missing edges. With synchronous inputs, the “s“ outputs will add a clock delay the non “s” outputs, without a gain in reliability.

I/O

Function

clk

I

Clock, rising edge is used

rst

I

Asynchronous Reset, active high

D

I

Input data bit

re

O

Rising edge detected (needs a synchronous input)

fe

O

Falling edge detected (needs a synchronous input)

sre

O

Rising edge detected (Data sampled before detection)

sfe

O

Falling edge detected (Data sampled before detection)

File name : gh_edge_det.vhd

4.3 Clock Divider

This uses a generic to set the dived ratio, the number of high speed clocks per low speed clock. The output is one clock period wide, designed to drive a clock enable pin on the parts running at the lower clock rate.

I/O

Function

CLK

I

Higher rate Clock

rst

I

Asynchronous Reset, active high

Q

O

Lower rate “clock enable” output

File name : gh_clk_ce_div.vhd

This part was designed specifically to be used by the TVFD_filter, the CIC_filter and any other part that requires two related clocks, where the lower rate “clock” is a clock enable pulse with the correct period.

For the TVFD_filter, the Q output drives the START input. For the CIC filtes, the Q output drives the ND input.

The GH VHDL Library

4.4 Pulse Generator

Does this belong here? Well, where else?? The Pulse Generator it is a simple application of two counters. If the Pulse Width is set to be equal to or larger than the Period, the output pulse will be a constant high.

I/O

Function

clk

I

Clock, rising edge is used

rst

I

Asynchronous Reset, active high

Period (size_Period-1 DOWNTO 0)

I

The number of clocks between pulses

Pulse_Width (size_Period-1 DOWNTO 0)

I

The Pulse width, in clock periods

ENABLE

I

Enable, active high

Pulse

O

The Output Pulse

I Enable, active high Pulse O The Output Pulse Here is a simulation of the Pulse

Here is a simulation of the Pulse generator with the period set to 9 and the pulse width set to 3. File name : gh_pulse_generator.vhd

4.5 Parity Generator

This is a serial parity generator. It needs to be before the start of a data word. The SD (sample data command) is included so that it is easy to use a clock that is greater that the data rate.

I/O

Function

clk

I

Clock, rising edge is used

rst

I

Asynchronous Reset, active high

srst

I

Synchronous Reset, active high

SD

I

Sample Data control

D

I

Serial data in

Q

O

Parity Bit

File name : gh_parity_gen_Serial.vhd

The GH VHDL Library

4.6 Delay Lines

Here is a collection of registered delay lines. All of the delay lines use shift registers, so it is not just an edge that is delayed, it will delay the entire serial data string.

The fixed length delay line uses the generic “clock_delays” to set the number of register delays.

The programmable delay lines use a number of fixed delay lines, each with a multiplexer at the input to select the source of the input, also a multiplexer is used to select the source for the output. This avoids the need for a single large multiplexer to select the delay tap.

Note: For the programmable delay lines- when the delay changes, any data in the shift

registers may be at the “wrong delay.”

max delay, which ever is less) number of clocks to shift out the “bad” data.

If it is not cleared, it will take the DELAY (or ½

I/O

Function

 

clk

 

I

Clock, rising edge is used

rst

 

I

Asynchronous Reset, active high

srst

 

I

Synchronous Reset, active high

D

 

I

Data input

DELAY (7, 6, 5, 4, or 3 downto 0)

 

I

Sets the programmable delay

Q

 

O

Output data

Parts

C

r

S

D

D

Q

Comments

L

s

r

E

K

t

s

L

t

A

Y

gh_delay.vhd

x

x

x

x

 

x

Uses generic “clock_delays” to set number of clock delays

gh_delay_bus.vhd

x

x

x

x

 

x

Uses generic “clock_delays” to set number of clock delays and the generic “size” to set bus width

gh_delay_programmable_15.vhd

x

x

x

x

x

x

 

gh_delay_programmable_31.vhd

x

x

x

x

x

x

 

gh_delay_programmable_63.vhd

x

x

x

x

x

x

 

gh_delay_programmable_127.vhd

x

x

x

x

x

x

 

gh_delay_programmable_255.vhd

x

x

x

x

x

x

 

gh_delay_programmable_255_bus

x

x

x

x

x

x

 

.vhd

gh_delay_programmable_bus.vhd

x

x

 

x

x

x

Uses generics for data width and size of possible delay (address size of internal RAM)

The GH VHDL Library

4.7 Baud Rate Generator

This 16 bit baud rate generator is designed to be a building block in UART’s. It has separate clocks for loading the baud rate register and for the generating baud rate. Valid baud rate divide ratio’s are from 2-65535. Divide values of 1 or 0 will disable the generator. The counter will be reloaded with a write to either byte.

I/O

Function

clk

I

Clock, rising edge is used

BR_clk

I

Baud rate counter clock

rst

I

Asynchronous Reset, active high

WR

I

Write, active high

BE(1 downto 0)

I

Byte enable, active high bit 1 for bits 15 downto 8 bit 0 for bits 7 downto 0

D(15 downto 0)

I

data in

RD(15 downto 0)

O

The baud rate register

rCE

O

Baud rate clock (Typically 16x of UART’s baud rate- one BR_clk period wide)

rCLK

O

Baud rate clock (duty cycle about

50%)

File name : gh_baud_rate_gen.vhd

The GH VHDL Library

4.8 Control Registers

Embedded Systems often have Control Registers, where the software folks would like to be able to set or clear individual bits. If they can not do this, they may need to do a Read- Modify-Write, or use a shadow register so that only the desired bits are changed.

These Control Registers allow individual bits to be set, reset, or inverted. This is done by setting the MODE bits. The four operations are to write entire register, set any number of individual bits, clear any number of bits, or invert any number of bits.

One easy way of controlling the MODE bits is to tie them the to lower address bits.

I/O

Function<