I2C Protocol Design for Reusability

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Dept, VTU (Belgaum), College, Bangalore, India
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Abstract One I2C protocol design method for reusability was proposed. In this method, design was divided into 3 levels: protocol level, signal level and interface level. Protocol level can be reused without any modification. Signal level can be reused by setting the number of be transferred byte according to specific operation. Interface level can be reused by changing the number of operation mode and the duration of every mode. Interface level is more complicated for reusability because different device has different number of operation mode. For low power reason, not all functions of I2C were designed.

Keywords I2C protocol, reusability, protocol level, signal level, interface level.

Introduction
Philips Semiconductors developed the I2C bus over 20 years ago and has an extensive collection of specific use and general purpose devices. Originally, the I2C bus was designed to link a small number of devices on a single card, such as to manage the tuning of a car radio or TV. The maximum allowable capacitance was set at 400 pF to allow proper rise and fall times for optimum clock and data signal integrity with a top speed of 100 kbps. In 1992 the standard bus speed was increased to 400 kbps, to keep up with the ever-increasing performance requirements of new ICs. The 1998 I2C specification, increased top speed to 3.4 Mbits/sec. All I2C devices are designed to be able to communicate together on the same two-wire bus.
I. I2C FEATURES

Only two bus lines are required: a serial data line (SDA) and a serial clock line (SCL). Each device connected to the bus is software addressable by a unique address and simple master/slave relationships exist at all times; masters can operate as master-transmitters or as master-receivers. Its a true multi-master bus including collision detection and arbitration to prevent data corruption if two or more masters simultaneously initiate data transfer. Serial, 8-bit oriented, bi-directional data transfers can be made at up to 100 kbit/s in the Standard mode, up to 400 kbit/s in the Fast-mode, or up to 3.4 Mbit/s in the High-speed mode. On-chip filtering (50 ns) rejects spikes on the bus data line to preserve data integrity. The number of ICs that can be connected to the same bus segment is limited only by the maximum bus capacitive loading of 400 pF.
II. I2C COMMUNICATION PROCEDURE

One IC that wants to talk to another must: 1) Wait until it sees no activity on the I2C bus. SDA and SCL are both high. The bus is 'free'. 2) Put a message on the bus that says 'its mine' - have STARTED to use the bus. All other ICs then LISTEN to the bus data to see whether they might be the one who will be called up (addressed). 3) Provide on the CLOCK (SCL) wire a clock signal. It will be used by all the ICs as the reference time at which each bit of DATA on the data (SDA) wire will be correct (valid) and can be used. The

data on the data wire (SDA) must be valid at the time the clock wire (SCL) switches from 'low' to 'high' voltage. 4) Put out in serial form the unique binary 'address' (name) of the IC that it wants to communicate with. 5) Put a message (one bit) on the bus telling whether it wants to SEND or RECEIVE data from the other chip. (The read/write wire is gone!) 6) Ask the other IC to ACKNOWLEDGE (using one bit) that it recognized its address and is ready to communicate. 7) After the other IC acknowledges all is OK, data can be transferred. 8) The first IC sends or receives as many 8-bit words of data as it wants. After every 8-bit data word the sending IC expects the receiving IC to acknowledge the transfer is going OK. 9) When all the data is finished the first chip must free up the bus and it does that by a special message called 'STOP'. It is just one bit of information transferred by a special 'wiggling' of the SDA/SCL wires of the bus. The bus rules say that when data or addresses are being sent, the DATA wire is only allowed to be changed in voltage (so, '1', '0') when the voltage on the clock line is LOW. The 'start' and 'stop' special messages BREAK that rule, and that is how they are recognized as special.

Fig.1 Example of an I2C-bus configuration using two microcontrollers.

Any device with the ability to initiate messages is called a master. It might know exactly what other chips are connected, in which case it simply addresses the one it wants, or there might be optional chips and it then checks whats there by sending each address and seeing whether it gets any response (acknowledge).
III. GENERAL CHARACTERISTICS

Generation of clock signals on the I2C-bus is always the responsibility of master devices; each master generates its own clock signals when transferring data on the bus. Bus clock signals from a master can only be altered when they are stretched by a slow-slave device holding-down the clock line or by another master when arbitration occurs. Both SDA and SCL are bi-directional lines, connected to a positive supply voltage via a currentsource or pull-up resistor. When the bus is free, both lines are HIGH. The output stages of devices connected to the bus must have an open-drain or open-collector to perform the wired-AND function. Data on the I2C-bus can be transferred at rates of up to 100 kbit/s in the Standard-mode, up to 400 kbit/s in the Fast-mode, or up to 3.4 Mbit/s in the High-speed mode. The number of interfaces connected to the bus is solely dependent on the bus capacitance limit of 400 pF.

Fig.2 Connection of Standard- and Fast-mode devices to the I2C-bus.

IV. BIT TRANSFER

Due to the variety of different technology devices (CMOS, NMOS, bipolar) which can be connected to the I2C-bus, the levels of the logical 0 (LOW) and 1 (HIGH) are not fixed and depend on the associated level of VDD. One clock pulse is generated for each data bit transferred. A. Data Validity The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW.

Fig.3 Bit transfer on I2C bus.

Fig.4 START and STOP conditions

B. START and STOP conditions Within the procedure of the I2C-bus, unique situations arise which are defined as START (S) and STOP (P) conditions. A HIGH to LOW transition on the SDA line while SCL is HIGH is one such unique case. This situation indicates a START condition. A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition. START and STOP conditions are always generated by the master. The bus is considered to be busy after the START condition. The bus is considered to be free again a certain time after the STOP condition. The bus stays busy if a repeated START (Sr) is generated instead of a STOP condition. In this respect, the START (S) and repeated START (Sr) conditions are functionally identical. Detection of START and STOP conditions by devices connected to the bus is easy if they incorporate the necessary interfacing hardware. However, microcontrollers with no such interface have to sample the SDA line at least twice per clock period to sense the transition.

V. TRANSFERRING DATA

A. Byte Format Every byte put on the SDA line must be 8-bits long. The number of bytes that can be transmitted per transfer is unrestricted. Each byte has to be followed by an acknowledge bit. Data is transferred with the most significant bit (MSB) first. If a slave cant receive or transmit another complete byte of data until it has performed some other function, for example servicing an internal interrupt, it can hold the clock line SCL LOW to force the master into a wait state. Data transfer then continues when the slave is ready for another byte of data and releases clock line SCL. A message which starts with such an address can be terminated by generation of a STOP condition, even during the transmission of a byte. In this case, no acknowledge is generated. B. Acknowledge Data transfer with acknowledge is obligatory. The acknowledge-related clock pulse is generated by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDA line during the acknowledge clock pulse so that it remains stable LOW during the HIGH period of this clock pulse. Of course, set-up and hold times must also be taken into account. Usually, a receiver which has been addressed is obliged to generate an acknowledge after each byte has been received. When a slave doesnt acknowledge the slave address (for example, its unable to receive or transmit because its performing some real-time function), the data line must be left HIGH by the slave. The master can then generate either a STOP condition to abort the transfer, or a repeated START condition to start a new transfer. If a slave-receiver does acknowledge the slave address but, sometime later in the transfer cannot receive any more data bytes, the master must again abort the transfer. This is indicated by the slave generating the not-acknowledge on the first byte to follow. The slave leaves the data line HIGH and the master gener-

ates a STOP or a repeated START condition. If a master-receiver is involved in a transfer, it must signal the end of data to the slave- transmitter by not generating an acknowledge on the last byte that was clocked out of the slave. The slave-transmitter must release the data line to allow the master to generate a STOP or repeated START condition.
VI. FORMATS WITH 7-BIT ADDRESSES

Data transfers follow the format shown in Fig.1. After the START condition (S), a slave address is sent. This address is 7 bits long followed by an eighth bit which is a data direction bit (R/W) - a zero indicates a transmission (WRITE), a one indicates a request for data (READ). A data transfer is always terminated by a STOP condition (P) generated by the master. However, if a master still wishes to communicate on the bus, it can generate a repeated START condition (Sr) and address another slave without first generating a STOP condition. Various combinations of read/write formats are then possible within such a transfer. Possible data transfer formats are:
A. Master-transmitter transmits to slave-receiver. The transfer direction is not changed.

Fig. 5 A master-transmitter addressing a slave receiver with a 7-bit address. The transfer direction is not changed.th

B. Master reads slave immediately after first byte (see Fig.12). At the moment of the first acknowledge, the master-

transmitter becomes a master- receiver and the slave-receiver becomes a slave-transmitter. This first acknowledge is still generated by the slave. The STOP condition is generated by the master, which has previously sent a notacknowledge (A).

Fig. 6 A master reads a slave immediately after the first byte.

C. Combined format (see Fig.13). During a change of direction within a transfer, the START condition and the slave

address are both repeated, but with the R/W bit reversed. If a master receiver sends a repeated START condition, it has previously sent a not-acknowledge (A).

Fig. 7 Combined formats.

VII. LEVEL DIVISION For the reason of reusability, I2C protocol design was divided into 3 levels in this method, as described in figure 8, these 3 levels from lowest to highest are: protocol level (PRL), signal level (SIL) and interface level (INL).

Fig.8 Level division of I2C protocol design

A. Protocol level (PRL) Protocol level is the lowest level of all three levels. In this level, the design was performed according to the protocol control signals and timing. Writing and reading are two basic operations in this level. For reusability, a division method based byte is proposed and showed below.

Fig.9 Description of PRL operation

According to the number of byte read or written in one pair of start-stop period, PRL operation can be divided into two types: separate PRL operation and continue PRL operation. There is only one byte was transferred during one pair of start-stop period in separate operation mode. As contrast, there are at least two bytes were transferred during one pair start-stop period in continue operation mode. In real application, continue PRL operation is widely used. Continue PRL operation includes three types: continue writing, continue reading and writing flowed by reading. For some devices whose register address can be added automatically after one read operation, the continue mode is very efficient. In this method, the timing information is as follows: One separate PRL operation: 17*clock_cycle One continue PRL operation: (N bytes were transferred) [17+(N-1)*(2+16)]*clock_cycle Interval between two PRL operation: 5*clock_cycle Interval between writing and reading signal in writing flowed by reading mode: 2*clock_cycle Clock_cycle is the period of the system clock. B. Signal level Signal level is the middle level of all three levels. According to the type of PRL operation, control signals were generated to realize relevant PRL operation. For example, in this level, write or read signal was used as control signal to generated start and stop signal in PRL. If write or read signal changes to 1 from 0 and SDA is 1, that is has a rising edge, then in PRL start signal was generated. When write or read signal changes to 0 from 1 and SDA is 1, that is has a falling edge, then in protocol level stop signal was generated. In order to write and read one byte correctly, the valid duration of write or read signal in separate operation mode is 17*clock_cycle. And there should be 5*clock_cycle wait time between two separated operations. For continue operations the valid duration of read or write signal is [17+(N-1)*(2+16)]*clock_cycle. N is the number of bytes were transferred. If

writing m bytes flowed by reading n bytes, the during of write signal is [17+(n-1)*(2+16)]*clock_cycle and the duration of read signal is [16+(m-1)*(2+16)] *clock_cycle. The read signal should valid after 2*clock_cycle when write signal becomes invalid. The whole operation time is also [17+(n+m-1)*(2+16)]*clock_cycle. The mapping relationship between SIL and PRL was showed in figure 3. in figure 3, the PRL operations were not classified into separate operation or continue operation. One SIL write operation can mapping into three separate PRL write operations or one continue PRL operation. This is decided by the specific protocol.

Fig.3 Mapping relationship between SIL and PRL

C. Interface level Interface level is the highest level of all three levels. Design of this level was determined by special device. One device can be work in different mode according to system requirement. One device can be in work mode or low power mode. In this level, the main design task is state machine design. The most important issue is timing of every state. The design method can be showed by one application of light sensor in section A of IV. VIII. DATA TRANSFORMATION A. Written data generation In order to realize some functions such as recognize the device and registers inside of it, the operation is writing or reading and so on, the master should send written data to I2C and received by slave. In this method, written data generation was realized in protocol level. There is one state for generating written data and loading the written data into one shift register. B. Data shift One byte was transferred as one unit, so one shift register was needed to realize transformation between parallel data and serial data. For write operation, parallel data were transformed into sequence data. For read operation, sequence data were transformed into parallel data. C. Data readout There should be one signal to indicate the validation of read data. It can also be as the write enable signal for SD card to store the read data.
IX. APPLICATIONS A. Reading operation Signal level: one SIL read operation Protocol level: two continued PRL operations. The first continue PRL operation is continue writing and the second continue PRL operation is writing flowed by reading. Two bytes were written in the first continue PRL operation, so the duration is : [17+(2-1)*(2+16)]*clock_cycle. One byte was written and one byte was read in the second continue PRL operation, so the duration is: [17+(2-1)*(2+16)]*clock_cycle. The duration of one SIL operation is (17+2+16)+5+(17+2+16) =75 clock cycles.

B. Writing operation Signal level: one SIL operation

Protocol level: one continue PRL writing operation. This PRL operation includes three continued writing operations. The duration of one SIL operation is [17+(3-1)*(2+16)]*clock_cycle=53 clock_cycle. X. CONCLUSIONS Hence it is proved that by using I2C protocol design for reusability: 1) The carry over time is reduced by reducing the number of clock cycles for a particular operation, thereby increasing the speed of the half duplex communication. 2) The master can access the register of choice in a slave device. REFERENCES
[1] [2] The I2C-bus specification, version 2.1, januaray 2000. I2C Protocol Design for Reusability, Third International Symposium on Information Processing, Zheng-wei HU North China Electric Power University, Baoding, China