EUROSOI 2005

First Workshop of the Thematic Network on Silicon On Insulator Technology, Devices and Circuits

19th 21st January 2005 Granada (Spain)

EUROSOI 2005 is organized by the Departamento de Electrnica y Tecnologa de Computadores de la Universidad de Granada (SPAIN) and supported by: EUROSOI Thematic Network on Silicon On Insulator Technology, Devices and Circuits

Ingeniera Electrnica. Facultad de Ciencias

Universidad de Granada

European Union

IST, Information Society Technologies

Ministerio de Educacin y Ciencia

Junta de Andaluca 1

PROGRAM SCHEDULE AT-A-GLANCE

REGISTRATION Tuesday, 18th January Wednesday, 19th January Thursday, 20th January Friday, 21st January CONFERENCE SCHEDULE Wednesday, 19th January
8:30 11:15 11:30 13:15 14:30 16:15 16:45 17:30 19:30 Training Course Coffee Break Training Course Lunch Training Course Coffee Break Training Course EUROSOI WG Meetings Welcome reception

17:00-21:00 8:00-20:00 8:00-19:00 8:00-12:00

Thursday, 20th January

8:30 10:30 11:00 13:00 15:00 17:00 20:00 Session 1: MATERIALS AND DEVICES Coffee Break Session 2: DEVICES AND SIMULATION I Lunch Session 3: DEVICES AND SIMULATION II Session 4: POSTER SESSION Gala Dinner

Friday, 21st January

8:30 11:00 11:30 13:00 14:00 15:00 17:00 22:00 Session 5: CIRCUITS AND APPLICATIONS I Coffee Break Session 6: CIRCUITS AND APPLICATIONS II Ramp Session Lunch EUROSOI MANAGEMENT BOARD MEETING Social Program: Historical Granada Social Program: Flamenco Show

Saturday, 22nd January

9:00

Social Program: Alhambra Visit

THE TECHNICAL PROGRAM will consist in 36 oral presentations and 19 poster papers. Session Chairs are as follows: Session 1 Session2 Session 3 Session 4 Session 5 Session 6 MATERIAL AND DEVICES Chair:Prof. Stefan Bengtsson (Chalmers University, Sweden) DEVICES AND SIMULATION I Chair: Prof. Jouni Ahopelto (VTT, Finland) DEVICES AND SIMULATION II Chair: Prof. J. E. Carceller (University of Granada, Spain) POSTER SESSION CIRCUITS AND APPLICATIONS I Chair: Prof.Cor Claeys (IMEC, Belgium) CIRCUITS AND APPLICATIONS II Chair: Prof.Amara Amara (ISEP, France)

TECHNICAL PROGRAM SCHEDULE

20th January SESSION 1 MATERIALS AND DEVICES Chair: Prof. Stefan Bengtsson
Chalmers University, Sweden 8:30-8:45 1.1 EUROSOI Network Status F. Gmiz
Dept. de Electrnica, Universidad de Granada, Spain

8:45-9:00

1.2

The evolution of future SOI materials: An European SOI material supplier point of view. B. Ghyselen, C. Mazure
Soitec S.A., Parc Technologique des Fontaines, 38190 BERNIN, FRANCE

9:00-9:15

1.3

From 100mm to 200mm Germanium-OnInsulator (GeOI) structures realized by the TM Smart-Cut technology 1 1 1 C. Deguet , C. Morales , J. Dechamp , J. M. 1 1 1 Hartmann , A.M. Charvet , H. Moriceau , F. 1 1 1 1 Chieux , A. Tauzin , L. Clavelier , V. Loup , N. 1 2 3 Kernevez , G. Raskin , C. Richtarch , T. 3 3 3 Signamarcheix , F. Allibert , T. Akatsu , F. 3 3 Letertre , C. Mazure
1CEA-DRT-LETI-CEA/GRE 17, rue des Martyrs, 38 054 GRENOBLE CEDEX 9 FRANCE 2Umicore, Watertorenstraat 33 B-2250 OLEN BELGIUM 3Soitec S.A., Parc Technologique des Fontaines, 38190 BERNIN FRANCE

9:15-9:30

1.4

Novel Bonding Techniques using the Formation of NiSi and TiSi2 1 1 1 M. F. Bain , P. Baine , B.M. Armstrong , H. S. 1 2 2 2 Gamble , R.W. Kelsall , Z. Ikonic , P. Harrison , 3 3 3 S.A. Lynch , P. Townsend , D.J. Paul , D.J. 4 4 4 5 Norris , S.L. Liew , A.G. Cullis , X. Li , and J. 5 Zhang .
1. School of Electrical & Electronic Engineering. The Queens University Belfast, UK 2. Institute of Microwaves and Photonics, The University of Leeds, UK 3. Cavendish Laboratory, The University of Cambridge, UK 4. Dept. of Electronic & Electrical Eng., The University of Sheffield, UK 5. Dept. of Physics. Imperial College London, UK

9:30-9:45

1.5

Atomistic Simulation of Hydrogen implantation for SOI wafer production T. Zahel, G. Otto, G. Hobler
Institute of Solid State Electronics, Vienna University of Technology Floragasse 7/362, A-1040 Vienna, Austria

9:45-10:00

1.6

Status of SiGe HBTs on SOI 1 1 2 2 S.Hall , O.Buiu , N.Lukyanchikova , N.Garbar , A. 2 2 3 Smolanka , M. Lokshin , I.Mitrovic , H.A.W. 3 3 El Mubarek , P.Ashburn , B. M. Armstrong, H. Gamble
1Department of Electrical Engineering & Electronics, University of Liverpool, Liverpool, L693BX, UK, 2Institute of Semiconductor Physics, 03028, Kiev, Ukraine, 3School of Electronics & Computer Science, University of Southampton, Southampton, SO17 1BJ, UK. 4Department of Electronic and Electrical Engineering, Queens University Belfast, Belfast, UK.

10:00-10:15

1.7

Customized BSOI substrates and SOI processed layer transfer 1 1 Bernard Aspar , Chrystelle Lagahe-Blanchard , 2 Hubert Moriceau
1TRACIT Technologies - Zone Astec - 17 Rue des Martyrs, 38054 Grenoble Cedex 9 France 2CEA-DRT-LETI - CEA/Gre - 17 Rue des Martyrs, 38054 Grenoble Cedex 9 France

10:15-10:30

1.8

Influence of traps in gate oxide-Si film transition layers on FD MOSFETs characteristics at cryogenic temperatures V.S. Lysenko*, I.P. Tyagulsky, I.N. Osiyuk, A.N. Nazarov Lashkaryov
Institute of Semiconductor Physics (ISP), Kyiv, UKRAINE

10:30-11:00

Coffee Break

SESSION 2

DEVICES AND SIMULATION I Chair: Prof. J. Ahopelto

VTT, Finland 2.1 New Memory Effect for Fully Depleted SOI MOSFET 1, 2 1 1 M. Bawedin , S. Cristoloveanu , J. G. Yun , D. 2 Flandre
1 IMEP, ENSERG, BP 257, 38016 Grenoble, France 2 Microelectronics Lab. (DICE), UCL, Louvain-La-Neuve, Belgium

11:00-11:15

10

11:15-11:30

2.2

Impact of Hot-Carrier Stress on Gate-Induced Floating Body Effects and Drain Current Transients of Thin-Gate-Oxide Partially Depleted SOI NMOSFETs 1 2 2 J.M. Raf *, E. Simoen , A. Mercha , and C. 2,3 Claeys
1 Institut de Microelectrnica de Barcelona (CNM-CSIC), Campus UAB, 08193 Bellaterra, Spain 2 IMEC, Kapeldreef 75, B-3001 Leuven, Belgium 3 KU Leuven, Electr. Eng. Dept., Kasteelpark Arenberg 10, B-3001 Leuven, Belgium

11:30-11:45

2.3

Numerical and experimental investigation of the RF dynamic and noise performance of sub100nm partially depleted SOI MOSFETs R. Rengel, M, J. Martn, G. Pailloncy, G.Dambrine, F. Danneville
Departamento de Fsica Aplicada, Universidad de Salamanca, Spain Dpartement Hyperfrquences et Semiconducteurs, I. E. M. N., France

11:45-12:00

2.4

Mobility, velocity and average energy in UltrThin-Body SOI MOSFETs L. Lucci, P. Palestri, D. Esseni, L. Selmi
DIEG, Univ. of Udine, Via delle Scienze 208, 33100 Udine, Italy

12:00-12:15

2.5

Physic-based compact model for surroundinggate MOSFET D. Jimnez, B. Iguez, J. Su, L. F. Marsal, J. Pallars, J. Roig, D. Flores
Departament dEnginyeria Electrnica, Universitat Autnoma de Barcelona. Departament dEnginyeria Electrnica, Elctrica i Automtica, Universitat Rovira i Virgili Centro Nacional de Microelectrnica (CNM-CSIC)

12:15-12:30

2.6

Experimental mobility study of DG-GAA MOSFETs down to 40nm gate length A. Cros, S. Harrison, P. Coronel, E. Balossier, T. Stotnicki, H. Brut, G. Ghibaudo
ST Microelectronics, Crolles, France IMEP, Grenoble, France L2MP, Marseille, France

12:30-12:45

2.7

Integration of high thermal conductivity buried insulators in SOI MOSFETs N. Bresson, S. Cristoloveanu, C. Mazur, F.Letertre, H. Iwai
SOITEC S.A. Crolles, France IMEP, Grenoble France Tokyo Institute of Technology, Japan

11

12:45-13:00

2.8

Power FINFET for scalable and reliable Smart Power circuits J. Roig , B. Iiguez , D. Flores , D. Jimnez , J. 2 2 2 Urresti , S. Hidalgo , and J. Rebollo
1Centro Nacional de Microelectrnica, CNM-CSIC, Campus UAB, 08193 Bellaterra, Barcelona, Spain Corresponding author: jaume.roig@cnm.es, Tel. 34 935947700, Fax. 34 935801496 2 Departament dEnginyeria Electrnica, Elctrica i Automtica, ETSE, URV 43007-Tarragona, Spain 3 Departament dEnginyeria Electrnica, ETSE, UAB, 08193Bellaterra, Barcelona, Spain
1 2 1 3

13:00-15:00

LUNCH

SESSION 3

DEVICES AND SIMULATION II Chair: Prof. J.Carceller

University of Granada, Spain 3.1 Theoretical investigation of the resonant tunnelling currents in the Double Gate SOI Structure B. Majkusiak
Institute of Microelectronics and Optoelectronics, Warsaw University of Technology Koszykowa 75, 00-662 Warsaw, Poland

15:00-15:15

15:15-15:30

3.2

Compact model for quasi-ballistic double gate MOSFET Hamdy A. Hamid, B. Iguez, D. Jimnez, L. F. Marsal, and J. Pallars
Departament dEnginyeria Electrnica, Elctrica i Automtica; Escola Tcnica Superior dEnginyeria; Universitat Rovira i Virgili; 43007-Tarragona, Spain. Departament dEnginyeria Electrnica; Escola Tcnica Superior dEnginyeria; Universitat Autnoma de Barcelona; 08193-Bellaterra (Barcelona), Spain

15:30-15:45

3.3

The potential impact of confined acoustic phonons in SOI-based nanoelectronics 1,2 2 3 C M Sotomayor Torres , A Zwick , M Prunnila , J 3 2 2 2 Ahopelto , A Mlayah , F Poinsotte , J Groenen 2 and V Paillard
1 National Microelectronics Research Centre, University College Cork, Lee Maltings, Prospect Row, Cork, Ireland. 2 Laboratory of Solid State Physics (LPST) UMR 5477 , Paul Sabatier University, 118 route de Narbonne, F-31062 Toulouse Cedex 04, France. 3 VTT Centre for Microelectronics, Tietotie 3, FIN-02150 Espoo, Finland.

12

15:45-16:00

3.4

Electronic transport in thin double-gate SOI MOSFETs 1 1 1 M. Prunnila , J. Ahopelto , K. Henttinen , H. 2 3 Sakaki , and F. Gamiz
1VTT Information Technology, Microelectronics, P.O.Box 1208, FIN-02044 VTT, Finland 2University of Tokyo, Institute of Industrial Science, 4-6-1 Komaba, Meguro-ku, Tokyo 1538503, Japan 3Departamento de Eletrnica, Universidad de Granada, Avenida Fuentenueva s/n 18071 Granada, Spain

16:00-16:15

3.5

Quantum transport in ultra scaled double-gate MOSFETs: A Wigner function-based Monte Carlo approach. A. Gehring, V. Sverdlov, H. Kosina, S. Selberherr
Institute for Microelectronics, TU Wien, Gusshausstrasse 2729/E360, 1040 Wien, Austria

16:15-16:30

3.6

3-D simulations of Multiple-Gate SOI MOSFETs in static and dynamic regimes T. M. Chung, A. Kranti, J. P. Raskin
Microwave Laboratory (EMIC), Universit catholique de Louvain, Place du Levant 3, Batiment Maxwell, 1348 Louvain-la-Neuve, Belgium.

16:30-16:45

3.7

Quantum Induced Suppression of Corner Effects in Double, Triple and Quadruple-Gate SOI Transistors R. Ritzenthaler, O. Faynot, C. Jahan and S. Cristoloveanu*
CEA-LETI/D2NT - 17, rue des Martyrs, 38054 Grenoble Cedex 9, France *IMEP (UMR CNRS-INPG-UJF), ENSERG, BP 257, 38016 Grenoble Cedex 1, France.

16:45:17:00

3.8

A comprehensive study of carrier velocity modulation in DGSOI transistors C. Sampedro, F. Gmiz, A. Godoy, M. Prunnila*, J. Ahopelto*
Departamento de Electrnica. Universidad de Granada. 18071 Granada (Spain). * VTT Information Technology, P.O.Box 1208, FIN-02044 Espoo (Finland)

SESSION 4 17:00-19:00
4.1

POSTER SESSION
Silicon on silicide on insulator substrates P. Baine, M. Bain, M. Jin, H.S. Gamble, B. M. Armstrong, D. H. Campbell
Northern Ireland Semiconductor Research Centre, School of Electrical and Electronic Engineering, Queens University Belfast, Ashby Building, Stranmillis Road, Belfast BT9 5AH

4.2

Parameter sensitivity for optimal design of 25 nm double gate SOI transistors T C Lim, G A Armstrong
School of Electrical and Electronics Engineering, Queens University Belfast, Stranmillis Rd, NI, UK. BT9 5AH

13

4.3

Analysis and selection of 2-D and bulk-like states in P-type FDSOI devices F.M. Gmez-Campos, S. Rodrguez-Bolvar, J. E. Carceller
Departamento de Electrnica y Tecnologa de Computadores, Facultad de Ciencias, Universidad de Granada, 18071, Granada, Spain

4.4

Extraction of charge trapping parameters in FD SOI MOSFET oxides subjected to -irradiation 1 1 1 Yuri Houk , Alexei Nazarov , Viktor Turchanikov , 1 2 Vladimir Lysenko , Stephan Andriaensen , Denis 2 Flandre
1Lashkaryov Institute of Semiconductor Physics (ISP), Kyiv, UKRAINE, 2Universit Catholique de Louvain (UCL), Louvain-la-Neuve, BELGIUM

4.5

Degradation and capacitance analysis of a retrograde drift doped SOI LDMOS with and without source field plate I. Cortes, D. Flores, J. Roig, J. Urresti, S Hidalgo and J. Rebollo
Centro Nacional de Microelectrnica (CNM-CSIC), Campus UAB, 08193, Bellaterra, Barcelona (Spain)

4.6

Magnetoresistance mobility measurements in gate all around SON MOSFETs W. Chaisantikulwat, M. Mouis, G. Ghibaudo, D.K. Maude, A. Cros, S. Harrison, H. Brut
1) Institut de Microlectronique Electromagntisme et Photonique, 23 Rue de Martyrs 38016 Grenoble, France 2) Laboratoire des Champs Magntiques Intense, CNRS, 25 Rue de Martyrs 38042 Grenoble, France 3) STMicroelectronics, 850 rue J. Monnet, BP.16 38921 Crolles, France

4.7

Field effect and Coulomb blockade in gated silicon on insulator I. Ionica, L. Monts, S. Ferraton, J. Zimmermann, L. Saminadayar, V. Bouchiat
Institut de Microlectronique, Electromagnetisme et Photonique (IMEP), Grenoble, France Centre de Recherche sur les Trs Basses Temperatures, CNRS, Grenoble France

4.8

C-continuous AM SOI pMOSFET model for high temperature applications 1 2 3 Yuri Houk , Benjamin Iiguez , Denis Flandre , 1 Alexei Nazarov
1Lashkaryov Institute of Semiconductor Physics (ISP), Kyiv, UKRAINE, 2Universitat Rovira i Virgili (URV), Tarragona (Catalonia), SPAIN, 3Universit Catholique de Louvain (UCL), Louvain-la-Neuve, BELGIUM

4.9

Limits of the 1st and 2 switch method for history effect characterization in digital circuits V. Liot, P. Flatresse
ST Microelectronics, 850, rue Jean Monnet, F38921 Crolles Cedex, France

nd

14

4.10

FinFET analog characterization from DC to 110 GHz 1 2 3 D. Lederer , V. Kilchytska , T. Rudenko N. 4 2 4,5 Collaert , D. Flandre , A. Dixit , 4,5 1 K. De Meyer and J.-P. Raskin
1 Microwave and 2 Microelectronic Laboratories of UCL, Place du Levant, 3 1348 Louvain-la-Neuve, Belgium 3 Institute of Semiconductor Physics, Kiev, Ukraine 4 IMEC, Kapeldreef 75, 3001 Heverlee, Belgium 5 KULEUVEN, ESAT-INSYS, Kasteelpark Arenberg 10, 3001 Heverlee, Belgium

4.11

Explicit continuous model for surrounding gate MOSFETs B. Iguez, D. Jimnez, L. F. Marsal, and J. Pallars and J. Roig
Departament dEnginyeria Electrnica, Elctrica i Automtica; Escola Tcnica Superior dEnginyeria; Universitat Rovira i Virgili; 43007-Tarragona, Spain. Departament dEnginyeria Electrnica; Escola Tcnica Superior dEnginyeria; Universitat Autnoma de Barcelona; 08193-Bellaterra (Barcelona), Spain. Centro Nacional de Microelectrnica, CNM-CSIC, Campus UAB, 08193 Bellaterra, Barcelona, Spain.

4.12

Towards the Terahertz NanoTransistor: The Roles of the Displacement Current and the Electron Phase-Coherence E.Fernndez-Daz, A.Alarcn and X.Oriols
Departament dEnginyeria Electrnica - Universitat Autnoma de Barcelona 08193 Bellatera Catalonia - SPAIN

4.13

Crosstalk suppression in SOI substrates P. Baine, M. Bain, M. Jin, H.S. Gamble, B. M. Armstrong, D. Linton, D. W. McNeill, J. Montgomery
Northern Ireland Semiconductor Research Centre, School of Electrical and Electronic Engineering, Queens University Belfast, Ashby Building, Stranmillis Road, Belfast BT9 5AH

4.14

Comparison between 0.13 m PD-SOI gated diode and non gated diode through DC TCAD simulations Christophe Entringer*, Philippe Flatresse*, Pascal Salome*, Pascal Nouet** and Florence Azais**
*ST Microelectronics Crolles, 850,rue Jean Monnet F-38926 Crolles Cedex tel : 04 38 78 27 07 fax : 04 76 92 56 78 **LIRMM 161, UMR CNRS/Universit Montpellier II, rue Ada, 34392Montpellier Cedex 05

4.15

Characterization and modeling of SOI MOSFET velocity overshoot: enhancement of SPICE BSIMSOI model A. Roldn, J. B. Roldn, F. Gmiz
Departamento de Electrnica y Tecnologa de Computadores. Universidad de Granada. Facultad de Ciencias. Avd. Fuentenueva s/n 18071 Granada (Spain)

15

4.16

Design and fabrication issues in ultra-thin film SOI MEMS resonators K. Buchheit, N. Abel, A. M. Ionescu
Institute of Microelectronics and Microsystems, Electronics Laboratories (LEG), Ecole Polytechnique Fdral de Lausanne (EPFL), Bt. ELB, CH-1015 Lausanne

4.17

Fabrication of Patterned and Mixed SOI 1 1 1 H. Moriceau , A.M. Charvet , C. Morales , M. 1 1 1 Zussy , J. Dechamp , N. Kernevez , 2 2 2 F. Letertre , B. Ghyselen , C. Mazure , C. 3 3 Lagahe-Blanchard , B. Aspar
1 CEA-DRT-LETI - CEA/Gre - 17 Rue des Martyrs, 38054 Grenoble Cedex 9 France 2 Soitec S.A., Parc Technologique des Fontaines, 38190 Bernin France 3 TRACIT Technologies S.A., Zone Astec -15 rue des martyrs, 38054 Grenoble Cedex 9 France

4.18

Embedded EEPROM in PD-SOI for Application in an Extended Temperature Range (-40 C up to 225 C) D. Kirsten, S.G.M. Richter, D.M. Nuernbergk and S.B. Richter*
Institute for Microelectronic and Mechatronic Systems gGmbH, Ilmenau, Germany, *X-FAB Semiconductor Foundries AG, Erfurt, Germany

4.19

High transmission gain Integrated Antennas on SOI substrate for VLSI wireless interconnect 1 1 2 A.Triantafyllou , A. Farcy , P.Benech , F. 2 2 1 1 Ndagijimana , O. Exshaw , J.Torres , C.Tinella , 1 C. Raynaud
1 2

STMicroelectronics: 850, rue Jean Monnet, 38926 Crolles Cedex, France ; mail: anna.triantafyllou@st.com IMEP: ENSERG, 23 rue des Martyrs, BP 257, 38016 Grenoble cedex 1,

21st January SESSION 5 CIRCUITS AND APPLICATIONS I Chair: Prof.Cor Claeys

IMEC, Belgium 8:30-9:00 5.1 CAD methodology for history effect characterization in PD-SOI libraries (Invited) P. Flatresse
ST Microelectronics, 850, rue Jean Monnet, F-38921 Crolles Cedex, France

9:00-9:15

5.2

Hybrid full adder cell in 0.13 m PD SOI CMOS for low voltage low-power applications I. Hassoune, J. D. Legat, D. Flandre
UCL, Microelectronics Laboratory, Place du Levant, 3, B-1348, Louvain-la-Neuve, Belgium

16

9:15-9:30

5.3

A partially depleted SOI 4 transistors selfrefresh ultra-low-voltage memory cell O. Thomas, A. Amara
ISEP, 21 rue dAssas, 75270 Paris cedex 06, France

9:30-9:45

5.4

First silicon fully functional Bulk-PDSOI migration of low-power SRAM 1) 2) 3) M.R. Casu , P. Flatresse , R. Gwoziecki , W. 2) 3) Pinnaire and C. Raynaud
1)Politecnico di Torino, Cso Duca degli Abruzzi 24, I-10129 Torino, Italy 2)ST Microelectronics, 850, rue Jean Monnet, F-38921 Crolles Cedex, France 3)LETI/CEA-Grenoble, 17 rue des Martyrs, F-38054 Grenoble Cedex 9, France

9:45-10:00

5.5

Crosstalk Reduction using low resistivity SOI J. Ankarcrona, L. Vestling, K. H. Eklund, J. Olsson
Uppsala University, The ngstrm Laboratory, Solid State Electronics, Uppsala, Sweden

10:00-10:15

5.6

Applications of SOI Materials to Quantum Devices and Microsystems 1) 1,3) Johan Piscator , Alexandra Nafari , Martin 1) 1,2) 1) Bring , Henrik Rdjegrd , Anke Sanz-Velasco , 1) 1) Peter Enoksson , Olof Engstrm and Stefan 1) Bengtsson
1)Solid State Electronics Laboratory, Department of Microtechnology and Nanoscience (MC2) Chalmers University of Technology, SE-412 96 Gteborg, Sweden 2)Imego AB, Arvid Hedvalls Backe 4, SE-411 33 Gteborg, Sweden 3)Nanofactory Instruments AB, Walleriusgatan 2, SE-412 58 Gteborg, Sweden

10:15-10:30

5.7

Optimization of Spiral Inductors on Highresistivity SOI Substrates for Low-power LCVCO Design 1 2 1 3 P. Delatte , P. Simon , L. Demes , D. Flandre
1 CISSOID S.A., Chemin du Cyclotron, 1348 Louvain-la-Neuve, Belgium 2 Microwave Lab, Universit catholique de Louvain, Place du Levant 3, 1348 Louvain-la-Neuve, Belgium 3 Microelectronics Lab, Universit catholique de Louvain, Place du Levant 3, 1348 Louvain-la-Neuve, Belgium

10:30-11:00

5.8

SOI technology for low power microprocessors (Invited talk) A.Perera

High Performance Device Integration Freescale Crolles, France

11:00-11:30

Coffee Break

17

SESSION 6

CIRCUITS AND APPLICATIONS II Chair: Prof. Amara Amara

ISEP, France 6.1 SOI for 45nm and beyond (Invited) G.Shahidi
IBM, T.J. Watson Research Center Yorktown Heights, NY 10598 U.S.A.

11:30-12:00

12:00-12:15

6.2

Technology Issues in SOI RFIC A. Dubreuil

DITOCOM, Campus de Ker Lann, BP 57446, 35174 Bruz (Cedex), France

12:15-12:30

6.3

Linear Regulators for High Temperature Applications Dirk M. Nuernbergk, Volker Boos, Stefan Bormann, Patrick Witzenhausen
Institute for Microelectronic and Mechatronic Systems gGmbH, Ilmenau, Germany

12:30-12:45

6.4

Design of a travelling wave amplifier in 0.13m partially depleted SOI 3 1,2 1 M. Si Moussa , C. Pavageau , F. Danneville , J. 2 2 3 Russat , N. Fel , J. P. Raskin and 3 D. Vanhoenacker-Janvier
1 IEMN UMR CNRS 8520, Villeneuve dAsq, France 2 CEA, Bruyres-Le-Chtel, France 3 EMIC, Microwave laboratory, Microwave Laboratory Universit Catholique de Louvain Maxwell Building, Place du Levant, 3, 1348 Louvain-la-Neuve, Belgium

12:4513:00

6.5

SOI Gate-All-Around optical modulators for high frequency applications 1 1,2 1 K. Moselund , P. Dainesi , L. Thvenaz , M. 1 1 Declerq , A. M. Ionescu
1 Electronics Laboratory. 2 Nanophotonics and Metrology Laboratory Swiss Federal Institute of Technology, EPFL, Switzerland

13:00-14:00

RAMP SESSION. Conclusions. SOI Roadmap Chair: Prof. J.B.Roldn

Universidad de Granada (Spain)

14:00-16:00

LUNCH

18

Characterization and modeling of SOI MOSFET velocity overshoot: enhancement of SPICE BSIMSOI model
A.Roldn, J.B.Roldn, F.Gmiz
Departamento de Electrnica y Tecnologa de Computadores. Universidad de Granada. Facultad de Ciencias. Avd. Fuentenueva s/n 18071 Granada (Spain). E-mail: amroldan@ugr.es

1. Abstract
We have improved the SPICE BSIMSOI model to account for velocity overshoot (VO) effects in single gate SOI MOSFETs. We introduce a new velocity overshoot parameter (VO) and an extraction method to obtain it. The transconductance curves needed to perform the extraction process have been obtained by means of an ensemble Monte Carlo simulator. A 51 stage oscillator ring and the influence of VO effects on the oscillation frequency have been studied. It has been shown that the oscillation frequency rises as VO effects increases, a quantitative relationship has been depicted.
I DS =

Weff F (Vgs ,Vds )

Vds Leff 1+ vsat Leff

+ OV

Weff F (Vgs ,Vds ) 2 Leff

(1)

2. Simulation and Results

Velocity overshoot effects have been studied both theoretically and experimentally [1-4]. These non local effects are essential to reproduce the experimental measurements of deep submicron MOSFETs [2-4]. These facts show, taking into consideration that SOI technology will allow the reduction of device channels beyond the prospects of bulk conventional technology [5-6], the need to study and model these effects. To do so, we have used a 2D SOI MOSFET ensemble Monte Carlo simulator to characterize the operation of single gate SOI MOSFETs. The main scattering mechanisms (Coulomb, surface roughness and phonon scattering) have been included in the simulation. Several devices with different technological parameters have been studied. The devices simulated had channel lengths ranging from 0.5 to 0.06 m, where VO effects are known to be important [1-2]. The results obtained have been used to improve the SPICE BSIMSOI model in order to account for VO effects in short channel SOI MOSFETs. To do so, we have made use of a previously developed model [2, 3] to include these effects in the calculation of the drain current (Equation 1) of the devices under study.

We have adapted the equations developed for the calculation of the drain current in the BSIMSOI model [7] to obtain an expression similar to the first term in the right hand side of Equation 1 (in this respect, function F(Vgs,Vds) that represents the integral of the inversion charge in the channel [2] has been compared to obtain its corresponding equation in the BSIMSOI model) in order to be able to include VO effects which are computed by the second term in the right-hand part of Equation 1. The Monte Carlo calculated transconductance curves and the predictions made with the model introduced in [2] are plotted in Figure 1. The velocity overshoot parameter obtained for the two gate-source voltages used was the same, VO =22x10-5 cm3/Vs.
500 450 400

T=300K
with VO

gm (S/m)

350 300 250 200 150 100 50

C oxvsat VGS=1,45 V

without VO V GS=1 V

0,0

0,1

0,2

0,3

0,4

0,5

0,6

Channel length (m)

Fig.1: Single SOI NMOSFET transconductance versus channel length at room temperature. The Monte Carlo calculated data are plotted in symbols. The transconductance model data [2] are shown in lines (dashed lines neglecting VO effects VO=0 and solid lines including VO effects VO0). The low field mobility and the VO used to fit the gm curves obtained were: a) VGS=1V (VO =22x10-5 cm3/Vs and =230 cm2/Vs) b) VGS=1.45 V (=570 cm2/Vs and VO =22x10-5 cm3/Vs).

Oscillation Frequency (MHz)

The value obtained for VO was in the order of the values used previously to reproduce experimental results as VO =25x10-5 cm3/Vs (conventional MOSFETs) [2] and VO =10x10-5 cm3/Vs (SOI MOSFETs) [3]. It has been also shown in Figure 1 the maximum theoretical transconductance value that would be obtained if the electrons had crossed the whole channel with their saturation velocity (gmmax=Coxvsat) and there were no areas in the device where inhomogeneous transport were taking place. The improved BSIMSOI model (using Equation 1 and the new parameter obtained) was used to simulate a 51 stage oscillator ring of CMOS single gate SOI MOSFETs in SPICE. The schematic of the circuit simulated is sketched in Figure 2.

It can be seen an increase of the oscillation frequency as VO rises. In order to highlight this increase we have plotted the oscillation frequency versus the VO parameter (Figure 4). The simulation for VO=0 represents the case where VO effects can be neglected.

195

T=300 K LCH=0,15 m

190

185

180

VDD= 2V

175

10

15

20

25
-5

30
3

35

40

45

50

in

25 INV

out25

25 INV

out50

buffer
INV

out

INV

OV (x10 cm /Vs)

1 pF

Fig.4: Oscillation frequency versus the velocity overshoot parameter at room temperature. Fig.2: Circuit schematic of the 51 stage oscillator ring simulated to study the influence of VO effects on the oscillator frequency.

We have not simulated PMOS devices by the Monte Carlo method, however we have used the results given by Laux et al. [8] where they show that VO effects increase the drain current of 0.1 m channel devices by a factor of 20% (NMOS) and 30% (PMOS). We have used this ratio to include VO effects in the PMOS devices. The results obtained are drawn in Figure 3 where the output voltage for other values of the VO parameter are included for comparison. The device technological features are the following: L=0.15 m, TOX=5 nm, TBOX=500 nm, TSi=90 nm, NA= ND=8x1017 cm-3.
2
=0

It is important to highlight that the control of VO effects in the design process of very short channel SOI MOSFET devices can be used as a means to improve the response of digital circuits as shown above. In this respect, not only a reduction of the channel length, as can be seen in Equation 1, is the way to follow but also an optimal (from the VO effects viewpoint) design to achieve a VO parameter as high as possible. Acknowledgments This work has been partially carried out within the framework of research project TEC2004-03926, supported by the Spanish Government, and EUROSOI and SINANO Networks. References
[1] M.R. Pinto et al., IEEE Electron Device Letters, 14, p. 375 (1993). [2] J.B. Roldn et al. IEEE Transactions on Electron Devices, vol 44, n 5, pp.841-846, (1997). [3] J.B. Roldn et al. IEEE Electron Device Letters, 21, pp.239-241 (2000). [4] G.A. Sai-Halasz, et al, IEEE Electron Device Letters, EDL-9, p.464 (1988). [5] G.K. Celler, et al, Applied Physics Review, 93, p. 49564976, (2003). [6] F. Gamiz, Applied Physics Letters, 84 pp. 299-301, (2004). [7] BSIMSOI Users manual, Dept. of Electrical Engineering and Computer Sciences, Berkeley University, (2003). [8] S.E. Laux, et al., IEDM (1997), pp.877-880.

VOUT (V)

VO=22x10 cm /Vs

-5

VO=40x10 cm /Vs

-5

10

15

20

25

Time (ns)

Fig.3: Ring oscillator output voltage versus simulation time for different velocity overshoot parameter values at room temperature.