Beruflich Dokumente
Kultur Dokumente
Chapter Goals
Describe operation of MOSFETs. Define FET characteristics in operation regions of cutoff, triode and saturation. Develop mathematical models for i-v characteristics of MOSFETs. Introduce graphical representations for output and transfer characteristic descriptions of electron devices. Define and contrast characteristics of enhancement-mode and depletion-mode FETs. Define symbols to represent FETs in circuit schematics. Investigate circuits that bias transistors into different operating regions. Learn basic structure and mask layout for MOS transistors and circuits. Explore MOS device scaling Contrast 3 and 4 terminal device behavior. Describe sources of capacitance in MOSFETs. Explore FET modeling in SPICE.
Intro
MOSFET metal-oxide-semiconductor field-effect transistor Most commercially successful solid-state device High density VLSI chips, including microprocessors, memories (up to 2 billion on a single chip) PMOS p-channel MOS transistors NMOS n-channel MOS transistors Biopolar junction transistor was reduced to practice first, but FET conceptually easier to understand thus covered 1st
4 device terminals: Gate(G), Drain(D), Source(S) and Body(B). Source and drain regions form pn junctions with substrate. vSB, vDS and vGS always positive during normal operation. vSB always < vDS and vGS to reverse bias pn junctions
Can guarantee in cutoff by connecting the Source (S) and Body (B) Conductors can be non-metal silicon based such as polysilicon Voltage applied to the gate controls the current flow between the Drain and Source Device is completely symmetrical and therefore the Source and Drain can be flipped without any effect on the device performance or behavior L typically from 0.03 m to 1.0 m, W typically from 0.1 m to 100 m
NMOSFET
Cox=ox/tox (F/m2) vOV = vGS VTN voltage, vDS establishes an electric field E |E| = vDS/L for vGS VTN vDS 0
ox=oxide
permittivity (F/cm) tox=oxide thickness (cm)
field causes a drift current towards the drain velocity(x) = n|E| = nvDS/L i(x) = (|Q|/unit_length)velocity(x)
v i = Kn v V DS v GS D TN 2 DS
v i = Kn v V DS v GS D TN 2 DS
If vDS increases above triode region limit, channel region disappears, also said to be pinched-off. Current saturates at constant value, independent of vDS. Saturation region operation mostly used for analog amplification.
k' W 2 i = n v D OV 2 L v =v DSAT OV
for
v v DS OV
k' W 2 i = n v D OV 2 L v =v DSAT OV
for
v v DS OV
NMOS Transistor
Channel-Length Modulation
As vDS increases above vDSAT, length of depleted channel beyond pinch-off point, L, increases and actual L decreases. iD increases slightly with vDS instead of being constant.
K 'W 2 i = n v V 1+ v GS D 2 L TN DS
Output resistance
Non-zero linear slope demonstrates the non-ideal finite output resistance that exist in saturation, ro. ro = 1/ (ID) or VA/ID
Output resistance
Non-zero linear slope demonstrates the non-ideal finite output resistance that exist in saturation, ro. ro = 1/ (ID) or VA/ID
MOSFET Circuits at DC
Bias sets the DC operating point around which the device operates.
MOSFET Circuits at DC
Diode-connected transistor (named due to BJT version of this circuit Chp. 6) Important circuit to understand as it is a building block for a very effective current source used in many IC designs
Behaves similar to a diode except with a squared relationship between the voltage and current
MOSFET Inverter
MOSFET Biasing
Bias sets the DC operating point around which the device operates. (Referred to as the Q-point) The signal is actually comprised of relatively small changes in the DC current and/or voltage bias.
MOSFET Amplifier
MOSFET Amplifier
MOSFET Amplifier
MOSFET Amplifier
Problem: Find Q-pt (ID, VDS , VGS) Approach: Assume operation region, find Q-point, check to see if result is consistent with operation region
Assumption: Transistor is saturated, IG=IB=0 Analysis: Simplify circuit with Thevenin transformation to find VEQ and REQ for gate-bias voltage. Find VGS and then use this to find ID. With ID, we can then calculate VDS.
Since IG=0,
V = I R +V =V EQ G EQ GS GS
Check:VDS>VGS-VTN. Hence saturation region assumption is correct. Q-pt: (50.0 A, 5.00 V) with VGS= 3.00 V Discussion: The Q-point of this circuit is quite sensitive to changes in transistor characteristics, so it is not widely used.
K 2 I = n V V D 2 GS TN 6 2510 A 31 2 V2 = 50 A = 2( ) 2 V
Approach: Find an equation for the load line. Use this to find Q-pt at Analysis: For circuit values above, intersection of load line with device load line becomes characteristic. 10 = I 100K +V D DS
= I R +V V DD D D DS
10 = I 100K +V D DS @VDS=0, ID=100uA @ID=0, VDS=10V Plotting on device characteristic yields Q-pt at intersection with VGS = 3V device curve.
Check: The load line approach agrees with previous calculation. Q-pt: (50.0 A, 5.00 V) with VGS= 3.00 V Discussion: Q-pt is clearly in the saturation region. Graphical load line is good visual aid to see device operating region.
Bias Analysis: Example 3 (Constant Gate-Source Voltage Biasing with Channel-Length Modulation)
Problem: Find Q-pt (ID, VDS , VGS) of previous example, given =0.02 V-1. Approach: Assume operation region, find Q-point, check to see if result is consistent with operation region
Assumption: Transistor is saturated, IG=IB=0 Analysis: Simplify circuit with Thevenin transformation to find VEQ and REQ for gate-bias voltage. Find VGS and then use this to find ID. With ID, we can then calculate VDS.
Bias Analysis: Example 3 (Constant Gate-Source Voltage Biasing with Channel-Length Modulation)
K 2 I = n V V 1+ V D 2 GS TN DS V =V I R DS DD D D (25106 ) 2 V =10V (100K) (31) 1+0.02 VDS DS 2 = 4.55 V (25106 ) 2 1+0.02 (4.55) = 54.5 A I = (31) ( ) D 2
Check:VDS>VGS-VTN. Hence saturation region assumption is correct. Q-pt: (54.5 A, 4.55 V) with VGS= 3.00 V
Discussion: The bias levels have changed by about 10%. Typically, component values will vary more than this, so there is little value in including effects in most circuits.
V =2.71V,+2.66V GS
Since IG=0,
V =V +I R EQ GS D S
K 2 V =V + n V V R EQ GS 2 GS TN S
4 =V + GS
25106 3.910 4
2 V 1 GS
VDS>VGS-VTN. Hence saturation region assumption is correct. Q-pt: (34.4 A, 6.08 V) with VGS= 2.66 V
But VDS<VGS-VTN. Hence, saturation region assumption is incorrect Using triode region equation, Assumption: IG=IB=0, transistor is saturated (since VDS= VGS) Analysis: VGS=VDD=4 V
I D = 25 A (4 1)2 = 1.13mA 2 V2
V 4V =1600 250 A (41 DS )V DS DS 2 V2 2 V = 2.3V and ID=1.06 mA DS
gm = K (V
n GS
V ) = 2 K n I TN D
Output resistance: |V | 1 ro = A = I I D D
( (
) )
vgs << 2V V TN GS Since MOSFET can be biased with (VGS - VTN) equal to several volts, it can handle much larger values of vgs than corresponding values of vbe for BJT.
If we replace the MOSFET with the small-signal model, we can solve for the small-signal gain, Av.
v v Av = vo = vds = gm R = gm (R || ro ) L D i gs
1+ g m R S
Ro = R D
CG Avo = gm RD
R =1/ gm i
Ro = R D
CG Avo = gm RL /(1+ gm RL )
Ro =1/ gm
Common-Source Amplifier
Common-Drain Amplifier
Source-Follower Amplifier