Analogue & Digital Telecommunications EE2009 Project Assignment 2012 Viterbi Codec

Phase 2
Design, simulate and implement on the supplied FPGA board the convolutional encoder specified for your group (see below). The PC should send a user specified byte (the final 3 bits being equal to 0 to return the encoder to state A) to the FPGA. The FPGA should then determine the encoded output and then send the result back to the PC (i.e. 8 bits are sent from the PC to the FPGA and 16 bits are sent back). As a set of minimum requirements, your software must then: (i) (ii) (iii) (iv) (v) Enable the user to specify how many of the received 16 bits are to be corrupted (i.e. inverted) and which bits to invert (e.g. corrupt 3 bits as follows: - bit numbers 2, 7 and 11). Introduce these errors into the received sequence. Use the Viterbi decoding algorithm to determine the 8 most likely paths through the trellis and their corresponding running Hamming distances and output these paths/distances to the screen. Decide upon the most likely sequence and determine if this is correct. Enable the user to repeat the decoding process with a new set of errors, or repeat the entire encoding/error injection/decoding cycle.

Once your group has achieved these deliverables, you are encouraged to develop one or more additional features/innovations in such a manner that your basic working solution is not compromised (i.e. dont break your solution while trying to expand/improve upon it).

Deliverables: - 20th March, 2012

(i) (ii) Location IT Lab. Group Presentation of final Viterbi codec. Practical demonstration of the design in the IT lab.

Deliverable : 21st March, 2012

(i) Phase 2 Final Report (once again, a distinct report from each student) detailing the project and the resulting design. To be submitted to www.turnitin.com by 5 pm on 21st March, 2012.

Reminder of marking scheme for Phase 2: Continuous Assessment: 15 marks (3 sessions x 5 marks/session). Group Presentation: 20 marks (G) Practical Demonstration: 10 marks (G) Individual Report: 100 marks. Bonus for acceptable (e.g. fully working) design: 30 marks (G)

Encoder Design Equations Group 1 A

v1 = S1 " S2 v2 = S2 " S3 " S4

Group 2
v1 = S1 " S3 v2 = S1 " S2 " S4

Group 3
v1 = S1 " S4 v2 = S3 " S2 " S4

Group 4
v1 = S2 " S3 v2 = S1 " S2 " S4

Group 1
v1 = S2 " S4

Group 2
v1 = S3 " S4

Group 3
v1 = S1 " S4

Group 4
v1 = S1 " S2 v2 = S1 " S4 " S3

v2 = S1 " S3 " S4

v2 = S1 " S3 " S2

v2 = S1 " S4 " S2

Group 1
v1 = S1 " S3

Group 2
v1 = S1 " S3

Group 3
v1 = S2 " S4

Group 4
v1 = S3 " S4 v2 = S4 " S2 " S1

v2 = S1 " S2 " S4

v2 = S3 " S2 " S4

v2 = S3 " S2 " S1