Beruflich Dokumente
Kultur Dokumente
2005
SPECTRUM DIGITAL, INC. 12502 Exchange Dr., Suite 440 Stafford, TX. 77477 Tel: 281.494.4505 Fax: 281.494.5310 sales@spectrumdigital.com www.spectrumdigital.com
IMPORTANT NOTICE Spectrum Digital, Inc. reserves the right to make changes to its products or to discontinue any product or service without notice. Customers are advised to obtain the latest version of relevant information to verify data being relied on is current before placing orders. Spectrum Digital, Inc. warrants performance of its products and related software to current specifications in accordance with Spectrum Digitals standard warranty. Testing and other quality control techniques are utilized to the extent deemed necessary to support this warranty. Please be aware, products described herein are not intended for use in life-support appliances, devices, or systems. Spectrum Digital does not warrant, nor is it liable for, the product described herein to be used in other than a development environment. Spectrum Digital, Inc. assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does Spectrum Digital warrant or represent any license, either express or implied, is granted under any patent right, copyright, or other intellectual property right of Spectrum Digital, Inc. covering or relating to any combination, machine, or process in which such Digital Signal Processing development products or services might be or are used. WARNING This equipment is intended for use in a laboratory test environment only. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonable protection against radio frequency interference. Operation of this equipment in other environments may cause interference with radio communications, in which case the user, at his own expense, will be required to take any measures necessary to correct this interference. TRADEMARKS eZdsp is a trademark of Spectrum Digital, Inc.
Contents
Introduction to the eZdspTM F2808 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Provides a description of the eZdspTM F2808, key features, and board outline. 1.0 Overview of the eZdspTM F2808 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.1 Key Features of the eZdspTM F2808 TM 1.2 Functional Overview of the eZdsp F2808 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 2-1 2 Operation of the eZdspTM F2808 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Describes the operation and various interfaces of the eZdspTM F2808. 2.0 The eZdspTM F2808 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.1 The eZdspTM F2808 Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.1.1 Power Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.2 eZdspTM F2808 Memory 2.2.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.3 eZdspTM F2808 Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.3.1 P1, JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.3.2 P3, USB Port/JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.3.3 P4,P8,P7, I/O Interface ................................................ 2-8 2.3.4 P5,P9, Analog Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2.3.5 P6, Power Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 2.3.6 P10, RS-232 Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 2.3.7 P11, CAN Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 2.3.8 J10, SCIB 5 x 2 Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 2.3.9 J11, CANB 5 x 2 Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 2.3.10 Connector Part Numbers ............................................. 2-15 TM 2.4 eZdsp F2808 Jumpers ............................................... 2-15 2.4.1 JP4, Voltage Jumper, +3.3/5 Volts for P8, P4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 2.4.2 JP5, ADCREFIN Select ............................................... 2-17 2.4.3 JP6, GPIO22/GPIO24 Select .......................................... 2-17 2.5 Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 2.5.1 Switch SW1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 2.5.1.1 Switch SW1, Position 1-3, Boot Mode Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 2.5.1.2 Switch SW1, Position 4, EEPROM Write Enable/Disable . . . . . . . . . . . . . . . . . . 2-19 2.5.1.3 Switch SW1, Position 5, Select EEPROM Pull-ups . . . . . . . . . . . . . . . . . . . . . . . 2-20 2.5.1.4 Switch SW1, Position 6, Serial EEPROM Address A1 . . . . . . . . . . . . . . . . . . . . 2-20 2.5 Switch SW2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 2.6 LEDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 2.7 Test Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 A eZdspTM F2808 Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 Contains the schematics for the socketed and unsocketed versions of the eZdspTM F2808 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 B eZdspTM F2808 Mechanical Information Contains the mechanical information about the socketed and unsocketed versions of the eZdspTM F2808 1
List of Figures ..................................... Figure 1-1, Block Diagram eZdspTM F2808 TM Figure 2-1, eZdsp F2808 PCB Outline ...................................... ................................... Figure 2-2, eZdspTM F2808 Memory Space TM F2808 Connector and Switch Positions ...................... Figure 2-3, eZdsp Figure 2-4, Connector P1 Pin Locations ....................................... Figure 2-5, Connector P8 Connector .......................................... Figure 2-6, Connector P5/P9 Pin Locations ................................... Figure 2-7, Connector P6 Location .......................................... Figure 2-8, eZdspTM F2808 Power Connector ................................. Figure 2-9, P10, DB9 Female Connector ..................................... Figure 2-10, P11, DB9 Female Connector .................................... Figure 2-11, eZdspTM F2808 Jumper Positions (Bottom Side) .................... Figure 2-12, JP4 Layout .................................................. Figure 2-13, JP6 Layout .................................................. Figure 2-14, SW1 Layout ................................................. Figure 2-15, SW2 Layout ................................................. 1-3 2-2 2-4 2-6 2-7 2-8 2-10 2-11 2-11 2-12 2-12 2-16 2-16 2-17 2-18 2-21
List of Tables Table 2-1, eZdspTM F2808 Connectors ....................................... Table 2-2, P1, JTAG Interface Connector ...................................... Table 2-3, P4/P8, I/O Connectors ........................................... Table 2-4, P5/P9, Analog Interface Connector ................................ Table 2-5, P10, RS-232 Pinout ............................................. Table 2-6, P11, CANA Pinout ............................................. Table 2-7, J10, 5 x 2 Pinout .............................................. Table 2-8, J11, 5 x 2 Pinout .............................................. Table 2-9, eZdspTM F2808 Suggested Connector Part Numbers ................ TM F2808 Jumpers Table 2-10, eZdsp ........................................ Table 2-11, JP4, +3.3/5 Volts to P8 ........................................ Table 2-12, JP6, GPIO22/GPIO24 Select ................................... Table 2-13, SW1, Switch Positions ......................................... Table 2-14, SW1, Positions 1-3 ............................................ Table 2-15, SW1, Position 4 ............................................... Table 2-16, SW1, Position 5 ............................................... Table 2-17, SW1, Position 6 ............................................... Table 2-18, SW2, Switch Positions ......................................... Table 2-19, LEDs ........................................................ Table 2-20, Test Points ................................................... 2-5 2-7 2-9 2-10 2-12 2-13 2-14 2-14 2-15 2-15 2-17 2-18 2-18 2-19 2-19 2-20 2-20 2-21 2-22 2-22
About This Manual This document describes board level operations of the eZdspTM F2808 based on the Texas Instruments TMS320F2808 Digital Signal Processor. The eZdspTM F2808 is a stand-alone module permitting engineers and software developers evaluation of certain characteristics of the TMS320F2808 DSP to determine processor applicability to design requirements. Evaluators can create software to execute onboard or expand the system in a variety of ways. Notational Conventions This document uses the following conventions. The eZdspTM F2808 will sometimes be referred to as the eZdsp. eZdsp will include the socketed or unsocketed version Program listings, program examples, and interactive displays are shown in a special italic typeface. Here is a sample program listing. equations !rd = !strobe&rw;
Information About Cautions This book may contain cautions. This is an example of a caution statement. A caution statement describes a situation that could potentially damage your software, hardware, or other equipment. The information in a caution is provided for your protection. Please read each caution carefully. Related Documents Texas Instruments TMS320F28x DSP CPU and Instruction Set Reference Guide, literature #SPRU430 Texas Instruments TMS320F28x Assembly Language Tools Users Guide, literature #SPRU513 Texas Instruments TMS320F28x Optimizing C/C++ Compiler Users Guide, literature #SPRU514 Texas Instruments Code Composer Studio Getting Started Guide, literature #SPRU509
Table 1: Manual History Revision A B C History Preliminary Release Production Release Corrected Table in Chapter 2
Topic
1.0 1.1 1.2 Overview of the eZdspTM F2808 Key Features of the eZdspTM F2808 Functional Overview of the eZdspTM F2808
Page
1-2 1-2 1-3
1-1
1-2
CLOCK
20 Mhz.
A N A L O G
TMS320F2808
EXTERNAL JTAG SCIA SCIB
1-3
1-4
This chapter describes the operation of the eZdspTM F2808, key interfaces and includes a circuit board outline.
Topic
2.0 2.1 2.1.1 2.2 2.2.1 2.3 2.3.1 2.3.2 2.3.3 2.3.4 2.3.5 2.3.6 2.3.7 2.3.8 2.3.9 2.3.10 2.4 2.4.1 2.4.2 2.4.3 2.5 2.5.1 2.5.1.1 2.5.1.2 2.5.1.3 2.5.1.4 2.5.2 2.6 2.7 The eZdspTM F2808 Operation The eZdspTM F2808 Board Power Connector eZdspTM F2808 Memory Memory Map eZdspTM F2808 Connectors P1, JTAG Interface P3, USB Port/JTAG Interface P8, I/O Interface P5,P9, Analog Interface P6, Power Connector P10, RS-232 Connector P11, CAN Connector J10, SCIB 5 x 2 Connector J11, CANB 5 x 2 Connector Connector Part Numbers eZdspTM F2808 Jumpers JP4, Voltage Jumper, +3.3/5 Volts for P8, P4 JP5, ADCREFIN Select JP6, GPIO22/GPIO24 Select Switches Switch SW1 Switch SW1, Position 1-3, Boot Mode Select Switch SW1, Position 4, EEPROM Write Enable/Disable Switch SW1, Position 5, Select EEPROM Pull-ups Switch SW1, Position 6, Serial EEPROM Address A1 Switch SW2 LEDs Test Points
Page
2-2 2-2 2-3 2-3 2-4 2-5 2-7 2-8 2-8 2-10 2-11 2-12 2-13 2-14 2-14 2-15 2-15 2-16 2-17 2-17 2-18 2-18 2-19 2-19 2-20 2-20 2-21 2-22 2-22 2-1
2-2
2-3
Block Start Address Data Space 0x0000-0000 0x0000-0400 0x0000-0800 0x0000-0D00 0x0000-0E00 0x0000-6000 0x0000-7000 0x0000-8000 0x0000-9000 0x0000-A000 0x0000-C000 0x003D-7800 0x003D-7800 0x003E-8000 0x003F-7FFF 0x003F-8000 0x003F-9000 0x003F-A000 0x003F-C000 0x003F-F000
F2808 Program Space M0 SARAM M1 SARAM Peripheral Frame 0 Pie Vector Table (256 x 16) Peripheral Frame 1 Peripheral Frame 2 (16 Bit access only) Do Not Use ! Do Not Use !
Flash (Read Only) (64K x 16) L0 SARAM Mirror L1 SARAM Mirror H0 SARAM Mirror
2-4
2-5
J201
P1
P10
J10
P11
JP3
JP1
J11
P6
SW2
P8
SW1
P5/P9
JP5
2-6
1 2 P1
Fig 2-4, P1 Pin Locations The definition of P1, which has the JTAG signals is shown below. Table 2: P1, JTAG Interface Connector Pin # 1 3 5 7 9 11 13 Signal TMS TDI PD (+5V) TDO TCK-RET TCK EMU0 Pin # 2 4 6 8 10 12 14 Signal TRSTGND no pin GND GND GND EMU1
2-7
2 1
4 3
6 5
8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
P8
2-8
* Default is No Connect (NC). User can jumper to +3.3V or +5V on backside of eZdsp with JP4.
2-9
P5 1 2 1 P9 2 4 3 3 6 5 4 8 7
ANALOG 5 9 6 7 8 9 10 10 12 14 16
18 20
11 13 15 17 19
The definition of P5/P9 signals are shown in the table below. Table 4: P5/P9, Analog Interface Connector P5 Pin # 1 2 3 4 5 6 7 8 9 10 Signal ADCINB0 ADCINB1 ADCINB2 ADCINB3 ADCINB4 ADCINB5 ADCINB6 ADCINB7 ADCREFM ADCREFP P9 Pin # 1 3 5 7 9 11 13 15 17 19 Signal GND GND GND GND GND GND GND GND GND GND P9 Pin # 2 4 6 8 10 12 14 16 18 20 Signal ADCINA0 ADCINA1 ADCINA2 ADCINA3 ADCINA4 ADCINA5 ADCINA6 ADCINA7 VREFLO * No connect
* Connect VREFLO to AGND or VREFLO of target system for proper ADC operation.
2-10
2-11
Figure 2-9, P10, DB9 Female Connector The pin numbers and their corresponding signals are shown in the table below. This corresponds to a standard dual row to DB-9 connector interface used on personal computers. Table 5: P10, RS-232 Pinout
Pin # 1 2 3 4 5 6 7 8 9 Signal Name No Connect PCRXDA PCTXDA No Connect GND No Connect No Connect No Connect No Connect N/A Out In Direction
2-12
Figure 2-10, P11, DB9 Female Connector The pin numbers and their corresponding signals are shown in the table below. Table 6: P11, CANA Pinout
Pin # 1 2 3 4 5 6 7 8 9 Signal Name No Connect CANLA GND No Connect No Connect No Connect CANHA No Connect No Connect
2-13
2.3.9 J11, CANB 5 x 2 Header The CANB signals are routed through the SN65HVD235 CAN driver to a 5 x 2 double row header, J11. The pin numbers for J11 and their corresponding signals are shown in the table below. Table 8: J11, 5 x 2 Pinout
Pin # 1 3 5 7 9 Signal Name No Connect CANLB GND No Connect No Connect Pin # 2 4 6 8 10 Signal Name No Connect CANHB No Connect No Connect No Connect
2-14
Table 9: eZdspTM F2808 Suggested Connector Part Numbers Connector P1 P2 Male Part Numbers SAMTEC TSW-1-10-07-G-T SAMTEC TSW-1-20-07-G-T *SSW or SSQ Series can be used 2.4 eZdspTM F2808 Jumpers The eZdspTM F2808 has 2 jumpers, JP4 and JP5. JP4 will allow power to be supplied to the expansion headers. Jumper JP5 selects the ACDREFIN. The table below lists the jumpers and their function. The following sections describe the use of each jumper. Table 10: eZdspTM F2808 Jumpers Jumper # JP1 JP3 JP4 JP5 JP6 Size 1x2 1x2 1x3 1x2 1x3 Function Terminator Resistor - CANB Terminator Resistor - CANA +3.3/5 Volts to P8 Pin 1,2 and P4, Pin 1 Selects ADCREFIN voltage Selects GPIO22 or GPIO24 to Pin 33, P8 Position As Shipped From Factory Installed Installed Not connected Not connected 2 - 3, GPIO24 to Pin 33, P8 Female Part Numbers SAMTEC SSW-1-10-01-G-T SAMTEC SSW-1-20-01-G-T
2-15
JP6
JP4
Figure 2-12, JP4 Layout The table below shows the functions of the two positions of JP4. Table 11: JP4, Voltage Jumper,+3.3/5 Volts for P8, P4 Position
1-2 2-3
2-16
2.4.3 JP6, GPIO22/GPIO24 Select Jumper JP6 selects which signal, GPIO22 or GPIO24, to be routed to Pin 33, P8. When the 1-2 jumper position is selected GPIO22 is connected to pin 33, P8. The 2-3 selection will route GPIOI24 to Pin 33, P8. The figure below shows the connector layout on the bottom side of the board.
Figure 2-13, JP6 Layout The table below shows the functions of the two positions of JP6. Table 12: JP6, GPIO22/GPIO24 Select Position
1-2 2-3
Function
GPIO22 connected to Pin 33, P8 GPIO24 connected to Pin 33, P8 *
* default
2-17
2.5.1 Switch SW1 The eZdsp F2808 has a 6 position switch, SW1, that allows the user to configure the board for their application. The function of each position on SW1 is shown in the table below. Table 13: SW1 Switch Positions Position 1-3 4 5 6 Function Boot Mode Select Serial EEPROM WP Serial EEPROM Pullups Serial EEPROM - A1
1 SW1 2 3 4 5 6
GPIO34 GPIO29 GPIO18 Serial EEPROM WP Serial EEPROM Pullups Serial EEPROM-A1
2-18
Position 2 GPIO29
Open-1 Open-1 Closed-0 Closed-0 Open-1 Open-1 Closed-0 Closed-0
Position 1 GPIO34
Open-1 Closed-0 Open-1 Closed-0 Open-1 Closed-0 Open-1 Closed-0
Boot Mode
Flash SCI-A SPI-A I2C-A eCAN-A M0 SARAM * OTP I/O
* factory default 2.5.1.2 Switch SW1, Position 4, EEPROM Write Enable/Disable Position 4 on switch SW1 is used to enable or disable the Write Enable for the EEPROM. When position 4 is in the Closed state the Write Protect to the EEPROM is disabled, therefore allowing the EEPROM to be written. When position 4 is in the Open state the EEPROM Write Protect is enabled, not allowing the EEPROM to be written. These positions are shown in the table below. Table 15: SW1, Position 4 Position
Closed-0 * Open-1
Function
EEPROM WP Disabled (EEPROM can be written to) * EEPROM WP Enabled (EEPROM cannot be written to)
* factory default
2-19
Function
Pull up resistors used * Pull up resistors not used
* factory default 2.5.1.4 Switch SW1, Position 6, Serial EEPROM Address A1 Position 6 on switch SW1 are used to select if the address line A1 to the serial EEPROM is pulled high or low. When position 6 is in the Closed state A1 equals 1. When position 6 is in the Open state A1 equals 0. These positions are shown in the table below. Table 17: SW1, Position 6 Position
Closed-1 Open-0
Function
A1 = 1 A1 = 0 *
* factory default
2-20
SCIA/ECANA MUX Control SCIA/ECANA MUX Enable SCIB/ECANB MUX Control SCIB/ECANB MUX Enable
2-21
Color
Green Green
Controlling Signal
+5 Volts GPIO34 bit (GPIO34 high = on)
2.7 Test Points The eZdspTM F2808 has two test points. The signals they are tied to are shown in the table below. Table 20: Test Points Test Point
J1 J2
Signal
Analog Ground Ground
2-22
The schematics for the eZdspTM F2808 can be found on the CD-ROM that accompanies this board. The schematics were drawn on ORCAD.
WARNING !
The TMS320F2808 supports +3.3V Input/Output levels which are NOT +5V tolerant. Connecting the eZdsp to a system with +5V Input/Output levels will damage the TMS320F2808. If the eZdsp is connected to another target then the eZdsp must be powered up first and powered down last to prevent lactchup conditions.
A-1
A-2
REVISIONS REV DESCRIPTION DATE APPROVED
PROTOTYPES
DATE DATE
The TMS320F2808 EzDSP design is based on preliminary information(SPRS230A) for the TMS320F2808 device. This schematic is subject to change without notification. Spectrum Digital Inc. assumes no liability for applications assistance, customer product design or infringement of patents described herein.
A
SH
SPECTRUM DIGITAL
Title TMS320F2808 EzDSP USB Size B D ate:
3 2
REV
SH USED ON
REV
R ev A 1 of 7
SH
3,4,5,6,7 GND
3,4,5,6,7 AGND
U 20
96 VDD3VFL 7
3 ADCREFM 3 ADCREFP
VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 XRSn X1 X2 88 86 90 66 XCLKIN 3 1 TP 97 98 TP1 78 XRSn 6
10 42 59 68 85 93
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 ADCINA0 ADCINA1 ADCINA2 ADCINA3 ADCINA4 ADCINA5 ADCINA6 ADCINA7 ADCINB0 ADCINB1 ADCINB2 ADCINB3 ADCINB4 ADCINB5 ADCINB6 ADCINB7
ADCINA0 ADCINA1 ADCINA2 ADCINA3 ADCINA4 ADCINA5 ADCINA6 ADCINA7 ADCINB0 ADCINB1 ADCINB2 ADCINB3 ADCINB4 ADCINB5 ADCINB6 ADCINB7
23 22 21 20 19 18 17 16 27 28 29 30 31 32 33 34
2.2UF CERAMIC LOW ESR C36 1 2 R26 2 22.1K ADCREF IN TEST1 TEST2 37 36 38 24 35 ADCREFP ADCREFM ADCRESEXT ADCLO ADCREFIN XCLKIN XCLKOUT
3 VREFLO
R1 0
84 75 74 73 76 80 81
GPIO18
GPIO29
GPIO34
MODE
FLASH
MUXED ON-BOARD
VDDAIO VSSAIO
26 25 12 40 13 39 15 14
1 1 1 0 0 0 0
1 0 0 1 1 0 0
0 1 0 1
0
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 GPIO0-EPWM1A GPIO1-EPWM1B-SPISIMOD GPIO2-EPWM2A GPIO3-EPWM2B-SPISOMID GPIO4-EPWM3A GPIO5-EPWM3B-SPICLKD-ECAP1 GPIO6-EPWM4A-EPWMSYNCI-EPWMSYNCO GPIO7-EPWM4B-SPISTED-ECAP2 GPIO8-EPWM5A-CANTXB-ADCSOCAOn GPIO9-EPWM5B-SCITXB-ECAP3 GPIO10-EPWM6A-CANRXB-ADCSOCBOn GPIO11-EPWM6B-SCIRXB-ECAP4 GPIO12-TZ1n-CANTXB-SPISIMOB GPIO13-TZ2n-CANRXB-SPISOMIB GPIO14-TZ3n-SCITXB-SPICLKB GPIO15-TZ4n-SCIRXB-SPISTEB
GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15
47 44 45 48 51 53 56 58 60 61 64 70 1 95 8 9
1
0
OTP I/O
3.3V SW1 R5 R6 R8 2.2K 2.2K 2.2K 3.3V 10K SW DIP-6/SM 4.99K 4.99K I2CA1 U21 3.3V R47 R4 R3 GPIO34 R41 GPIO29 GPIO18 1 2 100K
J1
MUXED ON-BOARD
NO-POP 3 GPIO32 3 GPIO33 3 GPIO34 VDDA1.8V U29 1 IN GND OUT REF3020 1.5K VDDA3.3V 1 1 1 R81 C 37 2 0.001uF 3 2 LM4040CIM3-2.5 2 D4 R82 0 2 2 1 1 1 JP5 A B JMP-2MM 2 3 2
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 GPIO16-SPISIMOA-CANTXB-TZ5n GPIO17-SPISOMIA-CANRXB-TZ6n GPIO18-SPICLKA-SCITXB GPIO19-SPISTEA-SCIRXB GPIO20-EQEP1A-SPISIMOC-CANTXB GPIO21-EQEP1B-SPISOMIC-CANRXB GPIO22-EQEP1S-SPICLKC-SCITXB GPIO23-EQEP1I-SPISTEC-SCIRXB GPIO24-ECAP1-EQEP2A-SPISIMOB GPIO25-ECAP2-EQEP2B-SISOMIB GPIO26-ECAP3-EQEP2I-SPICLKB GPIO27-ECAP4-EQEP2S-SPISTEB GPIO28-SCIRXDA-TZ5n GPIO29-SCITXDA-TZ6n GPIO30-CANRXA GPIO31-CANTXA
GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21 GPIO22 GPIO23 GPIO24 GPIO25 GPIO26 GPIO27 GPIO28 GPIO29 GPIO30 GPIO31
50 52 54 57 63 67 71 72 83 91 99 79 92 4 6 7
VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12
2 11 41 49 55 62 69 77 87 89 94
L4
1.8V
( 1.8V )
BLM21P221SN
C58 0.1uF
C2 1uF
C56 0.001uF
TMS320F2808PZ
3.3V
L3
1 2 3 4 ADCREF IN
Analog reference is a population option: 1) U29
A0 A1 NC1 VSS
8 7 6 5
SCLA SDAA
A
( 3.3V )
R83 2.0K 1%
BLM21P221SN
0.1uF
C3 1uF
C57
DSP
Title
2) Or R81, D4, R82, R83
C38
0.1uF
R ev A 2 of 7
A-3
TMS320F2808 supports 3.3V input/output levels which are NOT 5V tolerant. Connecting the eZdsp to a system with 5V input/output levels will damage the TMS320F2808. If the eZdsp is connected to another target then the eZdsp must be powered up first and powered down last to prevent latchup conditions.
3.3V C62 1 R43 SN74AHC1G14 4 220 2 0.1uF U12 2 GPIO34 XF 3 2 1
RN13 3.3V VCC 1A 2A 3A 4A 1 15 S OE GND 4 UART_TXDA MUX_GPIO29 4 UART_RXDA MUX_GPIO28 5 CAN_TXA MUX_GPIO31 5 CAN_RXA MUX_GPIO30 4 7 9 12 8 SN74CBT3257PW U22 16
RN100K RN100K
4 3 2 1
ADCINA0 ADCINA1 ADCINA2 ADCINA3 ADCINA4 ADCINA5 ADCINA6 ADCINA7 MUX_GPIO8 R N3 RN10K 5 6 7 8 L1 R10 VREFLO 2 3.3V SW2 1 2 3 4 SW DIP-4/SM 1 2 8 7 6 5 0
1 2 3 4 5 6 7 8 9 10 0.1uF U11 4 VCC OFFn CLK 20MHz SMT/4PIN DIP GND R29 2 XCLKIN 2 C42 1 NO-POP 2 3 1 100
A-4
7 6 5 4 3 2 1
3.3V JP4
5 6 7 8
4 3 2 1
RN10
RN100K
5 6 7 8
4 3 2 1
RN11
RN100K
GPIO4 GPIO5 GPIO27 GPIO6 2 GPIO22 JP6 JUMPER3_SMT 2 GPIO7 2 GPIO16 2 GPIO18 MUX_GPIO31 MUX_GPIO11 MUX_GPIO9
5 6 7 8
4 3 2 1
RN100K
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 GPIO15 2 GPIO17 2 GPIO19 2 MUX_GPIO30 MUX_GPIO8 MUX_GPIO10 GPIO25 2 GPIO32 2 GPIO33 2 HEADER 20X2 0.1uF
P8 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
5 6 7 8
4 3 2 1
GPIO17 GPIO18 GPIO19 MUX_GPIO22 GPIO28 GPIO29 GPIO30 GPIO31 5 6 7 8 RN16 RN100K GPIO8 GPIO9 GPIO10 GPIO11 5 6 7 8 RN17 U23 VCC 4 UART_TXDB MUX_GPIO9 4 UART_RXDB MUX_GPIO11 5 CAN_TXB 5 CAN_RXB MUX_GPIO10 1A 2A 3A 4A 1 15 S OE GND 4 3 2 1 4 3 2 1 2 3 5 6 11 10 14 13 1B1 1B2 2B1 2B2 3B1 3B2 4B1 4B2
5 6 7 8
4 3 2 1
RN14
RN100K
5 6 7 8
4 3 2 1
RN15
Pullups on all F2808 GPIO pins for backward compatibility with previous eZdsp and target boards.
3.3V
P9 2 2 2 2 2 2 2 2
1 3 5 7 9 11 13 15 17 19
1 3 5 7 9 11 13 15 17 19
2 4 6 8 10 12 14 16 18 20
2 4 6 8 10 12 14 16 18 20
2 3 5 6 11 10 14 13
P5
BLM21P221SN C43 1 2
1 2 3 4 5 6 7 8 9 10
ADCINB0 2 ADCINB1 2 ADCINB2 2 ADCINB3 2 ADCINB4 2 ADCINB5 2 ADCINB6 2 ADCINB7 2 ADCREFM 2 ADCREFP 2
G ND 2,4,5,6,7
R ev A Sheet 3
1
of
3.3V
4 3 2 1
R N4 RN20K U24 5 6 7 8
SH
IDC
DSUB-F
PCRXDA PCTXDA
1 SCI-A 2 3 4 7 6
24 23 22 19 17 DIN1 DIN2 DIN3 DIN4 DIN5 DOUT1 DOUT2 DOUT3 DOUT4 DOUT5
5 6 7 10 12
1 6 2 7 3 8 4 9 5 P10 DB9F
3 3 3 3 21 20 18 16 ROUT1 ROUT2 ROUT3 ROUT1B 15 3.3V 26 0.1uF GND V+ 27 C12 0.1uF 2 C16 INVALIDn FORCEON FORCEOFFn C1+ C1C2+ C2VMAX3238CPW C15 0.1uF VCC RIN1 RIN2 RIN3 13 14 28 25 C 13 0.1uF 1 3 C14 0.1uF 4 8 9 11
5 6 8
J10
7 8 9 4
PCRXDB PCTXDB
9 10
1 3 5 7 9
2 4 6 8 10
HEADER 5X2
G ND
G ND 2,3,5,6,7
A
R ev A 4 of 7
A-5
4 3 2 1
SH
5 6 7 8
A-6
4 3 2 1
3.3V 3.3V
IDC 1 1 2 3 4 5 6 8 7 8 9 10 9 5 4 7 3 6 2
DSUB-F
R N5 RN20K U25 5 AB TXD RXD RS SN65HVD235 GND 2 P11 DB9F CANL 6 JMP-2MM C ANLA CANH 7 B A CANHA 2 1 R23 120 VCC JP3 3 CAN_TXA 3 CAN_RXA 8 4 1 3
C17 0.1uF 1 6 2 7 3 8 4 9 5
3.3V
C23 0.1uF
U27 5 AB R 24 CANHB 2 B A JMP-2MM 1 C ANLB 120 TXD RXD RS SN65HVD235 GND 2 CANL 6 CANH 7 VCC JP1 3 CAN_TXB 3 CAN_RXB 8 4 1 3
1 3 5 7 9
G ND
G ND 2,3,4,6,7
A
R ev A 5 of 7
5V
3.3V
3.3V
G ND
G ND 2,3,4,5,7
2 4 6 8 10 12 14 2 4 6 8 10 12 14 HEADER 7X2 1 3 5 7 9 11 13
1 3 5 7 9 11 13
U19 XTRSTn T_TRSTn XTMS T_TMS XTDI T_TDI XTCK T_TCK USBSEL 3.3V XRSn 2 C70 22nF
IF U13 IS INSTALLED THEN REMOVE R49 AND R48.
Locate R7,R54, C70 at the DSP XRSn pin for best EMI/ESD noise immunity.
3.3V
XRSn is logical AND of PONRSnIN and emulator controlled reset. Power on default is PONRnIN controls XRSn.
2 3 5 6 11 10 14 13
C28_TDI 2 C28_TCK 2
R7 1.5K
100
USBSEL - HIGH, SELECT USB EMULATION USBSEL - LOW, SELECT XDS EMULATION
C4 2 5 1 22pF
DSP_RSn
To/from expansion header
USB1
DSP_RS_OUT_ODn
3.3V
R19
33 C28_TDO 2 C28_EMU0 2
RESET_INn
3.3V
C28_EMU1 2
R ev A 6 of 7
A-7
CENTER SHUNT SLEEVE CT2 47uF 2 0.1uF CT3 22uF R45 1 2 3.3V 17 18 19 1 C63
+
2 2
D S1 LTST-C150GKT G REEN C65 10 1 2 0.1uF 9 2GND CT4 22uF 0.1uF R52 2 0 3.3V 1 1 C1 1uF 2 2EN 2OUTA 2OUTB 2SENSE 11 12 2INA 2INB 2RESET 22
Optional power sequence R53 29 1.5K 1% TPS767D301 Q3 BSS138 S R9 0 R2 10K 1 TIE TPS767D301 POWER PAD TO GND PLANE (TI-SLMA002) 2 2 G 1 R34 2.0K 1% 2 D
THERMAL_PAD
3.3V
B
CT6 22uF
CT5 22uF
C19 0.1uF
C 18 0.1uF
C5 0.1uF
C8 0.1uF
C21 0.1uF
C41 0.1uF
C40 0.1uF
C61 0.1uF
A-8
1OUTA 1OUTB 1FB/SENSE 30.1K, 1% 2 23 24 25 1 2 7 8 13 14 NC12 NC11 NC10 NC9 NC8 NC7 15 16 20 21 26 27 VDD3VFL 2 C7 0.1uF
C
P6
RASM712
R 44 220
+5V Max
PONRSnIN
CT1 22uF C20 0.1uF C6 0.1uF C9 0.1uF C39 0.1uF C60 0.1uF
J2
R ev A 7 of 7
This appendix contains the mechanical information about the socketed and unsocketed versions of the eZdspTM F2808
B-1
B-2
B-3
B-4