Structural description in VHDL.

MSc Heiner Castro

Netlist
Un diseo complejo normalmente consta de varias descripciones ms pequeas (bloques funcionales). Estos bloques funcionales son mapeados en la descripcin principal. Ayudan a crear jerarquas de diseo y hacer ms claras las descripciones. Tambin facilitan la simulacin y la deteccin de errores.

Example: using Netlist.

Describir una ALU con las funciones que muestra la siguiente tabla:

ALU structure

Cortesy of SynthWorks & ALDEC

Netlist example: Optimal ALU

entity Optimal_ALU is port (A,B,C,D,E,F,G,H: in std_logic_vector (7 downto 0); opsel: in std_logic_vector (1 downto 0); Z: out std_logic_vector (7 downto 0)); end Optimal_ALU; architecture netlist of Optimal_ALU is --Signal declarative signal muxout1, muxout2: std_logic_vector (7 downto 0); --Component declarative component mux is generic (n: NATURAL :=8); port (x1, x2, x3, x4: std_logic_vector (n-1 downto 0); s: in std_logic_vector(1 downto 0);

Netlist example: Optimal ALU

--Component declarative (continuacin) component nBitAdder is generic (n: NATURAL :=4); Port (A,B: in std_logic_vector (n-1 downto 0); Cin: in std_logic; Sum: out std_logic_vector (n-1 downto 0); Cout: out std_logic); end component nBitAdder; -- fin de la declaracin de componentes Begin First_Mux: mux port map (A,C,E,G,opsel,muxout1); Second_Mux: mux port map (B,D,F,H,opsel,muxout2); addition: nBitAdder generic map (8) port map (muxout1,muxout2,0,Z, open); -- se pudo haber escrito tambin Z <= muxout1+muxout2; end netlist;

VHDL for simulation

Los Netlist son usados para simular sistemas descritos en HDL. En VHDL las descripciones para simulacin (testbench) no son necesariamente sintetizables. En un testbench en VHDL la entidad debe estar vaca. En la arquitectura se debe describir el comportamiento de las entradas del sistema que se quieran simular.

Testbench example: Full adder

Para simular un bloque combinacional en general deben probarse todas las combinaciones posibles.

Testbench example: Full adder

ENTITY Testbench1 IS END Testbench1; ARCHITECTURE behavior OF Testbench1 IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT FullAdder PORT( A, B, Ci : IN std_logic; S, Co : OUT std_logic); END COMPONENT; --Inputs signal In1, In2, CarryIn : std_logic := '0'; --Outputs signal Total, CarryOut : std_logic;

Testbench ejemplo: Full adder

BEGIN -- Instantiate the Unit Under Test (UUT) uut: FullAdder PORT MAP (A => In1, B => In2, Cin => CarryIn, S => Total, Co => CarryOut); In1<= '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '1' after 50 ns, '0' after 60 ns, '1' after 70 ns; In2<= '1' after 20 ns, '0' after 40 ns, '1' after 60 ns; CarryIn<= '1' after 40 ns; END;

Testbench simulation results

Testbench example: Multiplexer

Para sistemas digitales con numerosas entradas simular todas las combinaciones puede consumir mucho tiempo y esfuerzo. En algunas ocasiones simular todas las entradas no aporta informacin importante. As que en ocasiones solo es necesario simular pocas entradas. Lo importante es simular la funcionalidad del dispositivo. Ejemplo: en el caso del multiplexor es necesario simular todas las combinaciones del selector y pocos datos en las entradas de datos.

Testbench example: Multiplexer

library IEEE; use IEEE.std_logic_1164.all, IEEE.STD_LOGIC_UNSIGNED.all; ENTITY Testbench1 IS END Testbench1; ARCHITECTURE behavior OF Testbench1 IS -- Component Declaration for the Unit Under Test (UUT)

component mux is generic (n: NATURAL :=8); port (x1, x2, x3, x4: in std_logic_vector (n-1downto 0); s: in std_logic_vector(1 downto 0); f: out std_logic_vector (n-1 downto 0)); end component mux;

Testbench example: Multiplexer

--Signal declaration --inputs signal A,B,C,D : std_logic_vector (7 downto 0) := (others => 0); signal S : std_logic_vector (1 downto 0) := (others => 0); --ouputs signal Y : std_logic_vector (7 downto 0); BEGIN -- Instantiate the Unit Under Test (UUT) uut: mux generic map (8) port map (x1=>A, x2=>B, x3=>C, x4=>D, s =>S, f=>Y); A <= "00001010" after 5 ns, "10001010" after 40 ns; B <= "00001011" after 5 ns, "01001011" after 40 ns; C <= "00001100" after 5 ns, "00101100" after 40 ns; D <= "00001101" after 5 ns, "00011101" after 40 ns; S <= "01" after 10 ns, "10" after 20 ns, "11" after 30 ns,

Testbench simulation results