CMOS Inverter

Outline
Quantification of Design Metrics of an inverter
Static (or Steady-State) Behavior SteadyDynamic (or Transient Response) Behavior Energy Efficiency

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CMOS Inverter

For velocity saturated device

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CMOS Inverter

Estimation of NM USING Piecewise lin. approx.

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CMOS Inverter

Determine g at Vin~Vm

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CMOS Inverter

Switching Threshold
At VM where Vin = Vout, both PMOS and NMOS transistors are in saturation (since VDS = VGS)
VM rVDD/(1 + r) where r = kpVDSATp/knVDSATn /(1

Switching threshold set by the ratio r, which compares the relative driving strengths of the PMOS and NMOS transistors Goal: Goal: To set VM = VDD/2 (to maximize noise margins), so r 1 (W L)p k n 'VDSAT ,n (VM VT ,n VDSAT ,n /2) =
(W L)n
k p 'VDSAT , p VDD ( M VT , p VDSAT , p /2) V
CMOS Inverter

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Switch Threshold Example

In our generic 0.25 micron CMOS process, using the process parameters from Table 3.2, at VDD = 2.5V, and a minimum size NMOS device ((W/L)n of 1.5)
VT0(V) NMOS PMOS 0.43 -0.4 (V0.5) 0.4 -0.4 VDSAT(V) 0.63 -1 k(A/V2) 115 x 10-6 -30 x 10-6 (V-1) 0.06 -0.1

(W/L)p 115 x 10-6 0.63 (1.25 0.43 0.63/2)

= x x

(W/L)n -30 x

10-6

-1.0

(1.25 0.4 1.0/2)

= 3.5

(W/L)p = 3.5 x 1.5 = 5.25 for a VM of 1.25 V

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CMOS Inverter

Example: Simulated Results

1.8 1.7 1.6 1.5 1.4

V (V)

1.3 1.2 1.1 1 0.9 0.8

1.25 V

r = 3.4
10
0

10

W p /W n

Minimum Width-to-Length = 1.5 Width-toNitin Chaturvedi

CMOS Inverter

Observations I
VM is relatively insensitive to variations in device ratio
Small Variations of the ratio do not significantly disturb VTC. Common Industry Practice to set Wp smaller than the requirement.

Increasing the width of the PMOS moves VM towards VDD Increasing the width of the NMOS moves VM toward GND
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CMOS Inverter

Noise Margins: Determining VIH and VIL

3
VOH = VDD

By definition, VIH and VIL are where gain dVout/dVin = -1

Gain g = Slope NMH = VDD - VIH NML = VIL - GND

VM

1
Slope = g VOL = GND

Approximating: VIH = VM - VM /g VIL = VM + (VDD - VM )/g

0 VIL VIL
VIH Vin VIH

A piece-wise linear approximation of VTC pieceNitin Chaturvedi

So high gain in the transition region is very desirable

CMOS Inverter

CMOS Voltage Gain

Vin
0 0 -2 -4 -6 -8 -10 -12 -14 -16 -18 0.5 1 1.5 2

Gain is a strong function of the slopes of the currents in the saturation region, for Vin = VM

Determined only by technology parameters, especially channel length modulation (). Only designer influence through supply voltage and VM (transistor sizing).
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CMOS Inverter

Example: VTC and Noise Margin

For a 0.25m, (W/L)p/(W/L)n = 3.4, (W/L)n = 1.5 (min size) VDD = 2.5V
VM 1.25 V, g = -27.5 27. VIL = 1.2 V, VIH = 1.3 V NML = NMH = 1.2 Real Value VIL = 1.03 V, VIH = 1.45 V NML = 1.03, NMH = 1.05 03,

Output resistance Sensitivity of gate output with respect to noise lowlow-output = 2.4 k highhigh-output = 3.3 k
Preferably as low as possible
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CMOS Inverter

Observations II
First-Order Analysis overestimates the gain
Max. gain only 17 at VM VIL = 1.17V, VIH = 1.33V 17V 33V

Piecewise Linear Approximation is too overly optimistic

Major contributor to deviation from the true gain

CMOS inverter is a poor analog amplifier!

One of the major differences between analog and digital designs is that digital circuits operate in the regions of extreme nonlinearity nonlinearity.
Well-defined and well-separated high and low signals
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CMOS Inverter

Impact of Process Variation on VTC

2.5 2 Vout(V) 1.5 1 0.5 0 0 0.5 1 1.5 Vin(V) 2 2.5
Bad PMOS Good NMOS Good PMOS Bad NMOS

Process variations (mostly) cause a shift in the switching threshold

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CMOS Inverter

Scaling the Supply Voltage

2.5

0.2

0.15
1.5

0.1
1 0.5

0.05

0 0 0.5 1 1.5 2 2.5

0 0 0.05 0.1 0.15 0.2

Vin(V)

Gain=-1

Vin(V)

Reducing VDD improves Gain

But it deteriorates for very low VDD

Practical Lower Bound: VDDmin > 2 to 4 kt /q

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CMOS Inverter

Observations III
Reducing the supply voltage has a positive impact on the energy dissipation
But is also detrimental to the delay of the gate

DC Characteristic becomes increasingly sensitive to device variations once supply and intrinsic voltages become comparable Scaling the supply voltage = reducing the swing
Reduce internal noise (e.g., crosstalk) More susceptible to external noise that do not scale
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CMOS Inverter

Inverter Switching Charaterisitcs Dynamic Behavior

Delay Definitions (Propagation delay)

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CMOS Inverter

Delay Definitions- Rise and Fall time Definitions-

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CMOS Inverter

Delay Definitions-with input slope DefinitionsV in

50% t V out tpHL tpLH 90% 50% 10% tf

CMOS Inverter

t tr

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CMOS Inverter Dynamic Behavior

Transient behavior of the gate is determined by the time it takes to charge and discharge the load capacitance, CL, through on-transistors
Delay is a function of load capacitances and transistor on-resistances

Getting CL as small as possible is crucial to the realization of high-performance CMOS circuits

Transistor Capacitances Wire Capacitances Fanout

Wire Resistances also become more important.

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CMOS Inverter

Computing the Capacitances

VDD M2 Vin Cgd12 Cdb2 Vout Cg4 M4 Vout2

Extrinsic

VDD

Cdb1 M1

Cw

Cg3

M3

Intrinsic

Interconnect

Fanout Vout

Vin

CL Simplified Model
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Vout2 out2

CMOS Inverter

Finding Cgd: The Miller Effect

M1 and M2 are either in cut-off or in saturation. The floating gate-drain capacitor is replaced by a capacitance-to-ground (gate-bulk capacitor).
V
Vin
M1

Cgd1 gd1

Vout

Vout
V

2Cgd1 gd1 Vin

M1

A capacitor experiencing identical but opposite voltage swings at both its terminals can be replaced by a capacitor to ground whose value is two times the original value
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CMOS Inverter

Clock charge feed through

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CMOS Inverter

Diffusion Capacitances: Cdb1 and Cdb2 db1 db2

We can simplify the diffusion capacitance calculations by using a Keq to linearize the nonlinear capacitor to the value of the junction capacitance under zero-bias Ceq = Keq Cj0
0.25 m Process

high-tohigh-to-low Keqbp 0.57 0.79 Keqsw 0.61 0.86

CMOS Inverter

low-to-high low-toKeqbp 0.79 0.59 Keqsw 0.81 0.7

NMOS PMOS
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Extrinsic Capacitances: Cg3 and Cg4

Simplification of the actual situation
Assumes all the components of Cgate are between Vout and GND (or VDD) Assumes the channel capacitances of the loading gates are constant

The extrinsic, or fan-out, capacitance is the total gate capacitance of the loading gates M3 and M4.
Cfan-out = Cgate(NMOS) + Cgate(PMOS) fan= (CGSOn+ CGDOn+ WnLnCox) + (CGSOp+ CGDOp+ WpLpCox) (C (C
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CMOS Inverter

Example: Layout of Two Inverters

PMOS 1.125/0.25 125/ VDD AD = Drain Area PD = Drain Perimeter AS = Source Area PS = Source Perimeter

In
Polysilicon

Out
Metal1 Metal1

= 0.125
GND

NMOS 0.375/0.25

Minimum Drawn Length

0.25 m NMOS PMOS

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W/L 0.375/0.25 1.125/0.25

AD (m2) 0.3 0.7

PD (m) 1.875 2.375

AS (m2) 0.3 0.7

PS (m) 1.875 2.375

CMOS Inverter

Example: Components of CL (0.25 m)

C Term Expression 2 Cgd0n Wn 2 Cgd0p Wp KeqbpnADnCj + KeqswnPDnCjsw KeqbppADpCj + KeqswpPDpCjsw (2 Cgd0n)Wn + CoxWnLn (2 Cgd0p)Wp + CoxWpLp from extraction
CMOS Inverter

Value (fF) HL 0.23 0.61 0.66 1.5 0.76 2.28 0.12

Value (fF) L H 0.23 0.61 0.90 1.15 0.76 2.28 0.12

Cgd1 gd1 Cgd2 gd2 Cdb1 db1 Cdb2 db2 Cg3 Cg4 Cw CL
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6.1

6.0

Wiring Capacitance
The wiring capacitance depends upon the length and width of the connecting wires and is a function of the fan-out from the driving gate and the number of fan-out gates. Wiring capacitance is growing in importance with the scaling of technology.

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CMOS Inverter

Delay calculation method 1

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CMOS Inverter

Switch Model of CMOS Transistor Model-1 ModelApproximate as a simple RC network Where, R is given as an equivalent resistance of the NMOS and PMOS devices C is given as the total lumped Cload capacitance

|V

G S|

R on

|V G S | < | V T |
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|V G S | > |V T |

CMOS Inverter

CMOS Inverter: Transient Response

Switch model

Vout = VDD (1 e t / RONCL )

VDD

Vout = VDD (e t / RONCL )

tpHL = f(Ron.CL) = 0.69 RonCL

Vout Vout CL Ron

1

ln(0.5)

VDD

0.5 0.36

Vin = V DD RonCL
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CMOS Inverter

Inverter Propagation Delay

Propagation delay is proportional to the time-constant of the timenetwork formed by the on-resistance and the load capacitance onVDD

tp = f(Ron, CL)
Charge
Vout CL Low to High

VDD

Rp

tpLH = 0.69 Reqp CL tpHL = 0.69 Reqn CL

Discharge
Vout Rn CL High to Low

tp =

t pHL + t pLH 2

Vin = 0

Reqn + Reqp = 0.69C L 2

Vin = V DD

To equalize rise and fall times make the on-resistance of the NMOS and PMOS approximately equal.
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CMOS Inverter

Determination of Req

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CMOS Inverter

In velocity saturated device

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CMOS Inverter

CMOS Inverter Driving a Lumped Capacitance Load

CMOS Inverter can be viewed as a single transistor either charging the Cload or discharging the Cload Vin is assumed to switch abruptly If Vin switches high, the NMOS Tx discharges Cload while the PMOS Tx turns OFF If Vin switches low, the PMOS Tx charges Cload while the NMOS Tx turns OFF Cload is comprised of Cgate due to the gate capacitance of receiving circuits Cwire of the interconnect metal Cparasitics of the inverter output junctions
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CMOS Inverter

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CMOS Inverter

Inverter Transient Response (0.25 m)

Simulation
3 2.5 2 1.5 1 0.5 0 -0.5 0 50 100 150 200 250

Analysis
VDD= 2.5V W/Ln = 1.5 W/Lp = 4.5 Reqn= 13 k /1.5 Reqp= 31 k /4.5 tpHL = 36 psec tpLH = 29 psec tp = (36+29)/2 (36+29)/2 = 32.5 psec 32.

tpLH

tpHL

t(psec)

tpHL = 39.9 psec and tpLH = 31.7 psec 39. 31.

Analysis results is too optimistic ~ 10% better 10%

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CMOS Inverter

Inverter Propagation Delay, Revisited

To see how a designer can optimize the delay of a gate, we have to expand Req in the delay equation.
5.5 5 4.5 4 3.5 3 2.5 2 1.5 1 0.8 1 1.2 1.4 1.6 1.8 2

tpHL = 0.69 Reqn CL = 0.69(3CVDD)/(4IDSATn) 69( )/(4

t p (n o r m a liz e d )

t pHL

CL 0.52 (W L)n knVDSATn

2.2

2.4

VDD(V)
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CMOS Inverter

Delay as a function of VDD

5.5 5 4.5 4

t (normalized)

3.5 3 2.5 2 1.5 1 0.8

t pHL

CL 0.52 (W L)n knVDSATn

1.2

1.4

1.6

1.8

2.2

2.4

V
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DD

(V)

CMOS Inverter

Minimizing Propagation Delay

Reduce CL
Keep the drain diffusion as small as possible

Increase W/L ratio of the transistor

Most powerful and effective way Watch out for self-loading self-loading!
When the intrinsic capacitance dominates

Increase VDD
Trade off energy efficiency for performance Very minimal improvement above a certain level Reliability concerns enforce a firm upper bound on VDD
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CMOS Inverter

PMOS-toPMOS-to-NMOS Ratio
So far PMOS and NMOS have been sized such that their Reqs match (ratio of 3 to 3.5)
symmetrical VTC equal high-to-low and low-to-high propagation delays

If speed is the only concern, reduce the width of the PMOS device!
widening the PMOS degrades the tpHL due to larger parasitic capacitance
= (W/L)p/(W/L)n (W /(W
opt
CW = r1+ C +C dn 2 Cgn 2

r = Reqp/Reqn resistance ratio of identically-sized PMOS and NMOS

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CMOS Inverter

Method 2
AVERAGE CURRENT THROUGH LOAD

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CMOS Inverter

CMOS Inverter Propagation Delay

V DD

t pHL = C

(V 50% -VDD) Iav

Vout

Iav

CL

tpLH = C L (V50%-VOL) Iav

Vin = V DD
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CMOS Inverter

Average Current Calculations

Iav, HL = [ic(VIN=VOH, VOUT= VOH)]+ ic(VIN=VOH, VOUT= V50%)]

Iav, LH = [ic(VIN=VOL, VOUT= V50%)]+ ic(VIN=VOL, VOUT= VOL)]

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CMOS Inverter

Method is Simple

Drawback------neglects variation of capacitance load during the entire simulation

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CMOS Inverter

MethodMethod-3 Differential equation approach

accurate

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CMOS Inverter

Propagation delay times can be found more accurately By solving the state equations associated with the output node Differential equation associated with output node

Capacitance current is function of output voltage

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CMOS Inverter

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CMOS Inverter

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CMOS Inverter

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CMOS Inverter

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CMOS Inverter

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CMOS Inverter

tpHL

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CMOS Inverter

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CMOS Inverter

tpLH

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CMOS Inverter

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CMOS Inverter

Impact of Rise Time on Delay

0.35

0.3 tpHL(nsec) (

0.25

0.2

0.15

0.2

0.4 0.6 trise (nsec)

0.8

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CMOS Inverter

Consider Input slope

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CMOS Inverter

Design for Performance-(speed) PerformanceKeep capacitances small Increase transistor sizes

watch out for self-loading!

Increase VDD

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CMOS Inverter

Power Consumption

Where Does Power Go?

Static Power Consumption
Ideally zero for static CMOS but in the real world.. Leakage Current Loss
Diodes and Transistors constantly losing charge

Dynamic Power Consumption

Charging/Discharging Capacitances
Major Source of Power Dissipation in CMOS Circuits

DirectDirect-Path Current Loss

Short circuit between Power Rail during Switching
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CMOS Inverter

Dynamic Power Consumption

VDD iVDD(t)

Vin

Vout CL

Energy Supplied/Cycle =

i
0

VDD

(t)VDD dt

= CL * VDD2 = CL * VDD2 / 2

Energy Stored/Cycle =

i
0

VDD

(t)v out (t)dt

Pdyn = Energy/cycle * fclk = CL * VDD2 * fclk

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CMOS Inverter

Switching Activity
Power dissipation does not depend on the size of the devices but depends on how often the circuit is switched.
Switching Activity frequency of energy-consuming transition = f 01
Clock

Pdyn = CL * VDD2 * f 01
Gate output

= CL * VDD2 * P01 * fclk = Ceff * VDD2 * fclk

P01 = 0.25, 25,

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f01 = fclk / 4

Effective Capacitance Ceff = Average Capacitance Switched per clock cycle

CMOS Inverter

Example: Power Dissipation of an IC

Consider a 0.25 micron chip, 500 MHz clock, average load cap of 15fF/gate (for fanout of 4), 2.5V supply.
Dynamic Power consumption per gate is
Pdyn = Ceff * VDD2 * fclk = 15 fF * (2.5 V)2 * 500 MHz ~ 47 W

With 1 million gates and a switching activity of 25%

Dynamic Power of the entire chip is
Pchip = Pdyn * Ng * Pa (Ng = no. of gates) = 47 W/gate * 106 gates * 0.25 = 11.75 W ~ 12 W 11.
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CMOS Inverter

Lowering Dynamic Power

Lowering Physical Capacitance Capacitance: Function of fan-out, wire length, transistor sizes Quadratic Effect Supply Voltage: Has been dropping with successive generations

Pdyn = CL VDD2 P01 f

Activity factor: How often, on average, do gates switch? Reduction can be obtained only at Logic and Architectural Abstraction Levels
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Clock frequency: Increasing

CMOS Inverter

Short Circuit Power Consumption

VDD
tsc

Isc Vin CL Vout

Finite slope of the input signal causes a direct current path between VDD and GND for a short period of time during switching when both the NMOS and PMOS transistors are conducting (active).
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CMOS Inverter

Short Circuit Currents Determinates

Esc = tsc VDD Ipeak P01 Psc = tsc VDD Ipeak f01
tsc = Duration of the slope of the input signal
Ipeak determined by
the saturation current of the PMOS and NMOS transistors which depend on their sizes, process technology, temperature, etc. strong function of the ratio between input and output slopes
a function of CL
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CMOS Inverter

Impact of CL on Psc
VDD Isc 0 Vin Vout CL Vin VDD Isc Imax Vout CL

Large capacitive load Output fall time significantly larger than input rise time.
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Small capacitive load Output fall time substantially smaller than input rise time.

CMOS Inverter

Ipeak as a Function of CL
x 10-4
2.5

CL = 20 fF
2 1.5 1 0.5 0 0 -0.5 2 4

When load capacitance is small, Ipeak is large. Short circuit dissipation is minimized by matching the rise/fall times of the input and output signals - slope engineering. engineering

CL = 100 fF CL = 500 fF

6 x 10-10

time (sec) 500 psec input slope

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CMOS Inverter

Psc as a Function of Rise/Fall Times

8 7 6 5 4 3 2 1 0 0 1 2 3 4 5

VDD= 3.3 V

When load capacitance is small (tsin/tsout > 2 for VDD > 2V) the power is dominated by Psc If VDD < VTn + |VTp| then |V Psc is eliminated since both devices are never on at the same time time.
normalized wrt zero input riserise-time dissipation
CMOS Inverter

VDD = 2.5 V VDD = 1.5V

tsin/tsout
W/Lp = 1.125 m/0.25 m m/0 W/Ln = 0.375 m/0.25 m m/0 CL = 30 fF
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Static (Leakage) Power Consumption

VDD VDD Vout = VDD

Pstat= VDD Istat

dominant factor.

Drain junction leakage Gate leakage SubSub-threshold current

All leakages increase exponentially with temperature

Junction leakage doubles every 9C

Sub-threshold current becomes more concern in vDSM

The closer the threshold voltage to zero, the larger the leakage current at VGS = 0V (when NMOS off)
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CMOS Inverter

Leakage as a Function of VT
Continued scaling of supply voltage and the subsequent scaling of threshold voltage will make sub-threshold conduction a dominant component of power dissipation.
1.E-02

1.E-04

I D (A )

1.E-06

1.E-08 VT=0.4V VT=0.1V

1.E-10

An 90mV/decade VT 90mV/decade rollroll-off - so each 255mV 255mV increase in VT gives 3 orders of magnitude reduction in leakage (but adversely affects performance)
1

1.E-12 0 0.2 0.4 0.6 0.8

VGS (V)
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CMOS Inverter

TSMC Processes Leakage and VT

From MPR, June 2000, pp. 19 Performance of various TSMC processes 2000, (G generic, LP low power, ULP ultra low power, HS high speed) generic, power, power, speed) CL018 CL018 G Vdd Tox (effective) Lgate IDSat (n/p) (A/m) Ioff (leakage) (A/m) VTn FET Perf. (GHz)
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CL018 CL018 LP 1.8 V 42 0.16 m 500/ 500/180 1.60 0.63 V 22

CL018 CL018 ULP 1.8 V 42 0.18 m 320/ 320/130 0.15 0.73 V 14

CL018 CL018 HS 2V 42 0.13 m 780/ 780/360 300 0.40 V 43

CL015 CL015 HS 1.5 V 29 0.11 m 860/ 860/370 1,800 0.29 V 52

CL013 CL013 HS 1.2 V 24 0.08 m 920/ 920/400 13,000 13, 0.25 V 80

1.8 V 42 0.16 m 600/ 600/260 20 0.42 V 30

CMOS Inverter

Exponential Increase in Leakages

10000

Leakage currents double every 10 degree increase in temperature

0.10 m 0.13 m 0.18 m 0.25 m

1000

100

10

1 30 40 50 60 70 80 90 100 110 Temperature (C)

The Leakage Power is six orders of magnitude smaller than the dynamic power (at room temperature)
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CMOS Inverter

Energy and Power Equations

E = CL VDD2 P01 + tsc VDD Ipeak P01 + VDD IleakageTclock
f01 = P01 * fclock

P = CL VDD2 f01 + tsc VDD Ipeak f01 + VDD Ileakage

Dynamic power (~90% today and (~90% decreasing relatively) ShortShort-circuit power (~8% today and (~8 decreasing absolutely) Leakage power (~2% today and (~2 increasing)

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CMOS Inverter

PowerPower-Delay and Energy-Delay Product EnergyPowerPower-delay product (PDP) = Pav * tp = (CLVDD2)/2 (C )/2
PDP is the average energy consumed per switching event (Watts * sec = Joule) Lower power design could simply be a slower design

EnergyEnergy-delay product (EDP) = PDP * tp = Pav * tp2

EDP is the average energy consumed multiplied by the computation time required Takes into account that one can trade increased delay for lower energy/operation (e.g., via supply voltage scaling that increases delay, but decreases energy consumption)
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CMOS Inverter

EnergyEnergy-Delay Plot
15 10 5
Energy Delay
1 .1 V 0.25 micron

EnergyEnergy-Delay

EDP =

2(VDD VTE )

2 3 CLVDD

Where VTE = VT+VDSAT/2

VDDopt

0 0.5

3 = VTE 2

1.5 V (V) dd

2.5

VTE (VTn +| VTp |)/2 = 0.8 V (V |)/2 VDDopt = (3/2)*0.8 = 1.2 V (3 )*0

VTn = 0.43 V, VDSATn = 0.63 V, VTEn = 0.74 V VTp = -0.4 V, VDSATp = -1 V, VTEp = -0.9 V
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CMOS Inverter

Observation VI
Voltage Dependence of the EDP
Higher Supply Voltages reduce delay, but harm the energy. Vice Versa for low voltages

VDDopt simultaneously optimizes performance (delay) and energy

For submicron technologies with VT in the range of 0.5 V, VDDopt ~ 1V.

VDDopt does not necessarily represent the optimum voltage for a given design problem
Goal of the design (speed or power) determinates the supply voltage
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CMOS Inverter

END

Some Interesting Questions

What will cause this model to break? When will it break? Will the model gradually slow down?
Power and power density Leakage Process Variation

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CMOS Inverter