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ECE357: Introduction to VLSI CAD

Electrical Engineering & Computer Science Northwestern University

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Prof. Hai Zhou

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Logistics
Time & Location: MWF 11-11:50 TECH L160

Instructor: Hai Zhou haizhou@ece.northwestern.edu Oce: L461 Oce Hours: W 3-5P

Teaching Assistant: Chuan Lin Texts: VLSI Physical Design Automation: Theory & Practice, Sait & Youssef, World Scientic, 1999. Reference:
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An Introduction to VLSI Physical Design, Sarrafzadeh & Wong, McGraw Hill, 1996. Grading: Participation-10% Project-30% Midterm-30% Homework-30% Homework must be turned in before class on each due date, late: -40% per day Course homepage: www.ece.northwestern.edu/~haizhou/ece357

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What can you expect from the course

Understand modern VLSI design ows (but not the details of tools) Understand the physical design problem

Familiar with the stages and basic algorithms in physical design Improve your capability to design algorithms to solve problems Improve your capability to think and reason
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What do I expect from you

Active and critical participation

speed me up or slow me down if my pace mismatches yours Your role is not one of sponges, but one of whetstones; only then the spark of intellectual excitement can continue to jump over Read the textbook

Do your homeworks You can discuss homework with your classmates, but need to write down solutions independently
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VLSI (Very Large Scale Integrated) chips

VLSI chips are everywhere computers

commercial electronics: TV sets, DVD, VCR, ... voice and data communication networks automobiles

VLSI chips are artifacts they are produced according to our will ...

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Design: the most challenging human activity

Design is a process of creating a structure to fulll a requirement Brain power is the scarcest resource Delegate as much as possible to computersCAD Avoid two extreme views:

Everything manual: impossiblemillions of gates Everything computer: impossible either

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Design is always dicult

A main task of a designer is to manage complexity Silicon complexity: physical eects no longer be ignored resistive and cross-coupled interconnects; signal integrity; weak and faster gates reliability; manufacturability System complexity: more functionality in less time gap between design and fabrication capabilities desire for system-on-chip (SOC)
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CAD: A tale of two designs

Targethardware design

How to create a structure on silicon to implement a function Aidsoftware design (programming) How to create an algorithm to solve a design problem Be conscious of their similarities and dierences

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Emphasis of the course

Design ow

Understand how design process is decomposed into many stages What are the problems need to be solved in each stage Algorithms

Understand how an algorithm solves a design problem Consider the possibility to extend it Be conscious and try to improve problem solving skills
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Basics of MOS Devices

The most popular VLSI technology: MOS (Metal-Oxide-Semiconductor).

CMOS (Complementary MOS) dominates nMOS and pMOS, due to CMOSs lower power dissipation, high regularity, etc. Physical structure of MOS transistors and their schematic icons: nMOS, pMOS. Layout of basic devices: CMOS inverter CMOS NAND gate CMOS NOR gate
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MOS Transistors gate

drain source conductor (polysilicon) insulator (SiO2) drain n n gate

psubstrate ntransistor

diffusion

The nMOS switch passes "0" well.

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drain p

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source p

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drain

substrate

schematic icon

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gate

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conductor (polysilicon) insulator (SiO2)

source substrate

nsubstrate ptransistor

diffusion

schematic icon

The pMOS switch passes "1" well.

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A CMOS Inverter
Metal VDD Polysilicon Metaldiffusion contact pMOS transistor

nMOS transistor

GND

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B Diffusion

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VDD B

A 1 0

B 0 1

pchannel (pMOS)

nchannel (nMOS) GND

layout
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A CMOS NAND Gate

Metal VDD Diffusion Polysilicon C A

GND

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B

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A 0 0 1 1

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VDD

B C 0 1 1 1 0 1 1 0

C
B

GND

layout
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A CMOS NOR Gate

Metal VDD Polysilicon

GND

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B Diffusion

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A 0 0 1 1

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VDD

B C 0 1 1 0 0 0 1 0

GND

layout
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Current VLSI design phases

Synthesis (i.e. specication implementation)

1. High level synthesis (459 VLSI Algorithmics) 2. Logic synthesis (459 VLSI Algorithmics) 3. Physical design (This course)

Analysis (implementation semantics) Verication (design verication, implementation verication) Analysis (timing, function, noise, etc.) Design rule checking, LVS (Layout Vs. Schematic)
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Physical Design
Physical design converts a structural description into a geometric description. Physical design cycle: 1. Circuit partitioning 2. Floorplanning

3. placement, and pin assignment 4. Routing (global and detailed) 5. Compaction

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Design Styles
Issues of VLSI circuits

Performance

Area

Full custom

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Cost

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Different design styles

Standard cell

Gate array

FPGA

CPLD

SPLD

SSI

Performance, Area efficiency, Cost, Flexibility

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Full Custom Design Style

Data path PLA

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pins

ROM/RAM

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Controller

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I/O

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via (contact)

overthecell routing

A/D converter

Random logic

I/O pads

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Standard Cell Design Style

D A C B

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A B Cell B

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library cells
Cell A

Cell C

Cell D

Feedthrough Cell

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Gate Array Design Style

I/O pads

pins

prefabricated transistor array

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customized wiring

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FPGA Design Style

logic blocks

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routing tracks

switches Prefabricated all chip components

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SSI/SPLD Design Style

x1 y1 x2 y2 x3 y3 x4 y4
74LS86 x1 y1
Vcc

74LS02
Vcc

74LS00

Vcc

x3 y3

x2 y2

GND

F=

4 i=1

xi

yi

(a) 4bit comparator.

x1 y1 x2 y2 x3

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x4 y4

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y4
GND

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x3 y3 x4 y4

(b) SSI implementation.

AND array
x1 y1 x2 y2

OR array

(c) SPLD (PLA) implementation.

(d) Gate array implementation.

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Comparisons of Design Styles

Cell size Cell type Cell placement Interconnections Full custom variable variable variable variable Standard cell xed height variable in row variable

* Uneven height cells are also used.

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Gate array xed xed xed variable

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SPLD xed programmable xed programmable

FPGA xed programmable xed programmable

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Comparisons of Design Styles

Fabrication time Packing density Unit cost in large quantity Unit cost in small quantity Easy design and simulation Easy design change Accuracy of timing simulation Chip speed + desirable not desirable Full custom +++ +++ +++

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Standard cell ++ ++ ++

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Gate array + + + + +

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FPGA +++ +++ ++ ++ +

SPLD ++ + + ++ +

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Design-Style Trade-os
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4

10

10 Turnaround Time (Days) 10

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SPLDs 10
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semi custom

Full custom

FPGAs

SSIs 10
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optimal solution

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10

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Logic Capacity (Gates)

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Algorithms 101

Algorithm: a nite step-by-step procedure to solve a problem Requirements:

Unambiguity: can even be followed by a machine Basic: each step is among a given primitives Finite: it will terminate for every possible input

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A game

An ECE major is sitting on the Northwestern beach and gets thirsty, she knows that there is an ice-cream booth along the shore of Lake Michigan but does not know wherenot even north or south. How can she nd the booth in the shortest distance?

Primitives: walking a distance, turning around, etc.

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A rst solution

Select a direction, say north, and keep going until nd the booth

Suppose the booth is to the south, she will never stop... of course, with the assumption she follows a straight line, not lake shore or on earth

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Another solution
Set the place she is sitting as the origin

Search to south 1 yard, if not nd, turn to north Search to north 1 yard, if not nd, turn to south Search to south 2 yard, if not nd, turn to north Search to north 2 yard, if not nd, turn to south

... (follow the above pattern in geometric sequence 1, 2, 4, 8, ...)

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OR n = 1; While (not nd) do n = n + 1;

Search to south 2n, and turn; Search to north 2n, and turn;

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Correctness proof
Each time when the while loop is nished, the range from south 2n to north 2n is searched. Based on the fact that the booth is at a constant distance x from the origin, it will be within a range from south 2N to north 2N for some N . With n to increment in each loop, we will nd the booth in nite time.

Is this the fastest (or shortest) way to nd the booth?

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Analysis of algorithm
Observation: the traveled distance depends on where is the booth Suppose the distance between the booth and the origin is x When the algorithm stops, we should have 2n x but 2n1 < x The distance traveled is

which is smaller than 14x We know that the lower bound is x, can we do better?
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3 2n + 2(2 2n1 + 2 2n2 + + 2) 7 2n

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Complexity of an algorithm
Two resources: running time and storage

They are dependent on inputs: expressed as functions of input size Why input size: lower bound (at least read it once) Big-Oh notation: f (n) = O(g(n)) if there exist constants n0 and c such that for all n > n0, f (n) c g(n). Make our life easy: is it 13x instead of 14x in our game The solution is asymptotically optimal for our game

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Time complexity of an algorithm

Run-time comparison: 1000 MIPS (Yr: 200x), 1 instr. /op.

Time 500 3n n log n n2 n3 2n n! Big-Oh O(1) O(n) O(n log n) O(n2 ) O(n3 ) O(2n ) O(n!) n = 10 5 107 sec 3 108 sec 3 108 sec 1 107 sec 1 106 sec 1 106 sec 0.003 sec n = 100 5 107 sec 3 107 sec 2 107 sec 1 105 sec 0.001 sec 3 1017 cent. -

Polynomial-time complexity: O(p(n)), where n is the input size and p(n) is a polynomial function of n.

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n = 103 5 107 sec 3 106 sec 3 106 sec 0.001 sec 1 sec -

n = 106 5 107 sec 0.003 sec 0.006 sec 16.7 min 3 105 cent. -

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Complexity of a problem
Given a problem, what is the running time of the fastest algorithm for it? Upper bound: easynd an algorithm with less time Lower bound: hardevery algorithm requires more time P: set of problems solvable in polynomial time NP(Nondeterministic P): set of problems whose solution can be proved in polynomial time Millennium open problem: NP = P? Fact: there are a set of problems in NP resisting any polynomial solution for a long time (40 years)
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NP-complete and NP-hard

Cook 1970: If the problem of boolean satisability can be solved in poly. time, so can all problems in NP. Such a problem with this property is called NP-hard. If a NP-hard problem is in NP, it is called NP-complete. Karp 1971: Many other problems resisting poly. solutions are NP-complete.

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How to deal with a hard problem

Prove the problem is NP-complete:

1. The problem is in NP (i.e. solution can be proved in poly. time) 2. It is NP-hard (by polynomial reducing a NP-complete problem to it) Solve NP-hard problems:

Exponential algorithm (feasible only when the problem size is small) Pseudo-polynomial time algorithms Restriction: work on a subset of the input space
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Approximation algorithms: get a provable close-to-optimal solution

Heuristics: get a as good as possible solution Randomized algorithm: get the solution with high probability

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Algorithmic Paradigms
Divide and conquer: divide a problem into sub-problems, solve sub-problems, and combine them to construct a solution. Greedy algorithm: optimal solutions to sub-problems will give optimal solution to the whole problem. Dynamic programming: solutions to a larger problem are constructed from a set of solutions to its sub-problems. Mathematical programming: a system of optimizing an objective function under constraints functions. Simulated annealing: an adaptive, iterative, non-deterministic algorithm that allows uphill moves to escape from local optima.
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Branch and bound: a search technique with pruning. Exhaustive search: search the entire solution space.

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