Mobile Pentium 4 M Ntel 845mp MZ Chipset Guide

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Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform

Design Guide
April 2002
Order Number: 250688-002
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intels Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Actual system-level properties, such as skin temperature, are a function of various factors, including component placement, component power characteristics, system power and thermal management techniques, software application usage and general system design. Intel is not responsible for its customers system designs, nor is Intel responsible for ensuring that its customers products comply with all applicable laws and regulations. Intel provides this and other thermal design information for informational purposes only. System design is the sole responsibility of Intels customers, and Intels customers should not rely on any Intel-provided information as either an endorsement or recommendation of any particular system design characteristics. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel 845MP/845MZ chipset MCH-M may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. I2C is a 2-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was developed by Intel. Implementations of the I2C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips Corporation. Alert on LAN is a result of the Intel-IBM Advanced Manageability Alliance and a trademark of IBM. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation www.intel.com or call 1-800-548-4725 Intel, Pentium, NetBurst , and SpeedStep technology is a registered trademark or trademark of Intel Corporation and its subsidiaries in the United States and other countries. *Other brands and names may be claimed as the property of others. Copyright Intel Corporation 2002
Design Guide
Contents
1. Introduction ................................................................................................................................ 14 1.1. 1.2. 1.3. 1.4. Related Documentation................................................................................................. 15 Conventions and Terminology....................................................................................... 16 Mobile Intel Pentium 4 Processor-M in 478- Pin Package......................................... 18 Intel 845MP/845MZ Chipset .......................................................................................... 19 1.4.1. Intel Memory Controller Hub (MCH-M)........................................................ 20 1.4.1.1. Processor System Bus Support...................................................... 21 1.4.1.2. Integrated System Memory DRAM Controller ................................ 21 1.4.1.2.1. Accelerated Graphics Port (AGP) Interface ................. 21 1.4.1.3. Packaging/Power............................................................................ 22 1.4.1.4. I/O Controller Hub (ICH3-M)........................................................... 22 1.4.1.4.1. Packaging/Power.......................................................... 22 1.4.1.5. Firmware Hub (FWH) ..................................................................... 22 1.4.1.5.1. Packaging/Power.......................................................... 22 1.4.2. Bandwidth Summary ................................................................................... 22 Nominal Board Stackup................................................................................................. 24 Introduction.................................................................................................................... 25 Processor System Bus (PSB) Routing Guidelines ........................................................ 26 3.2.1. Return Path Evaluation ............................................................................... 27 3.2.2. GTLREF Layout and Routing Recommendations....................................... 28 Processor Configuration................................................................................................ 28 3.3.1. Mobile Intel Pentium 4 Processor-M in the 478 -Pin Package Configuration ............................................................................................... 28 General Topology and Layout Guidelines ..................................................................... 29 3.4.1. Design Recommendations .......................................................................... 29 3.4.2. Source Synchronous (SS) Signals .............................................................. 30 3.4.3. Common Clock (CC) AGTL+ Signals.......................................................... 32 3.4.3.1. CC Topology with ODT................................................................... 32 3.4.4. Asynchronous AGTL+ Signals .................................................................... 34 3.4.4.1. CPU THRMTRIP# Circuit Recommendation.................................. 35 3.4.4.1.1. Topology #1: Asynchronous AGTL+ Signals Driven by the Processor; FERR#, IERR#, PROCHOT# and THRMTRIP# ................................................................. 36 3.4.4.1.2. Topology #2, #2A: Asynchronous AGTL+ Signals Driven by ICH3-M..................................................................... 36 3.4.4.1.3. Topology #2B: Asynchronous AGTL+ Signals Driven by ICH3-M to Both CPU and FWH; INIT# ......................... 37 3.4.4.2. Voltage Translator Circuit ............................................................... 38 ITP Debug Port.............................................................................................................. 38 3.5.1.1. Logic Analyzer Interface (LAI) ........................................................ 38 3.5.1.1.1. Mechanical Considerations .......................................... 38 3.5.1.1.2. Electrical Considerations .............................................. 39 General Description....................................................................................................... 40 Power Delivery Architectural Block Diagram ................................................................. 41
2. 3.
General Design Considerations ................................................................................................. 24 2.1. 3.1. 3.2. Processor System Bus Design Guidelines ................................................................................ 25
3.3.
3.4.
3.5.
4.
Processor Power Requirements ................................................................................................ 40 4.1. 4.2.
Design Guide
4.3. 4.4.
4.5. 4.6.
4.7. 4.8. 4.9. 5. 5.1. 5.2.
Processor Phase Lock Loop Design Guidelines............................................................41 4.3.1. Filter Specifications for VCCA, VCCIOPLL, and VSSA ...............................41 Voltage and Current.......................................................................................................44 4.4.1. Voltage Identification....................................................................................44 4.4.2. VCC Power Sequencing ................................................................................44 4.4.2.1. Core Converter Soft Start Timer .....................................................44 4.4.2.2. Power On/Off Sequencing ..............................................................44 Voltage Regulator Design Recommendations ...............................................................45 Processor Decoupling Recommendation ......................................................................45 4.6.1. Transient Response.....................................................................................46 4.6.2. Processor Voltage Plane .............................................................................46 4.6.3. High Frequency Decoupling.........................................................................47 4.6.4. Bulk Decoupling ...........................................................................................47 Thermal Power Dissipation ............................................................................................47 Voltage Regulator Topology...........................................................................................49 Voltage Regulator Layout Recommendations ...............................................................49 Introduction ....................................................................................................................54 DDR System Memory Topology and Layout Design Guidelines....................................55 5.2.1. Data Signals SDQ[63:0], SDQS[8:0], SCB[7:0] ........................................55 5.2.1.1. Data to Strobe Length Matching Requirements ..............................57 5.2.1.2. Strobe to Clock Length Matching Requirements ............................59 5.2.1.3. Data Routing Example ....................................................................61 5.2.2. Control Signals SCKE[3:0], SCS#[3:0] .....................................................61 5.2.2.1. Control Group Signal Length Matching Requirements....................64 5.2.2.2. Control Routing Example ................................................................65 5.2.3. Command Signals SMA[12:0], SBS[1:0], SRAS#, SCAS#, SWE# ..........66 5.2.3.1. Command Topology 1 Solution.......................................................67 5.2.3.1.1. Routing description for Command Topology 1..............67 5.2.3.1.2. Command Group Signal Length Matching Requirements................................................................69 5.2.3.2. Command Topology 2 Solution.......................................................72 5.2.3.2.1. Routing Description for Command Topology 2 .............72 5.2.3.2.2. Command Group Signal Length Matching Requirements................................................................74 5.2.3.2.3. Command Routing Example for Topology 2 Solution ...76 5.2.4. Clock Signals SCK[5:0], SCK#[5:0] ..........................................................77 5.2.4.1. Clock Group Signal Length Matching Requirements ......................79 5.2.5. Feedback - RCVENOUT#, RCVENIN# .......................................................81 AGP Interface ................................................................................................................85 AGP 2.0 .........................................................................................................................86 6.2.1. AGP Interface Signal Groups ......................................................................86 AGP Routing Guidelines ................................................................................................87 6.3.1. 1X Timing Domain Routing Guidelines........................................................87 6.3.1.1. Trace Length Requirements for the AGP 1X ..................................87 6.3.1.2. Trace Spacing Requirements .........................................................88 6.3.1.3. Trace Length Mismatch ..................................................................88 6.3.2. 2X/4X Timing Domain Routing Guidelines ..................................................88 6.3.2.1. Trace Length Requirements for AGP 2X/4X...................................88 6.3.2.2. Trace Spacing Requirements .........................................................89
Double Data Rate Synchronous DRAM (DDR-SDRAM) System Memory Design Guidelines ...54
6.
AGP Port Design Guidelines ......................................................................................................85 6.1. 6.2. 6.3.
Design Guide
6.3.3. 6.3.4. 6.3.5. 6.3.6. 6.3.7. 6.3.8. 6.3.9. 7. 8. 7.1. 8.1. 8.2. 8.3. 8.4. 8.5. 9. 9.1.
6.3.2.3. Trace Length Mismatch Requirements .......................................... 90 AGP Clock Skew......................................................................................... 91 AGP Signal Noise Decoupling Guidelines................................................... 91 AGP Routing Ground Reference................................................................. 92 Pull-ups ....................................................................................................... 92 AGP VDDQ and Vref................................................................................... 93 Vref Generation for AGP 2.0(2X & 4X) ....................................................... 93 6.3.8.1. 3.3-V AGP Interface (AGP 2x)........................................................ 93 6.3.8.2. 1.5-V AGP interface (AGP 2x & 4x)................................................ 93 Compensation ............................................................................................. 94
MCH-M PLL Requirements ........................................................................................................ 95 MCH-M PLL Power Delivery.......................................................................................... 95 Hub Interface Routing Guidelines ................................................................................. 97 Hub Interface Data Signals ........................................................................................... 97 Hub Interface Strobe Signals ........................................................................................ 98 HUBREF Generation/Distribution .................................................................................. 98 Hub Interface Decoupling Guidelines ............................................................................ 99 IDE Interface ............................................................................................................... 100 9.1.1. Primary IDE Connector Requirements ...................................................... 102 9.1.2. Secondary IDE Connector Requirements ................................................. 103 PCI............................................................................................................................... 104 AC97........................................................................................................................... 104 9.3.1. Four-Layer Layout Example ...................................................................... 105 9.3.2. AC97 Audio Codec Detect Circuit and Configuration Options.................. 106 9.3.3. Valid Codec Configurations....................................................................... 106 9.3.4. SPKR Pin Consideration ........................................................................... 106 9.3.5. AC97 Routing ........................................................................................... 107 9.3.6. Motherboard Implementation .................................................................... 108 USB Guidelines and Recommendations ..................................................................... 108 9.4.1. General Routing and Placement ............................................................... 108 9.4.2. USB Trace Separation .............................................................................. 109 9.4.3. USB Trace Length Matching ..................................................................... 109 9.4.4. Plane Splits, Voids and Cut-Outs (Anti-Etch) ............................................ 110 9.4.4.1. VCC Plane Splits, Voids, and Cut-Outs (Anti-Etch)...................... 110 9.4.4.2. GND Plane Splits, Voids, and Cut-Outs (Anti-Etch) ..................... 110 9.4.4.3. EMI Recommendation .................................................................. 110 IOAPIC (I/O Advanced Programmable Interrupt Controller) ....................................... 110 9.5.1. IOAPIC Disabling Options ......................................................................... 110 9.5.1.1. Recommended Implementation ................................................... 110 9.5.2. PIRQ Routing Example ............................................................................. 111 SMBus 2.0/SMLink Interface....................................................................................... 112 9.6.1. SMBus Architecture and Design Considerations ...................................... 113 9.6.1.1. SMBus Design Considerations ..................................................... 113 9.6.1.2. General Design Issues/Notes....................................................... 113 9.6.1.3. The Unified Vcc_ Suspend Architecture....................................... 113 9.6.1.4. The Unified Vcc_Core Architecture .............................................. 114 9.6.1.5. Mixed Architecture........................................................................ 114 FWH ............................................................................................................................ 115 Hub Interface.............................................................................................................................. 97
I/O Subsystem.......................................................................................................................... 100
9.2. 9.3.
9.4.
9.5.
9.6.
9.7.
Design Guide
9.8. 9.9.
9.10.
9.7.1. FWH Decoupling........................................................................................115 9.7.2. In Circuit FWH Programming.....................................................................115 FWH Signaling Voltage Compatibility ..........................................................................116 9.8.1. FWH Vpp Design Guidelines .....................................................................116 RTC..............................................................................................................................116 9.9.1. RTC Crystal ...............................................................................................117 9.9.2. External Capacitors ...................................................................................119 9.9.3. RTC Layout Considerations.......................................................................120 9.9.4. RTC External Battery Connection..............................................................120 9.9.5. RTC Routing Guidelines ............................................................................121 9.9.6. VBIAS DC Voltage and Noise Measurements...........................................121 9.9.7. SUSCLK.....................................................................................................122 9.9.8. RTC-Well Input Strap Requirements .........................................................122 Internal LAN Layout Guidelines ...................................................................................123 9.10.1. ICH3-M LAN Interconnect Guidelines.....................................................124 9.10.1.1. Point-to-point Interconnect ............................................................124 9.10.1.2. Signal Routing and Layout ............................................................125 9.10.1.3. Crosstalk Consideration ................................................................126 9.10.1.4. Impedances...................................................................................126 9.10.1.5. Line Termination ...........................................................................126 9.10.2. General LAN Routing Guidelines and Considerations...............................126 9.10.2.1. General Trace Routing Considerations.........................................126 9.10.2.1.1. Trace Geometry and Length .......................................128 9.10.2.1.2. Signal Isolation............................................................129 9.10.2.2. Power and Ground Connections ...................................................129 9.10.2.2.1. General Power and Ground Plane Considerations .....129 9.10.2.3. A Four-Layer Board Design (Example) .........................................130 9.10.2.3.1. Top Layer Routing.......................................................130 9.10.2.3.2. Ground Plane ..............................................................131 9.10.2.3.3. Power Plane................................................................131 9.10.2.3.4. Bottom Layer Routing .................................................131 9.10.2.4. Common Physical Layout Issues ..................................................131 9.10.3. 82562EH Home/PNA* Guidelines .............................................................132 9.10.3.1. Related Docs.................................................................................132 9.10.3.2. Power and Ground Connections ...................................................133 9.10.3.3. Guidelines for 82562EH Component Placement ..........................133 9.10.3.4. Crystals and Oscillators ................................................................133 9.10.3.5. Phoneline HPNA Termination .......................................................133 9.10.3.6. Critical Dimensions .......................................................................134 9.10.3.6.1. Distance from Magnetic Module to Line RJ11 ............135 9.10.3.6.2. Distance from 82562EH to Magnetic Module .............135 9.10.3.6.3. Distance from LPF to Phone RJ11 .............................136 9.10.4. 82562ET / 82562EM Guidelines ................................................................136 9.10.4.1. Related Docs.................................................................................136 9.10.4.2. Guidelines for 82562ET / 82562EM Component Placement ........136 9.10.4.3. Crystals and Oscillators ................................................................136 9.10.4.4. 82562ET/82562EM Termination Resistors ...................................137 9.10.4.5. Critical Dimensions .......................................................................137 9.10.4.5.1. Distance from Magnetic Module to RJ45 ....................138 9.10.4.5.2. Distance from 82562ET to Magnetic Module..............138 9.10.4.6. Reducing Circuit Inductance .........................................................138 9.10.4.6.1. Terminating Unused Connections...............................139 9.10.4.6.2. Termination Plane Capacitance..................................139 9.10.5. 82562ET/82562EH Dual Footprint Guidelines...........................................139
Design Guide
10.
Platform Clock Routing Guidelines .......................................................................................... 142 10.1. 10.2. Clock Generation......................................................................................................... 142 Clock Control............................................................................................................... 145 10.2.1. CK-408 Delay Circuit Recommendation.................................................... 145 10.2.2. SLP_S1# ................................................................................................... 145 10.2.3. SLP_S3# ................................................................................................... 145 Clock Group Topology and Layout Routing Guidelines............................................... 146 10.3.1. HOST_CLK Clock Group .......................................................................... 146 10.3.1.1. End Of Line Termination Topology............................................... 146 10.3.1.2. Source Shunt Termination Topology ............................................ 148 10.3.2. CLK66 Clock Group .................................................................................. 151 10.3.3. AGPCLK Clock Group............................................................................... 152 10.3.4. CLK33 Clock Group .................................................................................. 154 10.3.5. CLK14 Clock Group .................................................................................. 154 10.3.6. PCICLK Clock Group ................................................................................ 156 10.3.7. USBCLK Clock Group ............................................................................... 158 Definitions.................................................................................................................... 159 Platform Power Requirements .................................................................................... 160 11.2.1. Platform Power Delivery Architectural Block Diagram .............................. 160 Voltage Supply............................................................................................................. 161 11.3.1. Power Management States ....................................................................... 161 11.3.2. Power Supply Rail Descriptions ................................................................ 161 11.3.3. Power Supply Control Signals ................................................................... 162 11.3.3.1. SLP_S3# .................................................................................... 162 11.3.3.2. SLP_S5# .................................................................................... 162 Platform Power Sequencing Requirements ................................................................ 162 11.4.1. Processor Power Sequencing ................................................................... 162 11.4.1.1. Core Converter Soft Start Timer................................................... 162 11.4.2. ICH3-M Power Sequencing....................................................................... 162 11.4.2.1. 1.8 V/3.3 V Sequencing ................................................................ 162 11.4.2.2. 3.3-V/V5REF and 3.3SUS/V5REF_SUS Sequencing .................. 163 11.4.3. MCH-M Power Sequencing Requirements ............................................... 165 11.4.4. DDR Power Sequencing Requirements .................................................... 165 Decoupling Recommendations ................................................................................... 166 11.5.1. Transient Response .................................................................................. 166 11.5.2. Processor Decoupling Recommendations ................................................ 166 11.5.3. ICH3-M Decoupling Recommendations.................................................... 166 11.5.3.1. 1.8-V Power Supply Rails ............................................................. 166 11.5.3.2. 3.3-V Power Supply Rails ............................................................. 167 11.5.4. MCH-M Decoupling Recommendations.................................................... 167 11.5.4.1. VCC_CORE, VTT Processor System Bus, VTT .......................... 167 11.5.4.2. 1.5-V AGP/CORE ......................................................................... 167 11.5.4.3. 1.8-V Hub Interface ...................................................................... 167 11.5.5. 2.5-V MCH-M System Memory High Frequency Decoupling .................... 167 11.5.6. 2.5-V MCH-M System Memory Low Frequency Bulk Decoupling............. 168 11.5.7. 2.5-V SO-DIMM System Memory High Frequency Decoupling ................ 168 11.5.8. 2.5-V SO-DIMM System Memory Low Frequency Decoupling ................. 168 11.5.9. 1.25-V DDR VTT High Frequency Decoupling Requirements .................. 168 11.5.10. 1.25-V DDR VTT Low Frequency Bulk Decoupling Requirements ........... 169 11.5.11. 1.5-V AGP Decoupling .............................................................................. 169 11.5.12. 1.8-V Hub Interface Decoupling ................................................................ 169
10.3.
11.
Platform Power Guidelines....................................................................................................... 159 11.1. 11.2. 11.3.
11.4.
11.5.
Design Guide
11.6. 11.7.
11.8. 12. 12.1. 12.2. 12.3. 12.4. 12.5. 12.6. 12.7. 12.8. 12.9. 12.10. 12.11. 12.12. 12.13. 12.14. 12.15. 12.16. 12.17. 12.18. 12.19. 12.20. 12.21. 13.
11.5.13. 3.3-V FWH Decoupling ..............................................................................169 11.5.14. 3.3-V General LAN Decoupling..................................................................170 3.3-V Clock Driver Decoupling.....................................................................................170 DDR Power Delivery Design Guidelines ......................................................................170 11.7.1. DDR Memory Bypass Capacitor Guidelines ..............................................171 11.7.2. 2.5-V Power Delivery Guidelines ...............................................................171 11.7.3. Intel 845MP/845MZ Chipset DDR Reference Board Power Delivery ........173 11.7.4. DDR Reference Voltage ............................................................................173 11.7.4.1. VREF Generation..........................................................................177 11.7.4.2. DDR VREF Requirements ............................................................179 11.7.5. DDR SMRCOMP Resistive Compensation ...............................................180 11.7.6. DDR VTT Termination ...............................................................................180 Clock Driver Power Delivery Design Guidelines ..........................................................180 Host Interface...............................................................................................................183 In Target Probe (ITP) ...................................................................................................185 Thermal Sensor ...........................................................................................................186 PLL[2:1] PLC Filter.......................................................................................................186 Decoupling Recommendation......................................................................................186 CK-408 Clock Checklist ...............................................................................................187 DDR SO-DIMM0 Connector.........................................................................................189 DDR SO-DIMM1 Connector.........................................................................................191 MCH-M Signals ............................................................................................................193 AGP ....................................................................................................196 ICH3-M Checklist ......................................................................................................198 HUB Interface.........................................................................................201 USB Checklist. .........................................................................204 FWH Checklist.. .....................................................................................204 LAN/HomePNA Checklist ............................................................................................205 EEPROM Interface ......................................................................................................205 Interrupt Interface ......................................................................................................206 GPIO............................................................................................207 CPU Signals.. .....................................................................................208 IDE Checklist...................................................................................208 HomePNA - Resistor Recommendation ......................................................................209
System Design Checklist..........................................................................................................183
Customer Reference Board Schematics ..................................................................................210
Design Guide
Figures
Figure 1. Typical System Block Diagram ................................................................................. 20 Figure 2. Cross-Sectional View of 2:1 Ratio ............................................................................ 27 Figure 3. GTLREF Routing ...................................................................................................... 28 Figure 4. Processor Topology .................................................................................................. 30 Figure 5. SS Topology for Address and Data .......................................................................... 31 Figure 6. CC Topology With ODT ............................................................................................ 33 Figure 7. CC Topology Without ODT ....................................................................................... 33 Figure 8. THRMTRIP# Circuit Recommendation..................................................................... 35 Figure 9. Routing Illustration for FERR#, IERR#, PROCHOT#, and THRMTRIP#.................. 36 Figure 10. Routing Illustration for LINT1/INTR, LINT0/NMI, DPSLP#, SLP#, STPCLK#, IGNNE#, SMI# and A20M#, CPUPERF#, and PWRGOOD- Topology 2, 2A .......... 37 Figure 11. Routing Illustration INIT# ........................................................................................ 37 Figure 12. Voltage Translator Circuit of Topology#1 and #2B ................................................. 38 Figure 13. Voltage Regulator Block Diagram........................................................................... 41 Figure 14. Typical VCCIOPLL, VCCA, and VSSA Power Distribution ..................................... 42 Figure 15. Filter Recommendation........................................................................................... 43 Figure 16. Example Component Placement for PLL Filter....................................................... 44 Figure 17. Power On Sequencing Diagram ............................................................................. 45 Figure 18. Power Off Sequencing Diagram ............................................................................. 45 Figure 19. Processor High Frequency Decoupling Placement Example ................................. 47 Figure 20. Data Signal Routing Topology ................................................................................ 56 Figure 21. DQ/CB to DQS Trace Length Matching Requirements .......................................... 58 Figure 22. SDQS to SCK/SCK# Trace Length Matching Requirements.................................. 60 Figure 23. Data Signal Group Routing Example ...................................................................... 61 Figure 24. SO-DIMM0, 1 Control Signal Routing Topology ..................................................... 62 Figure 25. Referencing Plane Stack-up ................................................................................... 63 Figure 26. Control Signal to SCK/SCK# Trace Length Matching Requirements ..................... 65 Figure 27. Control Routing Example ........................................................................................ 66 Figure 28. Command Signal Routing Topology 1 .................................................................... 67 Figure 29. Referencing Plane Stack-up ................................................................................... 69 Figure 30. Command Signal to SCK/SCK# Trace Length Matching Requirements ................ 70 Figure 31. Command Routing Example for Topology 1........................................................... 71 Figure 32. Command Signal Routing Topology ....................................................................... 72 Figure 33. Referencing Plane Stack-up ................................................................................... 73 Figure 34. Command Signal to SCK/SCK# Trace Length Matching Requirements ................ 75 Figure 35. Command Routing Example for Topology 2........................................................... 76 Figure 36. DDR Clock Routing Topology (SCK/SCK#[2:0])..................................................... 77 Figure 37. Ground Referencing Plane Stack-up ...................................................................... 78 Figure 38. SCK to SCK# Trace Length Matching Requirements ............................................. 80 Figure 39. Clock Pair Trace Length Matching Requirements .................................................. 81 Figure 40. DDR Feedback (RCVEN#) Routing Topology ........................................................ 82 Figure 41. AGP Layout Guidelines........................................................................................... 89 Figure 42. Intel 845MP/845MZ PLL0 Filter .............................................................................. 95 Figure 43. Intel 845MP/845MZ PLL1 Filter .............................................................................. 96 Figure 44. Hub Interface Routing Example .............................................................................. 97 Figure 45. Single HUBREF Voltage Divider ............................................................................. 99 Figure 46. Locally Generated HUBREF Divider ....................................................................... 99 Figure 47. Connection Requirements for Primary IDE Connector ......................................... 102 Figure 48. Connection Requirements for Secondary IDE Connector .................................... 103 Figure 49. PCI Bus Layout Example ...................................................................................... 104 Figure 50. ICH3-M AC97 Codec Connection ..................................................................... 105
Design Guide
Figure 51. Example Speaker Circuit.......................................................................................107 Figure 52. Minimum IOAPIC Disable Topology......................................................................111 Figure 53. Example PIRQ Routing .........................................................................................111 Figure 54. SMBUS 2.0/SMLink Interface................................................................................113 Figure 55. Unified Vcc_Suspend Architecture........................................................................114 Figure 56. Unified Vcc_Core Architecture ..............................................................................114 Figure 57. Mixed Vcc_Suspend/Vcc_Core Architecture.........................................................115 Figure 58. FWH VPP Isolation Circuitry .................................................................................116 Figure 59. RTCX1 and SUSCLK Relationship in ICH3-M ......................................................117 Figure 60. External Circuitry for the ICH3-M RTC ..................................................................118 Figure 61. RTC Connections When Not Using Internal RTC .................................................118 Figure 62. A Diode Circuit to Connect RTC External Battery .................................................121 Figure 63. ICH3-M/LAN Connect Section (Dual Footprint Option) .........................................123 Figure 64. Single Solution Interconnect..................................................................................125 Figure 65. LAN_CLK Routing Example ..................................................................................126 Figure 66. Trace Routing ........................................................................................................128 Figure 67. Ground Plane Separation ......................................................................................130 Figure 68. 82562EH Termination ...........................................................................................134 Figure 69. Critical Dimensions for Component Placement.....................................................135 Figure 70. 82562ET/82562EM Termination ...........................................................................137 Figure 71. Critical Dimensions for Component Placement.....................................................137 Figure 72. Termination Plane .................................................................................................139 Figure 73. Dual Footprint LAN Connect Interface ..................................................................140 Figure 74. Dual Footprint Analog Interface.............................................................................140 Figure 75. Processor BCLK Topology ....................................................................................144 Figure 76. ICH3-M Follows the CK-408 Power-up .................................................................145 Figure 77. PWRDWN# to CK-408 ..........................................................................................146 Figure 78. End of Line Termination Topology.........................................................................147 Figure 79. Source Shunt Termination Topology.....................................................................149 Figure 80. Clock Skew as Measured from Agent to Agent.....................................................151 Figure 81. Trace Spacing .......................................................................................................151 Figure 82. Topology for CLK66...............................................................................................152 Figure 83. Topology for AGPCLK to AGP Connector.............................................................153 Figure 84. Topology for AGPCLK to AGP Device Down ........................................................153 Figure 85. Topology for CLK33...............................................................................................154 Figure 86. Topology for CLK14...............................................................................................155 Figure 87. Topology for PCICLK to PCI Device Down ...........................................................156 Figure 88. Topology for PCICLK to PCI Slot ..........................................................................157 Figure 89. Topology for USB_CLOCK....................................................................................158 Figure 90. Platform Power Delivery Block Diagram ...............................................................160 Figure 91. Example 1.8-V/3.3-V Power Sequencing Circuit ...................................................163 Figure 92. Example 3.3-V/V5REF Sequencing Circuitry ........................................................164 Figure 93. V5REF_Sus Option 1: +V5_Always Available in Platform.....................................164 Figure 94. V5REF_Sus Option 1: +V5_Always Not Available in Platform ..............................165 Figure 95. DDR Power Delivery Block Diagram .....................................................................171 Figure 96. Intel 845MP/845MZ Chipset DDR Power Delivery Example .................................173 Figure 97. SMRCOMP Recommendation ..............................................................................180 Figure 98. Decoupling Capacitors Placement and Connectivity.............................................182
10
Design Guide
Tables
Table 1. Conventions and Terminology ................................................................................... 16 Table 2. Mobile Pentium 4 Processor-M in the 478-Pin Package Feature Set Overview........ 19 Table 3. Platform Bandwidth Summary.................................................................................... 23 Table 4. System Bus Routing Summary for the Processor...................................................... 26 Table 5. Processor System Bus Data Signal Routing Guidelines............................................ 30 Table 6. Processor System Bus Address Signal Routing Guidelines ...................................... 31 Table 7. Processor System Bus Control Signal Routing Guidelines........................................ 32 Table 8. Asynchronous AGTL+ Nets ....................................................................................... 34 Table 9. Layout Recommendations for Miscellaneous Signals Topology 1.......................... 36 Table 10. Layout Recommendations for Miscellaneous Signals Topology 2, 2A ................. 37 Table 11. Layout Recommendations for Miscellaneous Signals Topology 2B ..................... 37 Table 12. Intel Mobile Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Package Lengths..................................................................................................................... 50 Table 13. Intel 845MP/845MZ DDR Signal Groups ................................................................. 54 Table 14. Data Signal Group Routing Guidelines .................................................................... 56 Table 15. DQ/CB to DQS Length Mismatch Mapping.............................................................. 57 Table 16. Control Signal SO-DIMM Mapping........................................................................... 62 1 Table 17. Control Signal Group Routing Guidelines ............................................................... 63 1 Table 18. Command Signal Group Routing Guidelines .......................................................... 68 Table 19. Command Signal Group Routing Guidelines ........................................................... 73 Table 20. Clock Signal Mapping .............................................................................................. 77 1 Table 21. Clock Signal Group Routing Guidelines ................................................................. 78 Table 22. DDR Feedback Signal Routing Guidelines .............................................................. 82 Table 23. MCH-M DDR Signal Package Lengths .................................................................... 83 Table 24. AGP 2.0 Signal Groups............................................................................................ 86 Table 25. AGP 2.0 Data/Strobe Associations .......................................................................... 87 Table 26. Layout Routing Guidelines for AGP 1X Signals ....................................................... 88 Table 27. Layout Routing Guidelines for AGP 2X/4X Signals.................................................. 90 Table 28. AGP 2.0 Data Lengths Relative to Strobe Length.................................................... 90 Table 29. AGP 2.0 Routing Guideline Summary...................................................................... 91 Table 30. AGP 2.0 Pull-up Resistor Values ............................................................................. 93 Table 31. PLL0 Filter Routing Guidelines ................................................................................ 95 Table 32. PLL1 Routing Guidelines ......................................................................................... 96 Table 33. Recommended Inductor Components for MCH-M PLL Filter .................................. 96 Table 34. Recommended Capacitor Components for MCH-M PLL Filter................................ 96 Table 35. Hub Interface RCOMP Resistor Values ................................................................... 97 Table 36. Hub Interface Signals............................................................................................... 98 Table 37. Hub Interface HUBREF Generation Circuit Specifications ...................................... 98 Table 38. IDE Signals ............................................................................................................ 100 Table 39. Codec Configurations............................................................................................. 106 Table 40. USB Signals ........................................................................................................... 110 Table 41. Integrated LAN Capability ...................................................................................... 123 Table 42. LAN Design Guide Section Reference................................................................... 124 Table 43. LAN Design Guide Point-to-Point Length Requirements ....................................... 125 Table 44. LAN Signals ........................................................................................................... 128 Table 45. 82562EH Home/PNA* Critical Dimensions for Component Placement................. 135 Table 46. 82562ET / 82562EM Critical Dimensions for Component Placement ................... 138 Table 47. Intel 845MP/845MZ Clock Groups ......................................................................... 142 Table 48. Platform System Clock Cross-reference................................................................ 143 Table 49. End of Line Termination Topology BCLK [1:0]# Routing Guidelines ..................... 148 Table 50. Source Shunt Termination Topology BCLK [1:0]# Routing Guidelines.................. 149 Table 51. CLK66 Routing Guidelines ..................................................................................... 152 Table 52. AGPCLK Routing Guidelines ................................................................................. 153 Design Guide 11
Table 53. CLK33 Routing Guidelines .....................................................................................154 Table 54. CLK14 Routing Guidelines .....................................................................................155 Table 55. PCICLK Routing Guidelines ...................................................................................156 Table 56. PCICLK Routing Guidelines ...................................................................................157 Table 57. USBCLK Routing Guidelines ..................................................................................158 Table 58. Power Management States ....................................................................................161 Table 59. Power Supply Rail Descriptions (* Currents are Estimates Only)...........................161 Table 60. Power-up Initialization Sequence (Should Above Listed Requirements Not be Met) .........................................................................................................................165 Table 61. DDR SDRAM Memory Voltage & Current Specification .........................................175 Table 62. MCH-M DDR Voltage & Current Specifications......................................................176 Table 63. Termination Voltage and Current Specifications ....................................................177 Table 64. MCH-M DDR I/O.....................................................................................................178 Table 65. Effects of Varying Resistor Values in the Divider Circuit ........................................178 Table 66. MCH-M VREF Calculation ......................................................................................179 Table 67. Reference Distortion Due to Load Current .............................................................179 Table 68. Resistor Recommendations ...................................................................................183 Table 69. In Target Probe(ITP)...............................................................................................185 Table 70. Thermal Sensor Signals .........................................................................................186 Table 71. PLL[2:1] RLC Filter .................................................................................................186 Table 72. Decoupling Recommendation ................................................................................186 Table 73. Resistor Recommendation .....................................................................................187 Table 74. DDR S0-DIMM0 Recommendations.......................................................................189 Table 75. DDR S0-DIMM0 Recommendations.......................................................................191 Table 76. DDR Extra...............................................................................................................192 Table 77. Processor System Bus Signals ..............................................................................193 Table 78. Miscellaneous Signals ............................................................................................194 Table 79. Decoupling Recommendation ................................................................................194 Table 80. Reference Voltage Dividers ....................................................................................195 Table 81. Resistor Recommendation .....................................................................................196 Table 82. Decoupling Recommendation ................................................................................197 Table 83. Reference Voltage Dividers ....................................................................................197 Table 84. PCI Resistor Recommendation ..............................................................................198 Table 85. System Management Interface (SM-BUS) ............................................................199 Table 86. AC 97 Interface ......................................................................................................199 Table 87. Power Management Interface ................................................................................199 Table 88. LPC Interface..........................................................................................................201 Table 89. USB Interface .........................................................................................................201 Table 90. Decoupling Recommendation ................................................................................201 Table 91. Reference Recommendation..................................................................................201 Table 92. RTC Circuitry ..........................................................................................................202 Table 93. LAN Interface..........................................................................................................202 Table 94. Decoupling Recommendation ................................................................................203 Table 95. Reference Voltage Dividers ....................................................................................203 Table 96. ICH3-M Miscellaneous Signals...............................................................................203 Table 97.Resistor Recommendations ....................................................................................204 Table 98. Decoupling Recommendations...............................................................................204 Table 99. Resistor Recommendations ...................................................................................204 Table 100. LAN Resistor Recommendations ......................................................................205 Table 101. EEPROM Interface Recommendation..................................................................205 Table 102. Interrupt Interface Recommendation....................................................................206 Table 103. GPIO Recommendation .......................................................................................207 Table 104. CPU Signals .........................................................................................................208 Table 105. IDE Checklist ........................................................................................................208 Table 106. HomePNA - Resistor Recommendation ...............................................................209 12 Design Guide
Revision History
Rev. 001 002 Initial Release Updates include: Added 845MZ product information Description Date March 2002 April 2002
Design Guide
13
1.
Introduction
This design guide provides Intels design recommendations for systems based on the Mobile Intel Pentium 4 Processor-M and the Intel 845MP/845MZ chipset. Design issues such as thermal considerations should be addressed using specific design guides or application notes for the processor or 845MP/845MZ chipset. These design guidelines have been developed to ensure maximum flexibility for board designers while reducing the risk of board related issues. The design information provided in this document falls into one of the two following categories. Design Recommendations are items based on Intels simulations and lab experience to date and are strongly recommended, if not necessary, to meet timing and signal quality specifications. Design Considerations are suggestions for platform design that provide one way to meet the design recommendations. They are based on the reference platforms designed by Intel. They should be used as examples, but may not be applicable to particular designs. Note: The guidelines recommended in this document are based on experience and preliminary simulation work performed at Intel while developing Mobile Intel Pentium 4 Processor-M and 845MP/845MZ chipsetbased systems. This work is ongoing, and the recommendations and considerations are subject to change. Platform schematics are provided in Section 13. The schematics are a reference for board designers. While the schematics may cover a specific design, the core schematics will remain the same for most platforms. The schematic set provides a reference schematic for each platform, component as well as common motherboard options. Additional flexibility is possible through other permutations of these options and components.
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Design Guide
1.1.
Related Documentation
Reference the following documents or models for more information. All Intel issued documentation revision numbers are subject to change, and the latest revision should be used. The specific revision numbers referenced should be used for all documents not released by Intel. Contact the field representative for information on how to obtain Intel issued documentation.
Document Intel 845MP/845MZ Chipset: 82845MP/845MZ Memory Controller Hub Mobile (MCH-M) Datasheet Mobile Intel Pentium 4 Processor-M in the 478 Pin Package Datasheet Mobile Intel Pentium 4 Processor-M in the 478 Pin Package Thermal Design Guidelines Mobile Intel 845MP/845MZ Chipset Thermal and Mechanical Design Guidelines Mobile Intel Pentium 4 Processor-M in the 478 pin package Processor Signal Integrity Models Mobile Intel Pentium 4 Processor-M VR Down Design Guidelines mPGA478 Socket Design Guidelines Intel PC DDR-SDRAM Specification Accelerated Graphics Port Interface Specification Rev 2.0 Low Pin Count Interface Specification Rev 1.0 PCI Local Bus Specification Rev. 2.1 PCI-PCI Bridge Specification Rev. 1.0 PCI Bus Power Management Interface Specification Rev. 1.0 Universal Serial Bus 1.1 Specification Advanced Configuration and Power Interface Specification (ACPI) Rev. 1.0b PC01 Specification PC 99 System Design Guide, Revision 1.0 ITP700 Debug Port Design Guide Intel 82801CAM I/O Controller Hub 3 (ICH3-M) Specification Update Intel 82562ET 10/100 Mbps Platform LAN Connect (PLC) Product Preview Datasheet

Document Number/Source 250687-002 250686-002 Contact your Field Representative Contact your Field Representative Contact your Field Representative Contact your Field Representative 249890 http://developer.intel.com/technology /memory/ddr/specs/ddr_specs.htm http://www.agpforum.org/ http://www.intel.com/design/chipsets/ industry/lpc.htm www.pcisig.com www.pcisig.com www.pcisig.com http://www.usb.org/developers/docs. html http://www.teleport.com/~acpi/ www.microsoft.com http://www.microsoft.com/hwdev/pc9 9.htm http://www.intel.com/design/Xeon/gui des/249679.htm http://developer.intel.com/design/chi psets/datashts/290716.htm (Order# A00358-004), available at http://wwwniooem.jf.intel.com/components.htm and on IBL Contact your Field Representative
Intel 82562ET LAN on Motherboard Design Guide (AP-414)
Design Guide
15
Document Intel 82562ET/EM PCB Design Platform LAN Connect (AP-412)
Document Number/Source Contact your Field Representative
1.2.
Conventions and Terminology

This section defines conventions and terminology that are used throughout this document.
Table 1. Conventions and Terminology

Convention/ Terminology Aggressor AGTL+ Definition A network that transmits a coupled signal to another network is called the aggressor network. The processor System Bus uses a bus technology called AGTL+, or Assisted Gunning Transceiver Logic. AGTL+ buffers are open-drain and require pull-up resistors that provide the high logic level and termination. AGTL+ output buffers differ from GTL+ buffers by the addition of an active pMOS pull-up transistor to assist the pull-up resistors during the first clock of a low-tohigh voltage transition. A component or group of components that, when combined, represent a single load on the AGTL+ bus. Describes how a component performs when all parameters that could impact performance are adjusted simultaneously to have the best or worst impact on performance. Examples of these parameters include variations in manufacturing process, operating temperature, and operating voltage. Performance of an electronic component may change as a result of (including, but not limited to): clock to output time, output driver edge rate, output drive current, and input drive current. Discussion of the slow corner means having a component operating at its slowest, weakest drive strength performance. Similar discussion of the fast corner means having a component operating at its fastest, strongest drive strength performance. Operation or simulation of a component at its slow corner and fast corner is expected to bound the extremes between slowest, weakest performance and fastest, strongest performance. The reception on a victim network of a signal imposed by aggressor network(s) through inductive and capacitive coupling between the networks. Backward Crosstalkcoupling that creates a signal in a victim network that travels in the opposite direction as the aggressors signal. Forward Crosstalkcoupling that creates a signal in a victim network that travels in the same direction as the aggressors signal. Even Mode Crosstalkcoupling from single or multiple aggressors when all the aggressors switch in the same direction that the victim is switching. Odd Mode Crosstalkcoupling from single or multiple aggressors when all the aggressors switch in the opposite direction that the victim is switching.
Bus Agent Corner
Crosstalk
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Design Guide
Convention/ Terminology Flight Time
Definition Flight time is a term in the timing equation that includes the signal propagation delay, any effects the system has on the TCO of the driver, and any adjustments to the signal at the receiver needed to guarantee the setup time of the receiver. More precisely, flight time is defined to be: Time difference between a signal at the input pin of a receiving agent crossing the switching voltage (adjusted to meet the receiver manufacturers conditions required for AC timing specifications; e.g., ringback, etc.) and the output pin of the driving agent crossing the switching voltage when the driver is driving a test load used to specify the drivers AC timings. Maximum and Minimum Flight TimeFlight time variations can be caused by many different variables. The more obvious causes include variation of the board dielectric constant, changes in load condition, crosstalk, power noise, variation in termination resistance and differences in I/O buffer performance as a function of temperature, voltage and manufacturing process. Some less obvious causes include effects of Simultaneous Switching Output (SSO) and packaging effects. Maximum flight time is the largest acceptable flight time a network will experience under all variations of conditions. Minimum flight time is the smallest acceptable flight time a network will experience under all variations of conditions.
GTL+
GTL+ is the bus technology used by the Intel Pentium Pro processor. This is an incident wave switching, open-drain bus with pull-up resistors that provide both the high logic level and termination. It is an enhancement to the GTL (Gunning Transceiver Logic) bus technology. Inter-symbol interference is the effect of a previous signal (or transition) on the interconnect delay. For example, when a signal is transmitted down a line and the reflections due to the transition have not completely dissipated, the following data transition launched onto the bus is affected. ISI is dependent upon frequency, time delay of the line, and the reflection coefficient at the driver and receiver. ISI can impact both timing and signal integrity. The network is the trace of a Printed Circuit Board (PCB) that completes an electrical connection between two or more components. The distance between one agent pin and the corresponding agent pin at the far end of the bus. Maximum voltage observed for a signal at the device pad. The electrical contact point of a semiconductor die to the package substrate. A pad is observable only in simulation. The contact point of a component package to the traces on a substrate, like the system board. Signal quality and timings can be measured at the pin. In this document processor refers to the Mobile Intel Pentium 4 Processor-M in the 478-pin package based on 0.13-micron (130 nanometer) technology. The voltage that a signal rings back to after achieving its maximum absolute value. Ringback may be due to reflections, driver oscillations, or other transmission line phenomena. The System Bus is the microprocessor bus of the Mobile Intel Pentium 4 Processor-M. It may also be termed system bus in implementations where the System Bus is routed to other components. The P6 bus was the microprocessor bus of the Mobile Intel Pentium Pro processor, Mobile Intel Pentium II processor, and Mobile Intel Pentium III processors. The System Bus is not compatible with the P6 bus. The time between the beginning of Setup to Clock (TSU_MIN) and the arrival of a valid clock edge. This window may be different for each type of bus agent in the system.
ISI
Network Network Length Overshoot Pad Pin Processor Ringback System Bus
Setup Window
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17
Convention/ Terminology SSO
Definition Simultaneous Switching Output (SSO) effects refers to the difference in electrical timing parameters and degradation in signal quality caused by multiple signal outputs simultaneously switching voltage levels (e.g., high-to-low) in the opposite direction from a single signal (e.g., lowto-high) or in the same direction (e.g., high-to-low). These are respectively called odd-mode switching and even-mode switching. This simultaneous switching of multiple outputs creates higher current swings that may cause additional propagation delay (or push-out), or a decrease in propagation delay (or pull-in). These SSO effects may impact the setup and/or hold times and are not always taken into account by simulations. System timing budgets should include margin for SSO effects. The branch from the bus trunk terminating at the pad of an agent. The main connection, excluding interconnect branches, from one end agent pad to the other end agent pad. Minimum voltage observed for a signal that falls below VSS at the device pad. A network that receives a coupled crosstalk signal from another network is called the victim network. A guardband defined above and below VREF to provide a more realistic model accounting for noise such as VTT and VREF variation.
Stub Trunk Undershoot Victim VREF Guardband
1.3.
Mobile Intel Pentium 4 Processor-M in 478- Pin Package

The Mobile Intel Pentium 4 Processor-M in the 478-pin package is the next generation, IA-32 processor. This processor has a number of features that significantly increase its performance from previous IA-32 generation processors. The new Intel NetBurst micro-architecture includes a number of new features as well as some improvements on existing features. Intel NetBurst micro-architecture features include hyper-pipelined technology, rapid execution engine, 400-MHz system bus, and execution trace cache. Compared to previous generation processors, the hyper pipelined technology doubles the pipeline depth in the mobile Pentium 4 Processor-M in the mobile and allows the processor to reach much higher core frequencies. The rapid execution engine allows the 2 integer ALUs in the processor to run at twice the core frequency, which allows many integer instructions to execute in 1/2 clock tick. The 400-MHz system bus is a quad-pumped bus running off a 100-MHz system clock making 3.2 GB/sec data transfer rates possible. The execution trace cache is a level 1 cache that stores approximately 12-k decoded micro-operations, which removes the decoder from the main execution path, thereby increasing performance. Improved features within the Intel NetBurst micro-architecture include the advanced dynamic execution, advanced transfer cache, enhanced floating point and multi-media unit, and Streaming SIMD Extensions 2 (SSE2). The advanced dynamic execution improves speculative execution and branch prediction internal to the processor. The advanced transfer cache is 512, on-die level 2, cache with an increased bandwidth over previous micro-architectures. The floating point and multi-media units have been improved by making the registers 128 bits wide and adding a separate register for data movement. Finally, SSE2 adds 144 new instructions for double precision floating point, SIMD integer, and memory management. The mobile Pentium 4 Processor-M in the 478-pin package supports uniprocessor configurations only. The mobile Pentium 4 Processor-M includes a Thermal monitor that allows systems to be designed for anticipated processor thermals as opposed to worst case with no performance degradation expected.
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Design Guide
Table 2. Mobile Pentium 4 Processor-M in the 478-Pin Package Feature Set Overview
Feature L1 Cache L2 Cache L3 Cache Data Transfer Rate Manageability Features Package Pin Configuration Mobile Intel Pentium 4 Processor-M in the 478 Pin Package 12 KB on-die 512 KB on-die None 3.2 GB/sec Thermal Monitor 478 pin, 0.050 Micro-FCPGA
1.4.
Intel 845MP/845MZ Chipset

The Intel 845MP/845MZ chipset consists of the following main components: Mobile Intel Memory Controller Hub (MCH-M) and the Mobile Intel I/O Controller Hub 3 (ICH3-M). All these components are interconnected via an Intel proprietary interface called hub interface. The hub interface is designed into the Intel 845MP/845MZ chipset to provide efficient communication between components. Additional hardware platform features include AGP 4x mode, PC2100/PC1600 DDR System memory, Ultra ATA/100, Low Pin Count interface (LPC), integrated LAN* and Universal Serial Bus 1.1. The platform is also ACPI-compliant and supports Full-on, Stop Grant, Suspend to RAM, Suspend to Disk, and Soft-off power management states. Through the use of an appropriate LAN* connect, the platform supports Wake-on-LAN* for remote administration and troubleshooting.
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Figure 1. Typical System Block Diagram

Mobile Intel Pentium 4 Processor-M
System Bus 400MT/S (3.2 GB/sec Data Rate)

DDR200/266
4X AGP Graphic Controller
AGP 2.0
845MP/845MZ MCH-M 593 FC-BGA
PC1600/PC2100
DDR200/266
8-Bit HUB Interface
6 USB 1.1 Port
FWH
2 ATA 66/100 IDE Channels
ICH3-M 421 mBGA
LAN/HPNA
PCI Bus
MOON2
AC'97 Modem CODEC (Optional)
CardBUS
LAN
LPC Bus
SMC
SIO
KBC
1.4.1.
Intel Memory Controller Hub (MCH-M)

The Intel 845MP/845MZ MCH-M component provides the processor interface, DDR interface, AGP interface and hub interface in an Intel 845MP/845MZ chipset platform. The Intel MCH-M is in a 593-ball BGA package and has the following functionality: Supports a single Processor with a data transfer rate of 400 MHz Supports DDR-SDRAM at 100/133-MHZ operation (DDR200/266)
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Design Guide
AGTL+ host bus with integrated termination supporting 32-bit host addressing 1.5-V AGP interface with 4x SBA/data transfer and 2x/4x fast write capability 8-bit, 66-MHz,, 4x hub interface to the Intel ICH3-M
1.4.1.1.
Processor System Bus Support

AGTL+ bus driver technology (gated AGTL+ receivers for reduced power) Supports 32-bit AGTL+ bus addressing (no support for 36-bit address extension) Supports Uniprocessor (UP) systems 400 MT/s PSB support Optimized for Mobile Intel Pentium 4 Processor-M in 478-pin Micro-FCPGA package 12 deep in-order queue Supports in-order and dynamic deferred transactions Low Vtt
1.4.1.2.
Integrated System Memory DRAM Controller

Supports up to 2 SO-DIMMs Up to 1 GB using 64-Mb, 128-Mb, 256-Mb, 512-Mb technology 200/266 MHz DDR interface 64-bit data interface PC2100 and PC1600 system memory interface Supports x16 DDR device widths with Dynamic Powerdown Support for suspend to RAM (STR) and S3 Supports up to 16 simultaneous open pages Refresh Mechanism: CAS-before-RAS only Support for DIMM Serial Presence Detect (SPD) scheme via SMBus interface STR power management support via self refresh mode using CKE
1.4.1.2.1.
Accelerated Graphics Port (AGP) Interface

Supports AGP 2.0 data transfers Supports a single AGP (4X/2X/1X) device (either via a connector or on the motherboard) AGP 1.5-V Connector support only Synchronously coupled to the host with 1:2 clock ratio High priority access support Delayed transaction support for AGP reads that cannot be serviced immediately
AGP semantic traffic to the DRAM is not snooped on the PSB and is therefore not coherent with the
CPU caches
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AGP BUSY protocol. AGP Clamping and sense amp control Supports 32-deep AGP address queue.
1.4.1.3.
Packaging/Power
593-pin, FC-BGA package 1.5 V (5%) core and mixed 3.3 V, 1.5 V, 1.8 V, and AGTL+ I/O
1.4.1.4.
I/O Controller Hub (ICH3-M)

ICH3-M provides the I/O subsystem with access to the rest of the system: Upstream Accelerated Hub Architecture interface at 266 MB/s for access to the MCH-M PCI 2.2 interface (6 PCI Req/Grant Pairs) Bus Master IDE controller (supports Ultra ATA 100/66/33) USB 1.1 Controller SMBus Controller FWH Interface LPC Interface AC97 2.1 Interface Integrated System Management Controller Alert-On-LAN IRQ Controller
1.4.1.4.1.
Packaging/Power
421 BGA 3.3-V core and 1.8-V and 3.3-V standby
1.4.1.5.
Firmware Hub (FWH)

An integrated hardware Random Number Generator (RNG) Register-based locking Hardware-based locking 5 GPIs
1.4.1.5.1.
Packaging/Power
32-Pin PLCC 3.3-V core and 3.3 V/12 V for fast programming Register-based locking
1.4.2.
Bandwidth Summary
Table 3 lists the bandwidths of critical 845MP/845MZ chipset platform interfaces.
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Design Guide
Table 3. Platform Bandwidth Summary

Interface System Bus AGP Hub Interface PCI DDR-SDRAM 200/266 MHz Clock Speed (MHz) 100 66 66 33 100/133 Samples per Clock 4 4 4 1 2/2 Data Width (Bytes) 8 4 1 4 8/8 Bandwidth (MB/s) 3200 1066 266 133 1600/2100
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2.
General Design Considerations

This section documents motherboard layout and routing guidelines for Intel 845MP/845MZ platforms. This section does not discuss the functional aspects of any bus, or the layout guidelines for an add-in device. If the guidelines listed in this document are not followed, it is very important that thorough signal integrity and timing simulations are completed for each design. Even when the guidelines are followed, Intel recommends that critical signals be simulated to ensure proper signal integrity and flight time. Any deviation from the guidelines should be simulated. The trace impedance typically noted (i.e. 55 15%) is the nominal trace impedance for a 5-mil wide external trace and a 4-mil wide internal trace. That is, the impedance of the trace when not subjected to the fields created by changing current in neighboring traces. When calculating flight times, it is important to consider the minimum and maximum impedance of a trace that is based on the switching of neighboring traces. Using wider spaces between the traces can minimize this trace-to-trace coupling. In addition, these wider spaces reduce settling time. Coupling between two traces is a function of the coupled length, the distance separating the traces, the signal edge rate, and the degree of mutual capacitance and inductance. In order to minimize the effects of trace-to-trace coupling, the routing guidelines documented in this section should be followed.
2.1.
Nominal Board Stackup

The Intel 845MP/845MZ Chipset platform requires a board stackup yielding a target impedance of 55 15% with a 5-mil wide external trace and a 4-mil wide internal trace width for all interfaces.
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Design Guide
3.
3.1.
Processor System Bus Design Guidelines

Introduction
Intels Mobile Pentium 4 Processor-M is the first mobile Intel processor with the Intel NetBurst microarchitecture. The Mobile Pentium 4 Processor-M utilizes Micro Flip-Chip Pin Grid Array (MicroFCPGA) package technology, and plugs into a 478-pin, surface-mount, Zero Insertion Force (ZIF) socket, which is referred to as the mPGA478M socket. The Mobile Pentium 4 Processor-M maintains full compatibility with IA-32 software. The Mobile Pentium processors 400-MT/s Intel NetBurst microarchitecture system bus utilizes a split-transaction, deferred reply protocol like the Mobile Intel Pentium 4 Processor-M. The following layout guidelines support designs using the Mobile Intel Pentium 4 Processor-M and the Intel 845MP/845MZ chipset. Due to on-die Rtt resistors on both the processor and the chipset, additional resistors do not need to be placed on the motherboard for most PSB signals. The exception to these are RESET#, BPM[5:0]# signals which requires a 51.1 1% pull-up , and BR0 signal requires 220 5% pull-up to Vtt on the processor end of the transmission line.
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3.2.
Processor System Bus (PSB) Routing Guidelines

Table 4 summarizes the layout recommendations for mobile Pentium 4 Processor-M in the 478-pin package configurations and expands on specific design issues and their recommendations.
Table 4. System Bus Routing Summary for the Processor

Parameter Line to line spacing Processor Routing Guidelines Greater than or equal to 2:1 edge-to-edge spacing versus trace to reference plane height ratio. See Figure 1 for an illustration of this recommendation. 1.5 inches 10 inches from - pin to pin. Data signals of the same source synchronous group should be routed to the same pad-to-pad length within 0.100 inches of the associated strobes. The pad is defined as the attach point of the silicon die to the package substrate. Length must be added to the system board to compensate for package length differences. Signals in the same source synchronous group should be routed on the same layer and referenced to Vss. A data strobe and its complement should be routed within 0.025 inches of the same pad-to-pad length. The pad is defined as the attach point of the silicon die to the package substrate. Length must be added to the system board to compensate for package length differences. DSTBn/p# should be routed on the same layer as their associated data group and referenced to Vss. 1.5 inches 10 inches from pin-to-pin address signals of the same source synchronous group should be routed to the same Pad-toPad length within 0.200 inches of the associated strobes. The pad is defined as the attach point of the silicon die to the package substrate. Length must be added to the system board to compensate for package length differences. A layer transition may occur if the reference plane remains the same (Vss) and the layers are of the same configuration (all stripline or all microstrip). An address strobe and its complement should be routed within 0.200 inches of the same Pad-to-Pad length. The pad is defined as the attach point of the silicon die to the package substrate. Length must be added to the system board to compensate for package length differences. A layer transition may occur if the reference plane remains the same (Vss) and the layers are of the same configuration (all stripline or all microstrip). No length compensation is necessary. Stripline All associated signals and strobes should be routed on same layer for entire length of bus. All signals should be referenced to Vss. Ideally, layer changes should not occur for any signals. If a layer change must occur, reference plane must be Vss and the layers must all be of the same configuration (all stripline or all microstrip for example). A spacing requirement of 16-20 mils should be maintained around all clocks. 55 ohms 15% There are no length-matching routing restrictions between (or ithi ) ith th h d t dd A
Data Line lengths (agent to agent spacing)
DSTBn/p[3:0]#
Address line lengths(agent to agent spacing)
ADSTBn/p[1:0]#
Common Clock line lengths Topology Routing priorities
Clock keepout zones Trace Impedance Source Synchronous routing restriction
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Design Guide
Parameter
Processor Routing Guidelines within) either the source-synchronous data or address groups. As long as the strobe and associated line length routing guidelines are met for each group, there is no need to length-match between the groups. For example, one data group may be routed to the minimum allowable length while another data group could be routed to the maximum allowable length. Simulations have verified that the PSB will still function correctly even under this extreme condition.
Refer to the Intel 845MP or 845MZ Chipset Memory Controller Hub Mobile (MCH-M) Datasheet for MCH-M package dimensions and refer to the Intel Mobile Pentium 4 Processor-M in the 478 Pin Package Signal Integrity Models for Processor package dimensions. Figure 2. Cross-Sectional View of 2:1 Ratio Reference Plane(Vss) x trace 2x
NOTE: This is the edge-to-edge trace spacing versus trace to reference plane height.
trace
A trace spacing to height above reference plane ratio of 2 to 1 ensures a low crosstalk coefficient. All the effects of crosstalk are difficult to simulate. The timing and layout guidelines for the Processor have been created with the assumption of 2:1 trace spacing to height above reference plane ratio. A smaller ratio would have an unpredictable impact due to crosstalk.
3.2.1.
Return Path Evaluation

The return path is the route current takes to return to its source. It may take a path through ground planes, power planes, other signals, integrated circuits, vias, VRMs etc. Think of the return path as following a path of least resistance back to the original source. Discontinuities in the return path often have signal integrity and timing effects that are similar to the discontinuities in the signal conductor. Therefore, the return paths need to be given similar considerations. A simple way to evaluate return path parasitic inductance is to draw a loop that traces the current from the driver through the signal conductor to the receiver, and then back through the ground/power plane to the driver again. The smaller the area of the loop, the lower the parasitic inductance will be. The following sets of return path rules apply: Always trace out the return current path and provide as much care to the return path as the path of the signal conductor. Decoupling capacitors do not adequately compensate for a plane split. Do not allow splits in the reference planes in the path of the return current. Do not allow routing of signals on the reference planes near system bus signals. Maintain Vss as a reference plane for all system bus signals. Do not route over via anti-pads or socket anti-pads.
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3.2.2.
GTLREF Layout and Routing Recommendations

There are four AGTL+ GTLREF pins on the processor that are used to set the reference voltage level for the AGTL+ signals (GTLREF). Because all of these pins are connected inside the processor package, the GTLREF voltage only needs to be supplied to one of the four pins. The other three pins can be left unconnected.
Figure 3. GTLREF Routing

VCC_CPU
49.9 ohms 1% L1 = 1.5" max

Tline
pin
100 ohms 1%
1 F
220 pF
The processor must have one dedicated voltage divider. Decouple the voltage divider with a 1-F capacitor. Keep the voltage divider within 1.5 inches of the GTLREF pin Decouple the pin with a high frequency capacitor (such as a 220 pF 603) as close to the pin as possible Keep signal routing at least 10 mils separated from the GTLREF routes. Use a minimum of a 7-mil trace for routing. Do not allow signal lines to use the GTLREF routing as part of their return path (i.e., do not allow the GTLREF routing to create splits or discontinuities in the reference planes of the system bus signals).
3.3.
3.3.1.
Processor Configuration
Mobile Intel Pentium 4 Processor-M in the 478 -Pin Package Configuration
This section provides more details for routing Mobile Intel Pentium 4 Processor-M based systems. For proper operation of the processor and the Intel 845MP/845MZ chipset, it is necessary that the system designer meet the timing and voltage specifications of each component. The following recommendations
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Design Guide
are Intels best guidelines based on extensive simulation and experimentation that make assumptions, which may be different than an OEM's system design. The most accurate way to understand the signal integrity and timing of the system bus in your platform is by performing a comprehensive simulation analysis. It is conceivable that adjustments to trace impedance, line length, termination impedance, board stackup and other parameters can be made that improve system performance. Refer to the Mobile Intel Pentium 4 Processor-M Datasheet for a system bus signal list, signal types and definitions.
3.4.
General Topology and Layout Guidelines

The following topology and layout guidelines are preliminary and subject to change. The guidelines are derived from empirical testing with very preliminary Intel 845MP/845MZ Chipset package models.
3.4.1.
Design Recommendations
Below are the design recommendations for the data, address, strobes, and common clock signals. For the following discussion, the pad is defined as the attach point of the silicon die to the package substrate. DATA: Data signals of the same source synchronous group should be routed to the same pad-to-pad length within 0.100 inches of the associated strobes. As a result, additional trace will be added to some data nets on the system board in order for all trace lengths within the same data group to be the same length ( 0.100 inches) from the pad of the processor to the associated pad of the chipset.
Equation 1. Calculation to Determine Package Delta Addition to Motherboard Length for UP Systems
delta net,strobe = (cpu_pkglen net cpu_pkglen strobe* ) + (cs_pkglen net cs_pkglen strobe )
Refer to the Intel 845MP or 845MZ Chipset Memory Controller Hub Mobile (MCH-M) datasheet for MCH-M package dimensions and refer to the Intel Mobile Pentium 4 Processor-M in the 478 Pin Package/ Signal Integrity Models for package dimensions. * Strobe package length is the average of the strobe pair. ADDRESS: Address signals follow the same rules as data signals except they should be routed to the same pad-topad length within 0.200 inches of the associated strobes. Address signals may change layers if the reference plane remains Vss. STROBE: A strobe and its complement should be routed to a length equal to their corresponding data group's mean pad-to-pad length 0.025 inches COMMON CLOCK: Common clock signals should be routed to a minimum pin-to-pin motherboard length of 1.5 inches and a maximum motherboard length of 10.0 inches.
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Source synchronous groups and associated strobes should be routed on the same layer for the entire length of the bus. This results in a significant reduction of the flight time skew since the dielectric thickness, line width, and velocity of the signals will be uniform across a single layer of the stackup. There is no guarantee of a relationship of dielectric thickness, line width, and velocity between layers. Figure 4. Processor Topology
Processor Pad
Length L1
MCH Pad
Package trace Motherboard PCB trace
3.4.2.
Source Synchronous (SS) Signals

Routing Length (pin-to-pin) L1 Topology CPU D[63:0]# DBI[3:0]# DSTP[3:0]# DSTBN[3:0]# NOTE: Intel 845MP/845MZ HD[63:0]# DBI[3:0] HDSTP[3:0]# HDSTBN[3:0]# Stripline Stripline Stripline Stripline Max (inches) 10.0 10.0 10.0 10.0 Min (inches) 1.5 1.5 1.5 1.5
Table 5. Processor System Bus Data Signal Routing Guidelines

Signal Names Nominal Impedance (ohms) Width & spacing (mils)
55 15% 55 15% 55 15% 55 15%
4&8 4&8 4&8 4&8
The Data signals within each group must be routed to within 0.100 inches of its associated reference strobe. The complement strobe must be routed to within 0.025 inches of the associate reference strobe. All traces within each signal group must be routed on the same layer (required). Intel recommends that length of the strobes be centered to the average length of associated data or address traces to maximize setup/hold time margins.
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Design Guide
Table 6. Processor System Bus Address Signal Routing Guidelines

Signal Names Topology CPU A[35:3]# REQ[4:0]# ADSTB[1:0]# NOTE: Intel 845MP/845MZ HA[35:3]# HREQ[4:0]# HADSTB[1:0]# Stripline Stripline Stripline Max (inches) 10.0 10.0 10.0 Min (inches) 1.5 1.5 1.5 Routing Length (pin-to-pin) L1 Nominal Impedance (ohms) Width & Spacing (mils)
55 15% 55 15% 55 15%
4&8 4&8 4&8
The Address signals within each group must be routed to within 0.200 of its associated strobe. . All traces within each signal group must be routed on the same layer (required). Intel recommends that the length of the strobes be centered to the average length of associated data or address traces to maximize setup/hold time margins.
Figure 5. SS Topology for Address and Data
Processor
Vtt Pin Pad Pin Pad
Vtt
Chipset
L1
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31
3.4.3.
Common Clock (CC) AGTL+ Signals

Routing Trace Length (Pin-to-Pin) Topology CPU RESET# BR0# BNR# REQ[4:0]# BPRI# DEFER# LOCK# TRDY# DRDY# ADS# DBSY# HIT# HITM# RS[2:0]# NOTE: Intel 845MP/845MZ CPURST# BR0# BNR# HREQ[4:0]# BPRI# DEFER# HLOCK# HTRDY# DRDY# ADS# DBSY# HIT# HITM# RS[2:0]# Stripline Stripline Stripline Stripline Stripline Stripline Stripline Stripline Stripline Stripline Stripline Stripline Stripline Stripline Max (inches) 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 Min (inches) 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5
Table 7. Processor System Bus Control Signal Routing Guidelines

Signal Names Nominal Board Impedance (ohms) Width & spacing (mils)
55 15% 55 15% 55 15% 55 15% 55 15% 55 15% 55 15% 55 15% 55 15% 55 15% 55 15% 55 15% 55 15% 55 15%
4&8 4&8 4&8 4&8 4&8 4&8 4&8 4&8 4&8 4&8 4&8 4&8 4&8 4&8
Trace width of 4 mils and trace spacing of 8 mils within signal groups. Entire trace for each signal routed on one layer (recommended) RESET# and BR0# are CC AGTL+ signals without ODT (On die termination). For these signals Rtt should be placed near CPU: L2<= 0.5 inches. Rtt = 51.1 1%. Routing these signals to 4.0 inches 0.5 inches should maximize the setup and hold margin parameters while adhering to expected mobile solution design constraints.
3.4.3.1.
CC Topology with ODT

ODT Compensation Resistors:
Pentium 4: R_comp = 51.1 1% ohms (Pins L24 and P1 Pulled to ground through resistor) Intel 845MP/845MZ: R_comp = 24.9 1% ohms (Pins AC2 and AC13 - Pulled to ground through resistor)
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Design Guide
Figure 6. CC Topology With ODT
Processor
Vtt Pin Pad Pin Pad
Vtt
Chipset
L1
Figure 7. CC Topology Without ODT
Processor
Pad
Vtt
Vtt Pin Pad
Chipset
Pin
L2
L1
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3.4.4.
Signal Names FERR# IERR#
PWRGOOD and Asynchronous AGTL+ Signals

Description Topology # 1 1 1 1 2 2 2 2 2 2 2 CPU IO Type O O O O I I I I I I I Output Output Buffer Type OD AGTL+ OD AGTL+ OD AGTL+ OD AGTL+ CMOS CMOS CMOS CMOS CMOS CMOS CMOS Output Power Well N/A N/A N/A N/A CPU I/O (VCC_CPU) CPU I/O (VCC_CPU) CPU I/O (VCC_CPU) CPU I/O (VCC_CPU) CPU I/O (VCC_CPU) CPU I/O (VCC_CPU) CPU I/O (VCC_CPU) CPU I/O (VCC_CPU) CPU I/O (VCC_CPU) N/A Input Input Power Well Main I/O (3.3V) Vcc_Receiver Vcc_Receiver Vcc_Receiver N/A N/A N/A N/A N/A N/A N/A
Table 8. Asynchronous AGTL+ Nets
Floating point error Internal error Thermal sensor Thermal sensor Local interrupts Local interrupts Deep sleep Sleep Processor stop clock Ignore next numeric error System management interrupt Address 20 mask Processor initialize GHI#
CPU CPU CPU CPU ICH3-M ICH3-M ICH3-M ICH3-M ICH3-M ICH3-M ICH3-M
ICH3-M System Receiver System Receiver System Receiver CPU CPU CPU CPU CPU CPU CPU
PROCHOT# THRMTRIP# LINT1/INTR LINT0/NMI DPSLP# SLP# STPCLK# IGNNE# SMI#
A20M# INIT# CPUPREF#
2 2B 2
I I 1
ICH3-M ICH3-M ICH3-M
CMOS CMOS OD CMOS
CPU CPU, FWH CPU
N/A N/A, 3.3 V N/A
PWRGOOD
System power good
2A
ICH3-M
OD CMOS
N/A
CPU
N/A
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Design Guide
All signals must meet the AC and DC specifications as documented in the Mobile Intel Pentium Processor-M Datasheet. In addition, several design guidelines should be implemented when designing your platform with these signals. They are:
Although the asynchronous signals are not high frequency in nature, they nevertheless need to be protected from crosstalk and other sources of noise in the same fashion as the common-clock and source-synchronous signals. Therefore, the same line-to-line spacing ratio of 2:1. Figure 2 need also apply. Due to the long trace lengths usually associated with these signals, Intel recommends that no electrical stubs exist and that probing be done at the via nearest to the receiver in order to maintain signal integrity. These signals should also remain ground-referenced the entire length of the trace. If probing is required, active FET probes are recommended as they have a much lower effective capacitance than passive probes. This, again, is to maintain proper signal integrity and to prevent any outside influences that may detrimentally affect the system. On critical signals, such as DPSLP#, which is used for internal clock control, it may be desirable to implement additional precautions, such as ground shielding traces or wider keepout zones in order to assure proper functionality.
3.4.4.1.
CPU THRMTRIP# Circuit Recommendation

The following sections describe the topologies and layout recommendations for the miscellaneous signals. In the Figure 8 the circuit effectively latches the low state of THRMTRIP# via the D Flip-Flop once the processor has driven THRMTRIP# to a low state. Operation can be restored if the system power is cycled (power off/on system). R6 is included if the designer wishes to disable THRMTRIP# and remove R2, R3, Q1, R4, U1, R1, and R5 and can be included as a no-stuff. Please refer to customer reference board schematics in Section 13 for all referenced connections.
Figure 8. THRMTRIP# Circuit Recommendation

VCC_VID R2 56 +V3.3 S R3 10K VCC_VIDPWRGD(U13-4) +V3.3 S R1 10K R6 10K
PRE D R4 10K CLK CLR Q1 2N3904 Q Q
H_THRMTRIP# U11-9
+V3.3 S R5 10K
H_THRMTRIP_S# CPU Ball (A2)
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3.4.4.1.1.
Topology #1: Asynchronous AGTL+ Signals Driven by the Processor; FERR#, IERR#, PROCHOT# and THRMTRIP#
These signals should adhere to the following routing and layout recommendations. Figure 9 illustrates the recommended topology. If THRMTRIP# and PROCHOT# are routed to external logic, voltage translation may be required to avoid excessive voltage levels at the processor and to meet input thresholds for the external logic.
Figure 9. Routing Illustration for FERR#, IERR#, PROCHOT#, and THRMTRIP#

Vtt_CPU Rtt_CPU CPU ICH3-M (or sys. receiver) L2
Voltage Translator
Vcc_Rcvr Rtt_Rcvr
L2 L3
L3
L1
Note:
If the design is not using the recommended THRMTRIP# latch circuit in Figure 9, THRMTRIP# can be routed through a Voltage Translator to a system logic that can provide the equivalent latching function.
Table 9. Layout Recommendations for Miscellaneous Signals Topology 1

L1 1.5" - 14.0" L2 1.1" max L3 3.0" max Rtt Rtt_CPU = 56 ohms 5% Rtt_Rcvr = 300 ohms 5%
3.4.4.1.2.
Topology #2, #2A: PWRGOOD and Asynchronous AGTL+ Signals Driven by ICH3-M
Top. #2 signals: LINT1/INTR, LINT0/NMI, CPUPERF#, DPSLP#, SLP#, STPCLK#, IGNNE#, SMI# and A20M#. Top. #2A signal: PWRGOOD. These signals should adhere to the following routing and layout recommendations. Figure 10 illustrates the recommended topology.
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Design Guide
Figure 10. Routing Illustration for LINT1/INTR, LINT0/NMI, DPSLP#, SLP#, STPCLK#, IGNNE#, SMI# and A20M#, CPUPERF#, and PWRGOOD- Topology 2, 2A
Vtt_CPU Rtt_CPU
CPU ICH3-M
L2 L3 L1
L2
Table 10. Layout Recommendations for Miscellaneous Signals Topology 2, 2A

L1 1.5" - 14.0" L2 1.1" max L3 3.0" max Rtt Rtt_#2 = 200 ohms 5% Rtt_#2A = 300 ohms 5%
3.4.4.1.3.
Topology #2B: PWRGOOD and Asynchronous AGTL+ Signals Driven by ICH3-M to Both CPU and FWH; INIT#
These signals should adhere to the following routing and layout recommendations. Figure 11 illustrates the recommended topology.
Figure 11. Routing Illustration INIT#

Vtt_CPU Rtt_CPU CPU ICH3-M FWH Vcc_FWH Rtt_FWH
L3
L1
Voltage Translator Refer to Fig. 12
L2
L2
L2 L3
L1
Table 11. Layout Recommendations for Miscellaneous Signals Topology 2B

L1 1.5" - 14.0" L2 1.1" max L3 3.0" max Rtt Rtt_CPU = 200 5% Rtt_FWH= 300 5%
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3.4.4.2.
Voltage Translator Circuit

This recommended Voltage translator circuit should be applied to topologies #1 and #2B shown in Section 3.4.4.1.1 and 3.4.4.1.3.
Figure 12. Voltage Translator Circuit of Topology#1 and #2B
Vcc of Receiver
470 ohm +/- 5%
To Receiver
3904
From Driver
470 ohm +/- 5% 3904
3.5.
Note:
ITP Debug Port

The Debug Port design information has been moved! This includes all information necessary to develop a Debug Port on this platform, including electrical specifications, mechanical requirements, and all InTarget Probe (ITP) signal layout guidelines. Please reference the Intel Pentium 4 Debug Port Design Guide and the ITP700 Debug Port Design Guide, which can be found on http://developer.intel.com/design/Xeon/guides/249679.htm, for the design of your platform. Refer to the ITP700 Debug Port Design Guide for further information Debug Tools Specifications.
3.5.1.1.
Logic Analyzer Interface (LAI)

Intel is working with two logic analyzer vendors to provide logic analyzer interfaces (LAIs) for use in debugging the Mobile Intel Pentium 4 Processor-M system. Tektronix* and Agilent* should be contacted to get specific information about their logic analyzer interfaces. The following information is general in nature. Specific information must be obtained from the logic analyzer vendor. Due to the complexity of the Mobile Pentium 4 Processor-M system, the LAI is critical in providing the ability to probe and capture system bus signals. There are two sets of considerations to keep in mind when designing a Mobile Pentium 4 Processor-M that use LAI: mechanical and electrical.
3.5.1.1.1.
Mechanical Considerations
The LAI is installed between the processor socket and the Mobile Pentium 4 processor. The LAI pins plug into the socket, while the Mobile Pentium 4 Processor-M in the 478-pin package plugs into a socket on the LAI. Cabling that is part of the LAI egresses the system to allow an electrical connection between the Mobile Pentium 4 Processor-M and a logic analyzer. The maximum volume occupied by the LAI, known as the keep-out volume, as well as the cable egress restrictions, should be obtained from the logic analyzer vendor. System designers must make sure that the keep-out volume remains unobstructed inside the system. Note that it is possible that the keep-out volume reserved for the LAI may include space
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Design Guide
normally occupied by the Mobile Pentium 4 Processor-M heat sink. If this is the case, the logic analyzer vendor will provide a cooling solution as part of the LAI.
3.5.1.1.2.
Electrical Considerations
The LAI will also affect the electrical performance of the system bus; therefore, it is critical to obtain electrical load models from each of the logic analyzers to be able to run system level simulations to prove that their tool will work in the system. Contact the logic analyzer vendor for electrical specifications and load models for the LAI solution they provide.
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4.
4.1.
Processor Power Requirements

General Description
The IMVP-III Design Guide defines the electrical requirements for the DC-to-DC Voltage Regulator for the Mobile Pentium 4 Processor-M that features Intel SpeedStep technology in a Micro-FCPGA package. Please contact your Field Representative for more information.
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Design Guide
4.2.
Power Delivery Architectural Block Diagram

.
VDC V_5 V_3
Figure 13. Voltage Regulator Block Diagram
STP_CPU# DPRSLPVR VREF IMVP-III Processor Core Voltage Regulator

VID[0..4]
VDPRSLP
VR_ON
VCC
VCC
VTT VCC
VID
CPU_PWRGOOD
Mobile Intel Pentium 4 Processor-M

VSSA VCCA LC Filter
V_3
VVID
PWRGOOD
ICH3-M ChipSet
VR_ON
VID (1.2V) Voltage Regulator
PWRGOOD_VID
4.3.
4.3.1.
Processor Phase Lock Loop Design Guidelines

Filter Specifications for VCCA, VCCIOPLL, and VSSA
VCCA and VCCIOPLL are power sources required by the PLL clock generators on the processor silicon. Since these PLLs are analog in nature, they require quiet power supplies for minimum jitter. Jitter is detrimental to the system: it degrades external I/O timings as well as internal core timings (i.e., maximum frequency). To prevent this degradation these supplies must be low pass filtered from VCC_VID. The Design Guide 41
general desired filter topology is shown in Figure 14. Not shown in the core is parasitic routing and excluded from the external circuitry are parasitics associated with each component.
Figure 14. Typical VCCIOPLL, VCCA, and VSSA Power Distribution
VCC_VID
4.7 H CA 33 F
VCCA
Motherboard
c2
1 F
PLLs Processor Core
pkg
VSSA VCCIOPLL
CIO 33 F 4.7 H
The function of the filter is two-fold. It protects the PLL from external noise through low-pass attenuation. It also protects the PLL from internal noise through high-pass filtering. In general, the lowpass description forms an adequate description for the filter. For simplicity this document will address the recommendation for the VCCA filter design. The same characteristics and design approach is applicable for the VCCIOPLL filter design.
Note:
The 1-F package capacitor in Figure 14 does not exist on the Mobile Intel Pentium 4 Processor-M in the 478-pin package. It is present for the Mobile Intel Pentium 4 Processor-M only. The AC low-pass recommendation, with input at VCC_VID and output measured across the capacitor (CA or CIO in Figure 14), is as follows:
< 0.2 dB gain in pass band < 0.5 dB attenuation in pass band < 1 Hz (see DC drop in next set of requirements) 34 dB attenuation from 1 MHz to 66 MHz 28 dB attenuation from 66 MHz to core frequency
The filter recommendation (AC) is graphically shown in Figure 15.
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Design Guide
Figure 15. Filter Recommendation

0.2 dB 0 dB -0.5 dB forbidden zone
-28 dB -34 dB forbidden zone
DC
1 Hz
fpeak
1 MHz
66 MHz
fcore
passband
NOTES: 1. Diagram not to scale. 2. No specification for frequencies beyond fcore (core frequency). 3. fpeak, if existent, should be less than 0.05 MHz.
high frequency band
Other recommendations:
Capacitors for the filter can be any value between 22 F and 100 F as long components with ESL 5 nH and ESR < 0.3 are used. Values of either 4.7 H or 10 H may be used for the inductor. Use shielded type inductors to minimize magnetic pickup Filter should support DC current > 60 mA DC voltage drop from VCC_CPU to VCCA should be < 60 mV In order to maintain a DC drop of less than 60 mV, the total DC resistance of the filter from VCC_VID to the processor socket should be a maximum of 1 .
Other routing requirements:

C should be within 600 mils of the VCCA and VSSA pins. An example of the component placement is shown in Figure 16 VCCA route should be parallel and next to VSSA route (minimize loop area) A minimum of a 12-mil trace should be used to route from the filter to the processor pins. L should be close to C
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Figure 16. Example Component Placement for PLL Filter
4.4.
Voltage and Current

A mobile processor core regulator supplies the required voltage and current to a single processor. Refer to the IMVP-III Mobile Processor Core Voltage Regulator Specification Design Guide (contact your Field Representative) for the load line specification and implementation features.
4.4.1.
Voltage Identification
Refer to the IMVP-III Mobile Processor Core Voltage Regulator Specification Design Guide (contact your Field Representative) for the load line specification and implementation features.
4.4.2.
4.4.2.1.
VCC Power Sequencing

Core Converter Soft Start Timer
The main purpose of a soft start timer is to control the ramp-up time of the core voltage in order to reduce the initial in-rush current on the supply input voltage (battery) rail. The soft start circuit must not allow the VCC power plane voltage to rise too fast.
4.4.2.2.
Power On/Off Sequencing

For more information please refer to the IMVP-III Mobile Processor Core Voltage Regulator Specification Design Guide for the actual specifications (contact your Field Representative).
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Design Guide
Figure 17. Power On Sequencing Diagram

VID_ON VVID VID[4..0] PWRGOOD_VID VCC PWRGOOD RESET#
Figure 18. Power Off Sequencing Diagram
VID_ON VVID PWRGOOD_VID VCC PWRGOOD RESET#
4.5.
Voltage Regulator Design Recommendations

For more information please refer to the IMVP-III Mobile Processor Core Voltage Regulator Specification Design Guide for the actual specifications (contact your Field Representative). The following section describes some guidelines for the design of the voltage regulator in terms of design topology and component selection. This is done to ensure design and component compatibility.
4.6.
Processor Decoupling Recommendation

Intel recommends proper design and layout of the system board bulk and high frequency decoupling capacitor solution to meet the transient tolerance at the processor socket pins. To meet the transient
Design Guide
45
response of the processor, it is necessary to properly place bulk and high frequency capacitors close to the processor power and ground pins.
4.6.1.
Transient Response
The inductance of the motherboard power planes slows the voltage regulators ability to respond quickly to a current transient. Decoupling a power plane can be broken into several independent parts. The closer to the load the capacitor is placed, the more stray inductance is bypassed. By bypassing the inductance of leads, power planes, etc., less capacitance is required. However, areas closer to the load have less room for capacitor placement. Therefore, tradeoffs must be made. The processor causes very large switching transients. These sharp surges of current occur at the transition between low power states and the normal operating states. It is the responsibility of the system designer to provide adequate high frequency decoupling to manage the highest frequency components of the current transients. Larger bulk storage capacitors supply current during longer lasting changes in current demand. All of this power bypassing is required due to the relatively slow speed at which a DC-to-DC converter can respond. A typical voltage converter has a reaction time on the order of 1 to 100 s while the processors current steps are on the order of 30 to 40 ns. High Frequency decoupling is typically done with ceramic capacitors with a very low ESR. Because of there low ESR, these capacitors can act very quickly to supply current at the beginning of a transient event. However, because the ceramic capacitors are small, i.e. they can only store a small amount of charge, Bulk capacitors are needed too. Bulk capacitors are typically polarized with high capacitance values and unfortunately higher ESRs. The higher ESR of the Bulk capacitor limits how quickly it can respond to a transient event. The Bulk and HF capacitors working together can supply the charge needed to stay in regulator before the regulator can react during a transient. A load change transient occurs when coming out of or entering a low power state. These are not only quick changes in current demand, but also long lasting average current requirements. This occurs when the processor enters different power modes by stopping and starting its internal clock. The processor current requirements can change by as much as 70% (10%) of the maximum current very quickly.
4.6.2.
Processor Voltage Plane

Power must be distributed as a plane. This plane can be constructed as an island on a layer used for other signals, on a supply plane with other power islands, or as a dedicated layer of the PCB. Processor power should never be distributed by traces alone. Intel recommends that all layers of the stack-up be used for processor power and ground routing. Due to the fact that the processor voltage is unique to most system designs, a voltage island is the most cost-effective means of distributing power to the processor. This island from the source of power to the load should not have any breaks so as to minimize inductance in the plane. It should also completely surround all of the pins of the source and all of the pins in the power pin area of the processor. The bulk capacitors and the high frequency capacitors should be placed as close to the processor as possible and in the path of current flow. The processor socket has 478 pins with 50-mil pitch. The routing of these signals, power, and ground pins will require many vias. These vias cause a Swiss Cheese effect in the power and ground planes beneath the processor resulting in increased inductance and resistance of these planes. This increase in impedance can choke off the high current carrying channel of the voltage regulator. In order to provide the best path through the via field, it is recommended that vias are shared for every two processor ground pins.
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Design Guide
4.6.3.
High Frequency Decoupling

System motherboards should include high frequency decoupling capacitors as close to the socket power and ground pins as possible. A total of thirty-eight 10.0-F, X5R/X7R, 1206 package, ceramic capacitors are recommended to provided high frequency decoupling for the processor. Ten of these 1206 capacitors should be placed in the socket cavity area. Fourteen of these 1206 capacitors should be placed on the north side of the cavity and fourteen of these 1206 capacitors should be placed on the south side of the cavity. See Figure 19 for an example on placement of the high frequency decoupling capacitors.
Figure 19. Processor High Frequency Decoupling Placement Example
.
VCC VSS
4.6.4.
Bulk Decoupling
System motherboards should include bulk-decoupling capacitors as close to the processor socket power and ground pins as possible (<1.0 inch). The maximum Equivalent Series Resistance (ESR) should be equal to or less than 2.5 m.
4.7.
Thermal Power Dissipation

Power dissipation has traditionally been a thermal/mechanical challenge for mobile system designers. The amount of current required from the processor power delivery circuit and the heat generated by processors has increased as processor frequencies go up and the silicon process geometry shrinks. The package of any integrated device can only dissipate so much heat into the surrounding environment. The temperature of a device, such as a processor power delivery circuit-switching transistor, is a balance of
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heat being generated by the device and its ability to shed heat either through radiation into the surrounding air or by conduction into the circuit board. Increased power will effectively raise the temperature of the processor power delivery circuits. Switching transistor die temperatures can exceed the recommended operating value if the heat cannot be removed from the package effectively. As the current demands for higher frequency and performance processors increase, the amount of power dissipated, i.e., heat generated, in the processor power delivery circuit is becoming of concern for mobile system. The high input voltage, low duty factor inherent in mobile power supply designs leads to increasing power dissipation losses in the output stage of the traditional buck regulator topology that is used in the mobile industry today. These losses can be attributed to three main areas of the processor power delivery circuit: the switching MOSFET dissipates a significant amount of power during switching of the top control MOSFET; power dissipation resulting from drain to source resistance (RDS(ON) ) DC losses across the bottom synchronous MOSFET; and the power dissipation generated through the magnetic core and windings of the main power inductor. There has been significant improvement in the switching MOSFET technology to lower gate charge of the control MOSFET allowing them to switch faster thus reducing switching losses. Improvements in lowering the RDS(ON) parametric of the synchronous MOSFET have resulted in reduced DC losses. The Direct Current Resistance (DCR) of the power inductor has been reduced, as well, to lower the amount of power dissipation in the circuits magnetic. These technology improvements by themselves are not sufficient to effectively remove the heat generated during the high current demand and tighter voltage regulation required by todays mobile processors. There are several mechanisms for effectively removing heat from the package of these integrated devices. Some of the most common methods are listed below.
Attaching a heat spreader or heat pipe to the package with a low thermal co-efficient bonding material Adding and/or increasing the copper fill area attached to high current carrying leads Adding or re-directing air flow to flow across the device Utilize multiple devices in parallel, as allowed, to reduce package power dissipation Utilizing newer/enhanced technology and devices to lower heat generation but with equal or better performance
For the mobile designer, these options are not always available or economically feasible. The most effective method of thermal spreading and heat removal, from these devices, is to generate airflow across the package AND add copper fill area to the current carrying leads of the package. The processor power delivery topology can also be modified to improve the thermal spreading characteristic of the circuit and dramatically reduce the power dissipation requirements of the switching MOSFET and inductor. This topology referred to as multi-phase, provides an output stage of the processor regulator consisting of several smaller buck inductor phases that are summed together at the processor. Each phase can be designed to handle and source a much smaller current. This can reduce the size, quantity, and rating of the components needed in the design. This can also decrease the cost and PCB area needed for the total solution. The implementation options for this topology are discussed in the next section.
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Design Guide
4.8.
Voltage Regulator Topology

4.9.
Voltage Regulator Layout Recommendations

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49
Table 12. Intel Mobile Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Package Lengths
Processor lengths Signal Processor ball Length (inches) Signal MCH-M Lengths MCH-M ball Length (inches)
Address Group 0 ADSTB#[0] A#[03] A#[04] A#[05] A#[06] A#[07] A#[08] A#[09] A#[10] A#[11] A#[12] A#[13] A#[14] A#[15] A#[16] REQ#[0] REQ#[1] REQ#[2] REQ#[3] REQ#[4] L5 K2 K4 L6 K1 L3 M6 L2 M3 M4 N1 M1 N2 N4 N5 J1 K5 J4 J3 H3 0.219 0.392 0.281 0.170 0.435 0.330 0.157 0.374 0.328 0.261 0.406 0.420 0.362 0.252 0.204 0.447 0.232 0.294 0.357 0.360 HADSTB0# HA03# HA04# HA05# HA06# HA07# HA08# HA09# HA10# HA11# HA12# HA13# HA14# HA15# HA16# HREQ0# HREQ1# HREQ2# HREQ3# HREQ4# R5 T4 T5 T3 U3 R3 P7 R2 P4 R6 P5 P3 N2 N7 N3 U6 T7 R7 U5 U2 0.530 0.518 0.434 0.728 0.577 0.551 0.359 0.643 0.533 0.397 0.463 0.576 0.660 0.407 0.570 0.402 0.350 0.393 0.475 0.599
Address Group 1 ADSTB#[1] A#[17] A#[18] A#[19] A#[20] A#[21] A#[22] A#[23] A#[24] A#[25] A#[26] R5 T1 R2 P3 P4 R3 T2 U1 P6 U3 T4 0.220 0.477 0.399 0.316 0.257 0.333 0.394 0.470 0.160 0.399 0.294 HADSTB1# HA17# HA18# HA19# HA20# HA21# HA22# HA23# HA24# HA25# HA26# N6 K4 M4 M3 L3 L5 K3 J2 M5 J3 L2 0.438 0.550 0.580 0.648 0.604 0.521 0.624 0.685 0.509 0.636 0.648
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Design Guide
Processor lengths Signal A#[27] A#[28] A#[29] A#[30] A#[31] Processor ball V2 R6 W1 T5 U4 Length (inches) 0.423 0.177 0.491 0.232 0.293 Data Group 0 DSTBN#[0] DSTBP#[0] D#[00] D#[01] D#[02] D#[03] D#[04] D#[05] D#[06] D#[07] D#[08] D#[09] D#[10] D#[11] D#[12] D#[13] D#[14] D#[15] DBI#[0] E22 F21 B21 B22 A23 A25 C21 D22 B24 C23 C24 B25 G22 H21 C26 D23 J21 D25 E21 0.465 0.362 0.434 0.494 0.559 0.634 0.407 0.411 0.565 0.495 0.537 0.612 0.298 0.231 0.616 0.485 0.209 0.572 0.309 Data Group 1 DSTBN#[1] DSTBP#[1] D#[16] D#[17] D#[18] D#[19] D#[20] D#[21] K22 J23 H22 E24 G23 F23 F24 E25 0.312 0.313 0.281 0.481 0.365 0.428 0.449 0.521 HDSTBN1# HDSTBP1# HD16# HD17# HD18# HD19# HD20# HD21# HDSTBN0# HDSTBP0# HD00# HD01# HD02# HD03# HD04# HD05# HD06# HD07# HD08# HD09# HD10# HD11# HD12# HD13# HD14# HD15# DBI0# Signal HA27# HA28# HA29# HA30# HA31#
MCH-M Lengths MCH-M ball H4 N5 G2 M6 L7 Length (inches) 0.634 0.472 0.792 0.449 0.365
AD4 AD3 AA2 AB5 AA5 AB3 AB4 AC5 AA3 AA6 AE3 AB7 AD7 AC7 AC6 AC3 AC8 AE2 AD5
0.759 0.801 0.649 0.564 0.531 0.678 0.628 0.635 0.623 0.468 0.802 0.495 0.609 0.548 0.579 0.709 0.590 0.856 0.637
AE6 AE7 AG5 AG2 AE8 AF6 AH2 AF3
0.693 0.638 0.845 0.904 0.663 0.759 0.965 0.798
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Processor lengths Signal D#[22] D#[23] D#[24] D#[25] D#[26] D#[27] D#[28] D#[29] D#[30] D#[31] DBI#[1] Processor ball F26 D26 L21 G26 H24 M21 L22 J24 K23 H25 G25 Length (inches) 0.521 0.605 0.187 0.535 0.412 0.171 0.254 0.410 0.323 0.481 0.458 Signal HD22# HD23# HD24# HD25# HD26# HD27# HD28# HD29# HD30# HD31# DINVB_1
MCH-M Lengths MCH-M ball AG3 AE5 AH7 AH3 AF4 AG8 AG7 AG6 AF8 AH5 AG4 Length (inches) 0.898 0.709 0.863 0.904 0.794 0.789 0.785 0.785 0.711 0.892 0.888
Data Group 2 DSTBN#[2] DSTBP#[2] D#[32] D#[33] D#[34] D#[35] D#[36] D#[37] D#[38] D#[39] D#[40] D#[41] D#[42] D#[43] D#[44] D#[45] D#[46] D#[47] DBI#[2] K22 J23 M23 N22 P21 M24 N23 M26 N26 N25 R21 P24 R25 R24 T26 T25 T22 T23 P26 0.252 0.264 0.291 0.227 0.179 0.361 0.273 0.448 0.431 0.386 0.161 0.332 0.373 0.320 0.411 0.378 0.219 0.269 0.438 HDSTBN2# HDSTBP2# HD32# HD33# HD34# HD35# HD36# HD37# HD38# HD39# HD40# HD41# HD42# HD43# HD44# HD45# HD46# HD47# DINVB_2 AE11 AD11 AC11 AC12 AE9 AC9 AE10 AD9 AG9 AC10 AE12 AF10 AG11 AG10 AH11 AG12 AE13 AF12 AH9 0.595 0.532 0.514 0.565 0.652 0.566 0.605 0.635 0.724 0.543 0.558 0.666 0.703 0.705 0.754 0.669 0.563 0.596 0.775
Data Group 3 DSTBN#[3] DSTBP#[3] W22 W23 0.302 0.303 HDSTBN3# HDSTBP3# AC15 AC16 0.443 0.395
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Design Guide
Processor lengths Signal D#[48] D#[49] D#[50] D#[51] D#[52] D#[53] D#[54] D#[55] D#[56] D#[57] D#[58] D#[59] D#[60] D#[61] D#[62] D#[63] DBI#[3] Processor ball U26 U24 U23 V25 U21 V22 V24 W26 Y26 W25 Y23 Y24 Y21 AA25 AA22 AA24 V21 Length (inches) 0.424 0.329 0.269 0.386 0.174 0.246 0.343 0.457 0.460 0.429 0.339 0.386 0.214 0.422 0.268 0.387 0.202 Signal HD48# HD49# HD50# HD51# HD52# HD53# HD54# HD55# HD56# HD57# HD58# HD59# HD60# HD61# HD62# HD63# DINVB_3
MCH-M Lengths MCH-M ball AG13 AH13 AC14 AF14 AG14 AE14 AG15 AG16 AG17 AH15 AC17 AF16 AE15 AH17 AD17 AE16 AD15 Length (inches) 0.668 0.712 0.412 0.548 0.621 0.520 0.612 0.610 0.619 0.703 0.399 0.580 0.534 0.672 0.419 0.503 0.431
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5.
Double Data Rate Synchronous DRAM (DDR-SDRAM) System Memory Design Guidelines
Introduction
The Intel 845MP/845MZ chipset Double Data Rate (DDR) SDRAM system memory interface consists of 120 CMOS signals. These CMOS signals have been divided into several signal groups: Data, Command, Control, Feedback, and Clock signals. Table 13 summarizes the different signal groupings. Refer to the Intel 845MP/845MZ Chipset Memory Controller Hub-Mobile (MCH-M) Datasheet for details on the signals listed.
5.1.
Table 13. Intel 845MP/845MZ DDR Signal Groups

Group Signal Name SDQ[63:0] Data SCB[7:0] SDQS[8:0] Data Bus Check Bits for ECC Function Data Strobes Description
SMA[12:0] SBS[1:0] Command SRAS# SCAS# SWE#
Memory Address Bus Bank Select Row Address Select Column Address Select Write Enable
Control
SCKE[3:0] SCS#[3:0]
Clock Enable - (One per Device Row) Chip Select - (One per Device Row)
Feedback
RCVENOUT# RCVENIN#
Output Feedback Signal Input Feedback Signal
Clocks
SCK[5:0] SCK#[5:0]
DDR-SDRAM Differential Clocks - (3 per SO-DIMM) DDR-SDRAM Inverted Differential Clocks - (3 per SO-DIMM)
Caution:
The Intel 845MP/845MZ chipset does not support data masking. The system memory DQM[7:0] pins on the DDR SO-DIMMs must be tied to ground.
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Design Guide
5.2.
DDR System Memory Topology and Layout Design Guidelines

The Intel 845MP/845MZ chipset Double Data Rate (DDR) SDRAM system memory interface implements the low swing, high-speed, terminated SSTL_2 topology. This section contains information and details on the DDR topologies, the DDR layout and routing guidelines, and the DDR power delivery requirements that will provide for a robust DDR solution on a Intel 845MP/845MZ based design. The MCH-M AGP ST[0] signal is sampled by the MCH-M on power-on to indicate at what system memory mode, DDR, the MCH-M should configure and operate. An internal MCH-M pull-up resistor on this signal sets the default system memory configuration to PC133 SDRAM. To enable the MCH-M to operate in DDR mode an external pull-down resistor to ground is required on ST[0]. The recommended pull-down resistor is 2 K. The DDR bus has been designed to route in two ground referenced internal layers. DDR System Memory Topologies for all signal groups have a relatively high via usage, please take this in consideration for the board layout as the vias and the anti-pad for the via could restrict power delivery to the SO-DIMMs.
5.2.1.
Data Signals SDQ[63:0], SDQS[8:0], SCB[7:0]

The MCH-M data signals are source synchronous signals that include the 64-bit wide data bus, 8 check bits for Error Checking and Correction (ECC), and 9 data strobe signals. There is an associated data strobe (DQS) for each data (DQ) and check bit (CB) group. This section summarizes the DQ/CB to DQS matching. The data signals include SDQ[63:0], SDQS[8:0], and SCB[7:0]. The data signals should transition from an external layer to an internal signal layer under the MCH-M. Keep to the same internal layer until transitioning back to an external layer at the series resistor. After the series resistor, the signal route should transition from the external layer to the same internal layer and route to SO-DIMM0. At SODIMM0 the signal should transition to an external layer and connect to the appropriate pad of the connector. At the SO-DIMM0 transition continue the signal route on the same internal layer to SODIMM1. Transition back out to an external layer and connect to the appropriate pad of SO-DIMM1 and the parallel termination resistor. Data Signals (SDQ[63:0],SDQS[8:0],SCB[7:0]) need to be routed on the same inner signal layer. In addition, match routing topology and via placement for all signals in a given byte lane including the associated strobe. External trace lengths should be minimized. To facilitate simpler routing, swapping of the byte lane and the associated strobe is allowed. Bit swapping within the byte lane is also allowed. Intel suggests that the parallel termination be placed on both sides of SO-DIMM1 to simplify routing and minimize trace lengths. All internal and external signals should be ground referenced to keep the path of the return current continuous. Resistor packs are acceptable for the series (Rs) and parallel (Rt) data and strobe termination resistors, but data and strobe signals can not be placed within the same R pack as the command and control signals. The table and diagrams below depict the recommended topology and layout routing guidelines for the DDR-SDRAM data signals.
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Figure 20. Data Signal Routing Topology
MCHPkg
MCH Pad
Rs L1
Rt L2 L3 L4
Vtt
SO-DIMM0 PAD
SO-DIMM1 PAD
Table 14. Data Signal Group Routing Guidelines

Parameter Signal Group Topology Routing Guidelines Data SDQ[63:0], SCB[7:0], SDQS[8:0] Daisy Chain Figure 20 Figure 23 Reference Plane Characteristic Trace Impedance (Zo) Trace Width Ground Referenced 55 15% Inner layer: 4 mils Outer layer: 5 mils Trace to space ratio Group Spacing Trace Length L1 MCH-M die pad to Series Termination Resistor Pad Trace Length L2 Series Termination Resistor Pad to First SO-DIMM Pad Trace Length L3 SO-DIMM Pad to SODIMM Pad Trace Length L4 Last SO-DIMM Pad to Parallel termination Resistor Pad Series Resistor (Rs) Termination Resistor (Rtt) Maximum Recommended motherboard via Count per signal Length Matching Requirements 1:2 (e.g. 4 mil trace 8 mil space) Isolation spacing from non-DDR related signals = 20 mils minimum Min = 2.0 Max = 3.5 Max = 0.75 Max = 1.25 Max = 0.8 22 5% (see note below) 56 5% (see note below) 5 vias SDQ[63:0], SCB[7:0] to SDQS[8:0] SDQS[8:0] to SCK/SCK#[5:0] See Section 5.2.1.1 for details See Section 5.2.1.2 for details NOTES: 1. Recommended resistor values may change in a later revision of the design guide. 2. The overall maximum and minimum lengths to the SO-DIMM must comply with clock length matching requirements. Figure 21, Figure 22 Figure 20 Figure 20 Figure 20 Figure 20 Figure 20 Figure 20 Figure
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Design Guide
5.2.1.1.
Data to Strobe Length Matching Requirements

The data signals SDQ[63:0] and the check bit signals [7:0] are grouped by byte lane and associated with a data strobe, SDQS[7:0]. The data signals and check bit signals must be length matched to their associated strobe within 25mils. For SO-DIMM0 this length matching includes the MCH-M package length and the motherboard trace length to the pads of the SO-DIMM0 connector (MCH-M package + L1 + L2). For SO-DIMM1 this length matching includes the MCH-M package length and the motherboard trace length to the pads of the SO-DIMM1 connector (MCH-M package + L1 + L2 + L3).
Associated SDQS Length = X SDQ/SCB Byte Group Length = Y, where ( X 25 mils ) Y ( X + 25 mils ) Length X and Y include the compensated MCH-M Package Length + the Motherboard Trace Length
No length matching is required from the second SO-DIMM to the parallel termination resistors. The table and diagram below depict the length matching requirements between the DQ, CB, and DQS signals.
Table 15. DQ/CB to DQS Length Mismatch Mapping
Signal SDQ[7:0] SDQ[15:8] SDQ[23:16] SDQ[31:24] SDQ[39:32] SDQ[47:40] SDQ[55:48] SDQ[63:56] SCB[7:0] Length Mismatch 25 mils 25 mils 25 mils 25 mils 25 mils 25 mils 25 mils 25 mils 25 mils Relative To SDQS0 SDQS1 SDQS2 SDQS3 SDQS4 SDQS5 SDQS6 SDQS7 SDQS8
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Figure 21. DQ/CB to DQS Trace Length Matching Requirements

SO-DIMM0
= MCH-M Package Lengths from die Pad to Ball = Motherboard Trace Lengths
MCH-M Package
MCH-M DIE
DQ/CB[0 ] DQ/CB[1 ] DQ/CB[2 ] DQ/CB[3 ] DQS DQ/CB[4 ] DQ/CB[5 ] DQ/CB[6 ] DQ/CB[7 ]
DQ/CB Length (Y) = (X 25 mils)
DQS Length = X
Note: Lengths are measured from MCH-M die pad to SODIMM0 connector
SO-DIMM0
= MCH-M Package Lengths from die Pad to Ball = Motherboard Trace Lengths
DQ/CB[0 ] DQ/CB[1 ] DQ/CB[2 ] DQ/CB[3 ] DQS DQ/CB[4 ] DQ/CB[5 ] DQ/CB[6 ] DQ/CB[7 ]
SO-DIMM1
MCH-M Package
MCH-M DIE
DQS Length = X
Note: Lengths are measured from MCH-M die pad to SODIMM1 connector
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Design Guide
5.2.1.2.
Strobe to Clock Length Matching Requirements

The data strobe signals must be 1.0 inch to 2.0 inches shorter than their associated differential clock pairs. Length matching equation for SO-DIMM0: X1=SCK/SCK#[2:0] Y1=SDQS[8:0] = MCH-M package + L1 + L2 of Figure 21 where, ( X1 2.0 ) Y1 ( X1 1.0 ) Length matching equation for SO-DIMM1: X2=SCK/SCK#[5:3] Y2= SDQS[8:0] = MCH-M Package + L1 + L2 + L3 of Figure 21 where, ( X2 2.0 ) Y2 ( X2 1.0 ) For example if the total clock length of SCK/SCK#[2:0](X1) is 3.5 inches then the length of all data strobe signal routing to SO-DIMM0 must be between 1.5 inches to 2.5 inches, if SCK/SCK#[5:3](X2) is 4.5 inches then the length of all control signal route to SO-DIMM1 must be between 2.5 inches to 3.5 inches.
The MCH-M package lengths for clocks and strobes must be taken into account for routing length matching. Refer to Section Table 23 or the Pentium 4 Processor-M in the 568 Pin Package and 845MP/845MZ Chipset Platform Trace Length Calculator for package trace length data.
Figure 22 depicts the length matching requirements between the data strobe signals and the clock signals.
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Figure 22. SDQS to SCK/SCK# Trace Length Matching Requirements

DIMM0 SO-DIMM0
= MCH-MPackageLengths from PadPad to Ball MCH Package Lengths from to Ball = Motherboard Trace Lengths
DQ/CB[0] DQ/CB[1] DQ/CB[2]
MCH-M DIE
MCH-M Package MCH Package
DQ/CB[3] DQS DQ/CB[4] DQ/CB[5] DQ/CB[6] DQ/CB[7] DQ/CB Length (Y) = (X 25 mils) DQS Length = X
MCH DIE
Note: Lengths are are measured from MCH pad SO-DIMM0connector Note: Lengths measured from MCH-M pad to to DIMM0 connector pins. pins.
SO-DIMM0 DIMM0
= MCH-M Package Lengths from PadPad to Ball MCH Package Lengths from to Ball = Motherboard Trace Lengths
SO-DIMM1 DIMM1
MCH-M Package MCH Package
DQ/CB[0] DQ/CB[1] DQ/CB[2] DQ/CB[3] DQ/CB Length (Y) = (X 25 mils)
MCH-M DIE
MCH DIE
DQS DQ/CB[4] DQ/CB[5] DQ/CB[6] DQ/CB[7]
DQS Length = X
Note: Lengths are measured from MCH-M pad pad to DIMM1connector Note: Lengths are measured from MCH to SO-DIMM0 connector pins.pins.
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Design Guide
5.2.1.3.
Data Routing Example

Figure 23 is an example of a board routing for the data signal group. Data routing is shown in red. The majority of the Data signal route is on an internal layer, both external layers can used for parallel termination R-pack placement.
Figure 23. Data Signal Group Routing Example
MCH
Data signals
5.2.2.
Control Signals SCKE[3:0], SCS#[3:0]

The MCH-M control signals, SCKE[3:0] and SCS#[3:0], are common clocked signals. They are clocked into the DDR SDRAMs using clock signals SCK/SCK#[5:0]. The MCH-M drives the control and clock signals together, with the clocks crossing in the valid control window. The MCH-M provides one chip select and one clock enable signal per SO-DIMM physical device row. Two chip-selects and two clock-enables will be routed to each SO-DIMM. Table 16 summarizes the control signal mapping.
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Table 16. Control Signal SO-DIMM Mapping

Signal SCS#[0] SCS#[1] SCS#[2] SCS#[3] SCKE[0] SCKE[1] SCKE[2] SCKE[3] Relative To SO-DIMM0 SO-DIMM0 SO-DIMM1 SO-DIMM1 SO-DIMM0 SO-DIMM0 SO-DIMM1 SO-DIMM1 SO-DIMM Pin 121 122 121 122 96 95 96 95
Refer to Figure 24 and Figure 27 for clarification of the description below. The control signal routing should transition from an external layer to an internal signal layer under the MCH-M. It should keep to the same internal layer until transitioning back out to an external layer(s) to connect to the appropriate pad of the SO-DIMM connector and the parallel termination resistor. If the layout requires return to the same internal layer and transition back out to an external layer immediately prior to parallel termination resistor. External trace lengths should be minimized. Intel suggests that the parallel termination be placed on both sides of the board to simplify routing and minimize trace lengths. All internal and external signals should be ground referenced to keep the path of the return current continuous. Intel suggests that control be routed on the same internal layer. Resistor packs are acceptable for the parallel (Rt) control termination resistors but control signals cant be placed within the same Rpacks as data, strobe or command signals. The diagrams and tables below depict the recommended topology and layout routing guidelines for the DDR-SDRAM control signals going to SO-DIMM0 or SO-DIMM1.
Figure 24. SO-DIMM0, 1 Control Signal Routing Topology
MCH-M Package Rt
MCH-M Pad
Vtt
L1
SO-DIMM0,1 PAD
L2
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Table 17. Control Signal Group Routing Guidelines1

Parameter Signal Group Topology Routing Guidelines Control SCS#[3:0], SCKE[3:0] Point to Point Parallel Termination Figure 24, Figure 27 Reference Plane Characteristic Trace Impedance (Zo) Trace Width Ground Referenced 55 15% Inner Layer= 4 mils Outer Layer= 5 mils Trace to space ratio Group Spacing Trace Length L1 MCH-M Control Signal Ball to SO-DIMM Pad Trace Length L2 SO-DIMM Pad to Rtt Pad Parallel Termination Resistor (Rtt) Maximum Recommended motherboard via Count per signal Length Matching Requirements 1:2 (e.g. 4mil trace 8mil space) Isolation spacing from non-DDR related signals = 20 mils Min = 0.5 Max= 5.0 Max = 2.0 56 +/- 5% (see note below) 3 vias3 SCS#/SCKE[3:0] to SCK/SCK#[5:0] See section 0 for details NOTES: 1. Recommendations may change in a later revision of the design guide based on a post silicon simulation analysis. 2. Where ever possible control signal should be routed on adjacent layers to the referenced plane. See Figure 25 below for example, the control signal routing should only route on Signal 1 and Signal 2 layer where Signal 1 may be external (microstrip) and Signal 2 may be internal (stripline) or where Signal 1 is internal (stripline) and Signal 2 is external (microstrip). 3. It is possible to route control using 2 vias if one via is shared that connect to SO-DIMM and parallel termination resistor. Figure 24 Figure 24 Figure 27 Figure 26 Figure 24
2
Figure
Note:
The overall maximum and minimum lengths to the SO-DIMM must comply with clock length matching requirements.
Figure 25. Referencing Plane Stack-up
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5.2.2.1.
Control Group Signal Length Matching Requirements

The control signals must be 1.0 inch to 3.0 inches shorter than their associated differential clocks pair. Note that these requirements may change in a later revision of the design guide based on a post silicon simulation analysis. Length matching equation for SO-DIMM0: X1=SCK/SCK#[2:0] Y1=SCS#[1:0] and SCKE[1:0] = L1 of Figure 26 where, ( X1 3.0 ) Y1 ( X1 1.0 ) Length matching equation for SO-DIMM1: X2=SCK/SCK#[5:3] Y2=SCS#[3:2] and SCKE[3:2] = L1 of Figure 26 where, ( X2 3.0 ) Y2 ( X2 1.0 ) For example if the clock length of SCK/SCK#[2:0](X1) is 3.5 inches then the length of all control signal routing to SO-DIMM0 must be between 0.5 inches to 2.5 inches, if SCK/SCK#[5:3](X2) is 4.5 inches then the length of all control signal route to SO-DIMM1 must be between 1.5 inches to 3.5 inches.
The MCH-M package lengths dont need to be taken into account for routing purpose.
Figure 26 depicts the length matching requirements between the control signals and the clock signals.
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Figure 26. Control Signal to SCK/SCK# Trace Length Matching Requirements
SO-DIMM0
= Motherboard Trace Lengths MCH-M
SCS#[1:0], SCKE[1:0]
(X - 3.0") < = (CNTRL Length) = < ( X - 1.0" )
SCK[2:0 ] SCK#[2:0]
SCK/SCK#[2:0] Length = X
Note: Lengths are measured from MCH-M pins to SO-DIMM0 connector pins.
SO-DIMM0
= Motherboard Trace Lengths MCH-M
SO-DIMM1
SCS#[3:2], SCKE[3:2]
(X - 3.0") < = (CNTRL Length) = < ( X - 1.0" )
SCK[5:3] SCK#[5:3] SCK/SCK#[5:3] Length = X
Note: Lengths are measured from MCH-M pins to SO-DIMM1 connector pins.
5.2.2.2.
Control Routing Example

Figure 27 is an example of a board routing for the control signal group.
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Figure 27. Control Routing Example FROM MCH-M
Control signals
Parallel Termination on Both Layers
Control routing is shown in red. The majority of the control signal route is on an internal layer, both external layers are used for parallel termination R-pack placement.
5.2.3.
Command Signals SMA[12:0], SBS[1:0], SRAS#, SCAS#, SWE#

There are two supported topologies for the command signal group. This section has been divided into two subsection; Topology 1 and Topology 2. Topology 2 is the topology that best allows for placement of the SO-DIMMs back to back in the butterfly configuration, thus minimizing the SO-DIMM footprint area. Mixing topology 1 and topology 2 is OK, as long as designer follows this documents guidelines. The MCH-M command signals; SMA[12:0], SBS[1:0], SRAS#, SCAS#, and SWE#; are common clocked signals. They are clocked into the DDR SDRAMs using the clock signals SCK/SCK#[5:0]. The MCH-M drives the command and clock signals together, with the clocks crossing in the valid command window.
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Design Guide
5.2.3.1.
5.2.3.1.1.
Command Topology 1 Solution

Routing description for Command Topology 1
Refer to Figure 28 and Figure 31 for clarification of the description below. The command signal routing should transition from an external layer to an internal signal layer under the MCH-M. Keep to the same internal layer until transitioning back to an external layer immediately prior to connecting the appropriate pad of the SO-DIMM0 connector. At the SO-DIMM0 layer transition continue the signal route on the same internal layer to the series resistor Rd2d, collocated to SO-DIMM1. At this resistor the signal should transition to an external layer immediately prior to the pad of Rd2d. After the series resistor, Rd2d, continue the signal route on the external layer landing on the appropriate connector pad of SODIMM1. After SO-DIMM1, transition to the same internal layer or stay on the external layer and route the signal to Rt. External trace lengths should be minimized. It is suggested that the parallel termination(Rt) be placed on both sides of the board to simplify routing and minimize trace lengths. All internal and external signals should be ground referenced to keep the path of the return current continuous. It is suggested that command be routed on same internal layer. Resistor packs are acceptable for the series (Rd2d) and parallel (Rt) command termination resistors but command signals cant be placed within the same Rpacks as data, strobe or control signals. The diagrams and tables below depict the recommended topology and layout routing guidelines for the DDR-SDRAM command signals routing to SO-DIMM0 and SO-DIMM1 for topology 1.Collocating the series resistor, Rd2d, and SO-DIMM1 allows for the elimination of one via from the signal route.
Figure 28. Command Signal Routing Topology 1
MCH-M Package
MCH-M
Rd2d L2
Vtt L3 L4
Pad
L1
SO-DIMM0 PAD
w
Rt
SO-DIMM1 PAD
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Table 18. Command Signal Group Routing Guidelines

Parameter Signal Group Topology Reference Plane Characteristic Trace Impedance (Zo) Trace Width
Routing Guidelines Command SMA[12:0], SBS[1:0], SRAS#, SCAS#, SWE# Daisy Chain Ground Referenced2 55 15% Inner layers= 4 mils Outer layer= 5 mils
Figure
Figure 28, Figure 31
Trace to space ratio Group Spacing Trace Length L1 MCH-M Command Signal ball to Rs Pad Trace Length L2 + L3 SO-DIMM0 Pad to Rd2d Pad; Rd2d Pad to SO-DIMM1 pad Trace Length L4 SO-DIMM1 Pad to Rt Pad Series Resistor (Rd2d) SO-DIMM0 to SODIMM1
1:2 (e.g. 4mil trace 8mil space) Isolation spacing from non-DDR related signals = 20 mils Min = 1.0 Max= 4.0 Max=1.3 Max =0.8 10 5% Figure 28 Figure 28 Figure 28 Figure 28
Parallel Termination Resistor (Rt) Maximum Recommended motherboard via Count per signal Length Matching Requirements
56 5% 5 vias3 CMD to SCK/SCK#[5:0] See 5.2.3.1.2 for details
Figure 28 Figure 31 Figure 30
NOTES: 1. Recommendation may change in a later revision of the design guide based on a post silicon simulation analysis. 2. Where ever possible command signals should be routed on adjacent layers to the referenced plane. See Figure 29 below for example, the command signal routing should only route on Signal 1 and Signal 2 layer where Signal 1 may be external (microstrip) and Signal 2 may be internal (stripline) or where Signal 1 is internal(stripline) and Signal 2 is external(microstrip). The ground plane is shared between Signal 1 and Signal2. 3. It is possible to route using 3 vias if one via is shared that connects to SO-DIMM1 and the parallel termination resistor.
Note:
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Design Guide
5.2.3.1.2.
Command Group Signal Length Matching Requirements

The command signals must be 1.0 inch to 3.0 inches shorter than their associated differential clock pairs SCK/SCK#[5:0]. Note that these requirements may change in a later revision of the design guide based on a post silicon simulation analysis. Length matching equation for SO-DIMM0: X1=SCK/SCK#[2:0] Y1=L1 of Figure 30 where, ( X1 3.0 ) Y1 ( X1 1.0 inch ) Length matching equation for SO-DIMM1: X2=SCK/SCK#[5:3] Y2=L1+L2+L3 of Figure 30where, ( X2 3.0 inches) Y2 ( X2 1.0 inch ). For example if the clock length of SCK/SCK#[2:0](X1) is 5.0 inches then the length of all command signal routing to SO-DIMM0 must be between 2.0 inches to 4.0 inches, if SCK/SCK#[5:3](X2) is 5.5 inches then the length of command signal routing to SO-DIMM1 must be between 2.5 inches to 4.5 inches.
Caution:
The MCH-M package lengths do not need to be taken into account for routing purposes. Figure 30 below depicts the length matching requirements between the command signals and the clock signals.
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Figure 30. Command Signal to SCK/SCK# Trace Length Matching Requirements
SO-DIMM0
= Motherboard
SMA[12:0], SBS[1:0], RAS#, CAS#, WE# (X - 3.0") < = (CMD Length) = < ( X - 1.0" )
MCH-M
SCK[2:0] SCK#[2:0]
Note: CMD Lengths are measured from MCH-M pins to SO-DIMM0 connector pins
SO-DIMM0
SO-DIMM1
= Motherboard
MCH-M
SCK[5:3] SCK#[5:3]
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Design Guide
Figure 31. Command Routing Example for Topology 1
From MCH-M
Serial Dampening Resistor Rd2d
Parallel Termination
NOTE: Red signals are command routing. The majority of the command signal route is on an internal layer.
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5.2.3.2.
5.2.3.2.1.
Command Topology 2 Solution

Routing Description for Command Topology 2
Refer to Figure 32 and Figure 33 for clarification of the description below. The command signal routing should transition from an external layer to an internal signal layer under the MCH-M. Keep to the same internal layer until transitioning back to an external layer at the series resistor Rd2d. At this point there is a T in the topology. One leg of the T will route through Rd2d and either transition back to the same internal layer or stay external and landing on the appropriate connector pad of SO-DIMM0. If it was necessary to return to the internal layer the signal should return to the external layer immediately prior to landing on the appropriate connector pad of SO-DIMM0. The other leg of the T will continue on the same internal layer and return to the external layer immediately prior to landing on the appropriate connector pad of SO-DIMM1. If possible stay on the external layer and connect to the parallel termination resistor or if the parallel termination resistor is on the opposite side of the board from the SO-DIMM1 connector then share the via and route to the parallel termination resistor. If sharing the via or using the opposite side of the board is not possible, continue on the same internal layer and route to the external layer immediately prior to the termination resistor. External trace lengths should be minimized. It is suggested that the parallel termination be placed on both sides of the board to simplify routing and minimize trace lengths. All internal and external signals should be ground referenced to keep the path of the return current continuous. It is recommended that command signal group be routed on same internal layer. Resistor packs are acceptable for the series (Rd2d) and parallel (Rt) command termination resistors but command signals cant be placed within the same Rpacks as data, strobe or control signals. The diagrams and tables below depict the recommended topology and layout routing guidelines for the DDR-SDRAM command signals going to SO-DIMM0 and SO-DIMM1.
Figure 32. Command Signal Routing Topology
MCH-M Package
MCH-M
Vtt
Pad
L1
Rd2d
L3
SO-DIMM1 PAD
L4
w
Rt
L2
SO-DIMM0 PAD
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Table 19. Command Signal Group Routing Guidelines

Parameter Signal Group Topology Reference Plane Characteristic Trace Impedance (Zo) Trace Width Routing Guidelines Command SMA[12:0], SBS[1:0], SRAS#, SCAS#, SWE# T Topology Ground Referenced2 55 15% Inner layers= 4 mils Outer layer= 5 mils Trace to space ratio Group Spacing Trace Length L1 MCH-M Command Signal ball to Rs Pad Trace Length L2 Rd2d Pad to SO-DIMM0 Pad Trace Length L3 Rd2d Pad to SO-DIMM1 1:2 (e.g. 4mil trace 8mil space) Isolation spacing from non-DDR related signals = 20 mils Min = 0.5 Max= 5.0 Max = 1.0 Min = 0.4 Max=1.75 Trace Length L4 SO-DIMM1 Pad to Rt Pad Series Dampening Resistor (Rd2d) Parallel Termination Resistor (Rt) Maximum Recommended motherboard via Count per signal Length Matching Requirements Max = 0.25 10 (see note below) 56 5% 6 vias3 CMD to SCK/SCK#[5:0] See 5.2.3.2.2 for details NOTES: 1. Recommendation may change in a later revision of the design guide based on a post silicon simulation analysis. 2. Wherever possible command signals should be routed on adjacent layers to the referenced plane. See Figure 33 for example. The command signal routing should only route on Signal 1 and Signal 2 layer where Signal 1 may be external (microstrip) and Signal 2 may be internal (stripline) or where Signal 1 is internal (stripline) and Signal 2 is external (microstrip). 3. It is possible to route using 3 vias if one via is shared that connect to SO-DIMM0 and Rd2d resistor.
1 1
Figure
Figure 32, Figure 35
Figure 32
Figure 32 Figure 32
Figure 32 Figure 32 Figure 32 Figure 35 Figure 34
Note:
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5.2.3.2.2.
Command Group Signal Length Matching Requirements

The command signals, must be 1.0 inch to 3.0 inches shorter than their associated differential clock pairs SCK/SCK#[5:0]. Note that these requirements may change in a later revision of the design guide based on a post silicon simulation analysis. Length matching equation for SO-DIMM0: X1=SCK/SCK#[2:0] Y1=L1 +L2 of Figure 34 where, ( X1 3.0 ) Y1 ( X1 1.0 inch ) Length matching equation for SO-DIMM1: X2=SCK/SCK#[5:3] Y2=L1+L3 of Figure 34 where, ( X2 3.0 ) Y2 ( X2 1.0 inch ) For example if the clock length of SCK/SCK#[2:0](X1) is 3.0 inches then the length of all command signal routing to SO-DIMM0 must be between 0.75 inches to 2.0 inches, if SCK/SCK#[5:3](X2) is 3.5 inches then the length of all command signal routing to SO-DIMM0 must be between 0.5 inches to 2.5 inches. The minimum length of 0.75 inches for command signal routing is the shortest possible length to SO-DIMM0.
Caution:
The MCH-M package lengths dont need to be taken into account for routing purposes. The diagram below depicts the length matching requirements between the command signals and the clock signals.
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Design Guide
Figure 34. Command Signal to SCK/SCK# Trace Length Matching Requirements
SO-DIMM0
= Motherboard
MCH-M Package
SCK[2:0] SCK#[2:0]
SO-DIMM0
SO-DIMM1
= Motherboard
MCH-M Package
SCK[5:3] SCK#[5:3]
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5.2.3.2.3.
Command Routing Example for Topology 2 Solution

Figure 35 is an example of a board routing for the command signal group.
Figure 35. Command Routing Example for Topology 2 From MCH-M
Series Dampening Resistor Rd2d
Parallel Termination on Both layers
NOTE:
Red signals are command routing. The majority of the command signal route is on an internal layer; both external layers are used for parallel termination R-pack placement. Note that the series dampening R-packs are rotated to allow for improved power distribution.
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Design Guide
5.2.4.
Clock Signals SCK[5:0], SCK#[5:0]

The clock signal group includes the differential clock pairs SCK[5:0] and SCK#[5:0]. The MCH-M generates and drives these differential clock signals required by the DDR interface; therefore, no external clock driver is required for the DDR interface. The MCH-M only supports unbuffered DDR SODIMMs, three differential clock pairs are routed to each SO-DIMM connector. Table 20 summarizes the clock signal mapping.
Table 20. Clock Signal Mapping

Signal SCK[2:0], SCK#[2:0] SCK[5:3], SCK#[5:3] Relative To SO-DIMM0 SO-DIMM1
Note:
One to one mapping of the clocks from the MCH-M to the SO-DIMM is not required. For example, it is not necessary that SCK0 from the MCH-M routes to the same number clock on the SO-DIMM0 connector, which is CK0 in the PC2100 and PC1600 DDR SDRAM Unbuffered SO-DIMM Reference Design Specification. However CKn and CKn# may not be swapped from the MCH-M to the SODIMMs. The changing of clock numbering from MCH-M to SO-DIMMs may require a BIOS change. The clock signal routing should transition from an external layer to an internal signal layer under the MCH-M and route as a differential pair referenced to ground for the entire length to their associated SODIMM connector pads. Immediately prior to the SO-DIMM connector the signals should transition to an external layer to connect the appropriate pad of the connector. External trace lengths should be minimized. All internal and external signal routing should be ground referenced to keep the path of the return current continuous. The diagrams and table below depict the recommended topology and layout routing guidelines for the DDR-SDRAM differential clocks.
Figure 36. DDR Clock Routing Topology (SCK/SCK#[2:0])
MCH-M Package
MCH-M Pad
L1
SO-DIMM0,1 PAD
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Table 21. Clock Signal Group Routing Guidelines

Parameter Signal Group Topology Reference Plane Characteristic Trace Impedance (Zo) Trace Width
Routing Guidelines Clock SCK[5:0], SCK#[5:0] Differential Pair Point to Point Ground Referenced
2
Figure
Figure 35
Single Ended =55 15% Inner layers= 4 mils Outer layer= 5 mils
Differential Trace Spacing
Inner layers= 4 mils Outer layer= 5 mils
Group Spacing
Isolation spacing from another DDR signal group = 20 mils Isolation spacing from non-DDR related signals = 20 mils
Serpentine Spacing Trace Length L1 MCH-M Signal ball to Associated SO-DIMM0 Connector Pad Maximum Recommended motherboard via Count per signal Length Matching Requirements
12 mils minimum Min = 1.5 Max= 8.0 2 vias SCK / SCK# The three SO-DIMM0 Clock pairs are equal in length plus tolerance, and the three SO-DIMM1 Clock pairs are equal in length plus tolerance. See Section 5.2.4.1 for details Figure 38, Figure 39 Figure 35
Clock pair to pair tolerance SCK to SCK# tolerance
25 mils 10 mils
NOTES: 1. Recommendation may change in a later revision of the design guide based on a post silicon simulation analysis. 2. Wherever possible the clock signals should be routed on adjacent layers to the referenced ground plane. See Figure 37 for example. The clock signal routing should only route on Signal 1 and Signal 2 layer where Signal 1 may be external (microstrip) and Signal 2 may be internal (stripline) or where Signal 1 is internal (stripline) and Signal 2 is external (microstrip).
Figure 37. Ground Referencing Plane Stack-up
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Design Guide
5.2.4.1.
Clock Group Signal Length Matching Requirements

The MCH-M provides three differential clock pair signals for each SO-DIMM. A differential clock pair is made up of a SCK signal and its complement signal SCK#. The differential pairs for one SODIMM are: SCK[0] / SCK#[0] SCK[1] / SCK#[1] SCK[2] / SCK#[2] The differential pairs for the second SO-DIMM are: SCK[3] / SCK#[3] SCK[4] / SCK#[4] SCK[5] / SCK#[5] The SCK and SCK# lengths must include both the MCH-M Package Length plus the Motherboard Trace Length. Clock length matching is required between clock pairs to their specified SO-DIMM connector. The differential clock pairs must be matched to 25 mils including MCH-M package lengths. Each SCK to SCK# pair must be matched to 10 mils including MCH-M package lengths. Please note that the differential clocks must be 1.0 inch to 2.0 inches longer than the data and data strobe signals, and 1.0 inch to 3.0 inches longer then the control and command signals. For information covering the data and data strobe to clock length matching requirements reference 5.2.1.1, for information covering the control signal to clock length matching requirements reference 5.2.2.1, and for information covering the command signal to clock length matching requirements reference Section 5.2.3.1.2 and 5.2.3.2.2-update link. The diagrams below depict the clock length matching requirements. Refer to the Pentium 4 Processor-M in the 568 Pin Package and Intel 845MP/845MZ Chipset Platform Trace Length Calculator for package trace length data.
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Figure 38. SCK to SCK# Trace Length Matching Requirements
SO-DIMM0
= MCH Package Lengths from Die Pad to Ball = Motherboard Trace Lengths
MCH-M Package
SCK0 SCK#0 SCK1 SCK#1 SCK0 Length = X SCK#0 Length = X SCK1 Length = X SCK#1 Length = X SCK2 Length = X SCK#2 Length = X
MCH-M DIE
SCK2 SCK#2
Note: Lengths are measured from MCH-M pad to SO-DIMM0 connector pins.
= MCH Package Lengths from Die Pad to Ball = Motherboard Trace Lengths
SCK3 SCK3# SCK4 SCK4#
SO-DIMM0
SO-DIMM1
MCH-M Package
MCH-M DIE
SCK5 SCK#5
SCK3 Length = Y SCK#3 Length = Y SCK4 Length = Y SCK#4 Length = Y SCK5 Length = Y SCK#5 Length = Y
Note: Lengths are measured from MCH-M Die Pad to SO-DIMM1 connector pins.
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Design Guide
Figure 39. Clock Pair Trace Length Matching Requirements
SO-DIMM0
= MCH Package Lengths from Pad to Ball = Motherboard Trace Lengths
SCK/SCK#[0]
MCH-M Package
SCK/SCK#[1]
SCK/SCK#[0] Length = X SCK/SCK#[1] Length = X SCK/SCK#[2] Length = X
MCH-M DIE
SCK/SCK#[2]
Note: Lengths are measured from MCH-M pad to SO-DIMM0 connector pins
SO-DIMM0
= MCH-M Package Lengths from Pad to Ball = Motherboard Trace Lengths
SO-DIMM1
MCH-M Package
SCK/SCK#[3]
SCK/SCK#[4]
SCK/SCK#[3] Length = Y SCK/SCK#[4] Length = Y SCK/SCK#[5] Length = Y
MCH-M DIE
SCK/SCK#[5]
Note: Lengths are measured from MCH-M pad to SO-DIMM1 connector pins
5.2.5.
Feedback - RCVENOUT#, RCVENIN#

The MCH-M provides a feedback signal called receive enable (RCVEN#), which is used to gate the strobe inputs for read data. There are two pins on the MCH-M to facilitate the use of RCVEN#. The RCVENOUT# pin is an output of the MCH-M and the RCVENIN# pin is an input to the MCH-M. RCVENOUT# must connect to RCVENIN#. The RCVEN# signal must be routed on the same layer as the system memory clocks. It should transition from the top signal layer to an inner signal layer under the MCH-M, routed referenced to ground for the entire length, and then transition from the inner signal layer back to the top signal layer under the MCHM.
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External trace lengths should be minimized. All internal and external signals should be ground referenced to keep the path of the return current continuous. The diagrams and table below depicts the recommended topology and layout routing guidelines for the DDR-SDRAM feedback signal.
Figure 40. DDR Feedback (RCVEN#) Routing Topology
MCH-M
RCVENOUT# Ball
MCH-M
RCVENIN# Ball
A B
A
Internal Layer
Table 22. DDR Feedback Signal Routing Guidelines

Parameter Signal Group Topology Reference Plane Characteristic Trace Impedance (Zo) Trace Width Routing Guidelines Feedback RCVENOUT# and RCVENIN# Point to Point Ground Referenced 55 15% Inner layers= 4 mils Outer layers= 5mils Group Spacing Isolation spacing from another DDR signal group = 10 mils Isolation spacing from non-DDR related signals = 10 mils Trace Length A MCH-M Signal Ball to MCH-M Signal Via Total Length A + B MCH-M RCVENOUT# Signal Ball to MCH-M RCVENIN# Signal Ball Maximum via Count per signal Length Matching Requirements Max = 40 mils Must equal 1000 mils 10 mils Figure 40 Figure 40 Figure
2 None
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Design Guide
Table 23. MCH-M DDR Signal Package Lengths

DDR Data Signals Data Signal MCH-M Ball Package Length (inches) 0.716 0.699 0.874 0.754 0.532 0.666 0.592 0.892 0.797 0.833 0.812 0.753 0.886 0.867 0.773 0.645 0.722 0.602 0.699 0.566 0.785 0.781 0.64 0.711 0.627 0.555 0.587 0.522 0.615 0.487 0.579 0.521 0.432 Data Signal MCH-M Ball Package Length (inches) 0.639 0.552 0.588 0.626 0.533 0.605 0.587 0.522 0.523 0.715 0.706 0.643 0.7 0.664 0.76 0.922 0.64 0.846 0.81 0.67 0.859 0.811 0.723 0.814 0.949 0.893 0.865 0.689 0.57 0.526 0.623 0.533 0.621
SDQ0 SDQ1 SDQ2 SDQ3 SDQ4 SDQ5 SDQ6 SDQ7 SDQ8 SDQ9 SDQ10 SDQ11 SDQ12 SDQ13 SDQ14 SDQ15 SDQ16 SDQ17 SDQ18 SDQ19 SDQ20 SDQ21 SDQ22 SDQ23 SDQ24 SDQ25 SDQ26 SDQ27 SDQ28 SDQ29 SDQ30 SDQ31 SDQ32
G28 F27 C28 E28 H25 G27 F25 B28 E27 C27 B25 C25 B27 D27 D26 E25 D24 E23 C22 E21 C24 B23 D22 B21 C21 D20 C19 D18 C20 E19 C18 E17 E13
SDQ36 SDQ37 SDQ38 SDQ39 SDQ40 SDQ41 SDQ42 SDQ43 SDQ44 SDQ45 SDQ46 SDQ47 SDQ48 SDQ49 SDQ50 SDQ51 SDQ52 SDQ53 SDQ54 SDQ55 SDQ56 SDQ57 SDQ58 SDQ59 SDQ60 SDQ61 SDQ62 SDQ63 SCB0 SCB1 SCB2 SCB3 SCB4
B13 C13 C11 D10 E10 C9 D8 E8 E11 B9 B7 C7 C6 D6 D4 B3 E6 B5 C4 E5 C3 D3 F4 F3 B2 C2 E2 G5 C16 D16 B15 C14 B17
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DDR Data Signals Data Signal MCH-M Ball Package Length (inches) 0.543 0.596 0.59 Data Signal MCH-M Ball Package Length (inches) 0.583 0.54 0.503
SDQ33 SDQ34 SDQ35
C12 B11 C10 DDR Data Strobe Signals
SCB5 SCB6 SCB7
C17 C15 D14 DDR Clock Signals
Data Signal
MCH-M Ball
Package Length (inches) 0.651 0.775 0.738 0.636 0.493 0.596 0.776 0.821 0.52
Data Signal
MCH-M Ball
Package Length (inches) 0.453 0.432 0.454 0.587 0.551 0.543 0.371 0.349 0.610 0.548 0.589 0.693
SDQS0 SDQS1 SDQS2 SDQS3 SDQS4 SDQS5 SDQS6 SDQS7 SDQS8
F26 C26 C23 B19 D12 C8 C5 E3 E15
SCK0 SCK#0 SCK1 SCK#1 SCK2 SCK#2 SCK3 SCK#3 SCK4 SCK#4 SCK5 SCK#5
E14 F15 J24 G25 G6 G7 G15 G14 E24 G24 H5 F5
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6.
AGP Port Design Guidelines

For detailed AGP interface functionality (e.g., protocols, rules, signaling mechanisms), refer to the latest AGP Interface Specification, Revision 2.0, which can be obtained from http://www.agpforum.org. This design guide (Intel 845MP/845MZ Chipset Platform Design Guide) focuses only on specific Intel 845MP/845MZ chipset platform recommendations.
6.1.
AGP Interface
The AGP Interface Specification Revision 2.0 enhances the functionality of the original AGP Interface Specification (revision 1.0) by allowing 4X data transfers (4 data samples per clock) and 1.5-volt operation. In addition to these major enhancements, additional performance enhancement and clarifications, such as fast write capability, are included in Revision 2.0 of the AGP Interface Specification. The 4X operation of the AGP interface provides for quad-sampling of the AGP AD (Address/Data) and SBA (Side-band Addressing) buses. That is, the data is sampled four times during each 66-MHz AGP clock. This means that each data cycle is of a 15 ns (66-MHz clock) or 3.75 ns. It is important to realize that 3.75 ns is the data cycle time; not the clock cycle time. During 2X operation, the data is sampled twice during a 66-MHz clock cycle, therefore, the data cycle time is 7.5 ns. In order to allow for these high-speed data transfers, the 2X mode of AGP operation uses source synchronous data strobing. During 4X operation, the AGP interface uses differential source synchronous strobing. With data cycle times as small as 3.75 ns, and setup/hold times of 1 ns, propagation delay mismatch is critical. In addition to reducing propagation delay mismatch, it is important to minimize noise. Noise on the data lines will cause the settling time to be large. If the mismatch between a data line and the associated strobe is too great, or there is noise on the interface, incorrect data will be sampled. The low-voltage operation on AGP (1.5 V) requires even more noise immunity. For example, during 1.5V operation, Vilmax is 570 mV. Without proper isolation, crosstalk could create signal integrity issues. A single AGP connector is supported by the Intel 845MP/845MZ chipset MCH-M AGP interface. LOCK# and SERR#/PERR# are not supported. The AGP buffers operate in only one mode. 1.5-V drive, not 3.3-V safe. This mode is compliant with the AGP 2.0 spec. The Intel 845MP/845MZ chipset can make use of a 1.5V only AGP connector. AGP 4X, 2X and 1X must operate at 1.5 V. The AGP interface supports up to 4X AGP signaling. AGP semantic cycles to DRAM are not snooped on the host bus. The Intel 845MP/845MZ chipset MCH-M supports PIPE# or SBA[7:0] AGP address mechanisms, but not both simultaneously. Either the PIPE# or the SBA[7:0] mechanism must be selected during system initialization The AGP interface is clocked from the 66-MHz clock (pin 3V66). The AGP interface is synchronous to the host and system memory interfaces with a clock ratio of 1:2 (66 MHz: 133 MHz) and to the hub interface with a clock ratio of 1:1 (66 MHz : 66 MHz).
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6.2.
AGP 2.0
The AGP Interface Specification, rev. 2.0, enhances the functionality of the original AGP Interface Specification (rev. 1.0) by allowing 4X data transfers (i.e., 4 data samples per clock) and 1.5-volt operation. The 4X operation of the AGP interface provides for "quad-pumping" of the AGP AD (address/data) and SBA (side-band addressing) buses. That is, data is sampled four times during each 66MHz AGP clock. This means that each data cycle is of a 15-ns (66-MHz) clock or 3.75 ns. It is important to realize that 3.75 ns is the data cycle time, not the clock cycle time. During 2X operation, data is sampled twice during a 66-MHz clock cycle; therefore, the data cycle time is 7.5 ns. In order to allow for these high-speed data transfers, the 2X mode of AGP operation uses source-synchronous data strobing. During 4X operation, the AGP interface uses differential source-synchronous strobing. With data cycle times as small as 3.75 ns and setup/hold times of 1 ns, propagation delay mismatch is critical. In addition to reducing propagation delay mismatch, it is important to minimize noise. Noise on the data lines will cause the settling time to be long. If the mismatch between a data line and the associated strobe is too great or if there is noise on the interface, incorrect data will be sampled. The lowvoltage operation on AGP (1.5 V) requires even more noise immunity.
6.2.1.
AGP Interface Signal Groups

The signals on the AGP interface are broken into three groups: 1X timing domain signals, 2X/4X timing domain signals, and miscellaneous signals. Each group has different routing requirements. In addition, within the 2X/4X timing domain signals, there are three sets of signals. All signals in the 2X/4X timing domain must meet minimum and maximum trace length requirements as well as trace width and spacing requirements. The signal groups are documented in the following table.
Table 24. AGP 2.0 Signal Groups

1x Timing Domain AGPCLK PIPE# RBF# WBF# ST[2:0] G_FRAME# G_IRDY# G_TRDY# G_STOP# G_DEVSEL# G_REQ# G_GNT# G_PAR 2x/4x Timing Domain SET #1 G_AD[15:0] G_CBE[1:0]# AD_STB0 AD_STB0# SET #2 G_AD[31:16] G_CBE[3:2]# AD_STB1 AD_STB1# SET #3 SBA[7:0] SB_STB SB_STB# Miscellaneous Signals USB+ USBOVRCNT# PME# TYPDET# PERR# SERR# INTA# INTB#
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These signals are used in 4X AGP mode ONLY.

Table 25. AGP 2.0 Data/Strobe Associations
Data AD[15:0] and C/BE[1:0]# AD[31:16] and C/BE[3:2]# SBA[7:0] Associated Strobe in 1X Strobes are not used in 1X mode. All data is sampled on rising clock edges. Strobes are not used in 1X mode. All data is sampled on rising clock edges. Strobes are not used in 1X mode. All data is sampled on rising clock edges. Associated Strobe in 2X AD_STB0 AD_STB1 SB_STB Associated Strobes in 4X AD_STB0, AD_STB0# AD_STB1, AD_STB1# SB_STB, SB_STB#
Throughout this section, the term data refers to AD[31:0], C/BE[3:0]#, and SBA[7:0]. The term strobe refers to AD_STB[1:0], AD_STB#[1:0], SB_STB, and SB_STB#. When the term data is used, it refers to one of the three sets of data signals, as in Table 24. When the term strobe is used, it refers to one of the strobes as it relates to the data in its associated group. The routing guidelines for each group of signals (1X timing domain signals, 2X/4X timing domain signals, and miscellaneous signals) will be addressed separately.
6.3.
6.3.1.
6.3.1.1.
AGP Routing Guidelines

1X Timing Domain Routing Guidelines
Trace Length Requirements for the AGP 1X
This section contains information on the 1X Timing Domain Routing Guidelines. The AGP 1X timing domain signals (refer to Table 24) has a maximum trace length of 9.5 inches. The target impedance is 55 ohm, with plus and minus fifteen percent tolerance. This maximum applies to ALL of the signals listed as 1X timing domain signals in Table 25. In addition to this maximum trace length requirement (refer to Table 27 and Table 28) these signals must meet the trace spacing and trace length mismatch requirements in Sections 6.3.1.2 and 6.3.1.3.
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Table 26. Layout Routing Guidelines for AGP 1X Signals

1X signals CLK_AGP_SLT AGP_PIPE# AGP_RBF# AGP_WBF# AGP_ST[2:0] AGP_FRAME# AGP_IRDY# AGP_TRDY# AGP_STOP# AGP_DEVSEL# AGP_REQ# AGP_GNT# AGP_PAR Max. length (inches) 10 10 10 10 10 10 10 10 10 10 10 10 10 Width (mils) 4 4 4 4 4 4 4 4 4 4 4 4 4 Space (mils) 4 4 4 4 4 4 4 4 4 4 4 4 4
6.3.1.2.
Trace Spacing Requirements

AGP 1X timing domain signals (refer to Table 27) can be routed with 4-mil minimum trace separation.
6.3.1.3.
Trace Length Mismatch

There are no trace length mismatch requirements for 1X timing domain signals. These signals must meet minimum and maximum trace length requirements.
6.3.2.
6.3.2.1.
2X/4X Timing Domain Routing Guidelines

Trace Length Requirements for AGP 2X/4X
These trace length guidelines apply to ALL of the signals listed as 2X/4X timing domain signals in Table 25. In addition to these maximum trace length requirements, these signals must meet the trace spacing and trace length mismatch requirements in Sections 6.3.2.2 and 6.3.2.3. The maximum line length and mismatch requirements are dependent on the routing rules used on the motherboard. These routing rules were created to give design freedom by making tradeoffs between signal coupling (trace spacing) and line lengths. These routing rules are divided by trace spacing. In 1:2 spacing, the distance between the traces is two times the width of traces. Simulations in mobile environment support this rule.
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Figure 41. AGP Layout Guidelines

(Line:Space) Always 1:2 Strobe to Strobe# Routing Always 1:3 Strobe to Data Routing
MCH-M
1:3 routing 6.0 max length +/-0.1 mismatch
AGP Controller
If the AGP interface is less than 6.0 inches, a 1:2 trace spacing is required for 2X/4X lines. These 2X/4X signals must be matched their associated strobe within 0.1 inches. This is for designs that require less than 6 inches between the graphics device and the MCH-M. Reduce line length mismatch to ensure added margin. In order to reduce trace to trace coupling (cross talk), separate the traces as much as possible.
6.3.2.2.
Trace Spacing Requirements

AGP 2X/4X timing domain signals (refer to Table 25) must be routed as documented in Table 28. They should be routed using 4-mil traces. Additionally, the signals can be routed with 5-mil spacing when breaking out of the MCH-M. The routing must widen to the requirement in Table 28 within 0.3 inches of the MCH-M package. Since the strobe signals (AD_STB0, AD_STB0#, AD_STB1, AD_STB1#, SB_STB, and SB_STB#) act as clocks on the source synchronous AGP interface, special care should be taken when routing these signals. Because each strobe pair is truly a differential pair, the pair should be routed together (e.g. AD_STB0 and AD_STB0# should be routed next to each other). The two strobes in a strobe pair should be routed on 4-mil traces with 8 mils of space (1:2) between them. This pair should be separated from the rest of the AGP signals (and all other signals) by at least 15 mils (1:3). The strobe pair must be length matched to less than 0.1 inches (that is, a strobe and its compliment must be the same length within 0.1 inches).
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Table 27. Layout Routing Guidelines for AGP 2X/4X Signals

Signal 2X/4X Timing Domain Set#1 2X/4X Timing Domain Set#2 2X/4X Timing Domain Set#3 Maximum Length (inch) 6 Trace Space (mils) (4 mil traces) 8 Length Mismatch (inch) 0.1 Relative To AGP_ADSTB0 and AGP_ADSTB0# AGP_ADSTB1 and AGP_ADSTB1# AGP_SBSTB and AGP_SBSTB # Notes AGP_ADSTB0, AGP_ADSTB0# must be the same length (10 mils) AGP_ADSTB1, AGP_ADSTB1# must be the same length 10 mils) AGP_SBSTB, AGP_SBSTB# must be the same length (10 mils)
0.1
0.1
6.3.2.3.
Trace Length Mismatch Requirements

The length-matching requirement depends on the maximum AGP trace length. If there are no AGP 2X/4X traces longer than 6.0 inches, then signals must be matched within 0.1 inches.
Table 28. AGP 2.0 Data Lengths Relative to Strobe Length

Max Trace Length < 6 in Trace Spacing 1:2 Strobe Length X Minimum Trace Length X 0.1 in Maximum Trace Length X + 0.1 in
The trace length minimum and maximum (relative to strobe length) should be applied to each set of 2X/4X timing domain signals independently. That is, if AD_STB0 and ADSTB0# are 5 inches, then AD[15:0] and C/BE[1:0] must be between 4.9 inches and 5.1 inches. However AD_STB1 and ADSTB1# can be 3.5 inches (and therefore AD[31:16] and C/BE#[3:2] must be between 3.4 inches and 3.6 inches). In addition, all 2X/4X timing domain signals must meet the maximum trace length requirements. All signals should be routed as striplines (inner layers). All signals in a signal group should be routed on the same layer. Routing studies have shown that these guidelines can be met. The trace length and trace spacing requirements must not be violated by any signal. Trace length mismatch for all signals within a signal group should be as close to 0 inches as possible to provide optimal timing margin. Table 29 shows AGP 2.0 routing summary.
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Table 29. AGP 2.0 Routing Guideline Summary

Signal 1X Timing Domain 2X/4X Timing Domain Set#1 2X/4X Timing Domain Set#2 2X/4X Timing Domain Set#3 Miscellaneous Maximum Length 10 in 6 in Trace Spacing (4 mil traces) 4 mils 8 mils Length Mismatch No Requirement 0.1 in Relative To N/A AD_STB0 and AD_STB0# AD_STB1 and AD_STB1# SB_STB and SB_STB# N/A Notes None AD_STB0, AD_STB0# must be the same length AD_STB1, AD_STB1# must be the same length SB_STB, SB_STB# must be the same length PCI_PME#, AGP_PERR#, AGP_SERR#
6 in
8 mils
0.1 in
6 in
8 mils
0.1 in
10 in
8 mils
No Requirement
NOTE:
Each strobe pair must be separated from other signals by at least 15 mils.
6.3.3.
AGP Clock Skew

The maximum total AGP clock skew, between the Intel 845MP/845MZ and the graphics component, is 1 ns for all data transfer modes. This 1 ns includes skew and jitter, which originates on the motherboard, add-in module (if used), and clock synthesizer. Clock skew must be evaluated not only at a single threshold voltage, but also at all points on the clock edge that falls in the switching range. The 1-ns skew budget is divided such that the motherboard is allotted 0.9 ns of clock skew (the motherboard designer shall determine how the 0.9 ns is allocated between the board and the synthesizer).
6.3.4.
AGP Signal Noise Decoupling Guidelines

The following routing guidelines are recommended for the optimal system design. The main focus of these guidelines is to minimize signal integrity problems on the AGP interface of the Intel 845MP/845MZ chipset (MCH-M). The following guidelines are not intended to replace thorough system validation on Intel 845MP/845MZ chipset-based products.
A minimum of six 0.01-F capacitors are required and must be as close as possible to the MCH-M. These should be placed within 70 mils of the outer row of balls on the MCH-M for VDDQ decoupling. The closer the placement, the better the performance. The designer should evenly distribute placement of decoupling capacitors in the AGP interface signal field. Intel recommends that the designer use a low-ESL ceramic capacitor, such as with a 0603 body-type X7R dielectric. In order to add the decoupling capacitors within 70 mils of the MCH-M and/or close to the vias, the trace spacing may be reduced as the traces go around each capacitor. The narrowing of space between traces should be minimal and for as short a distance as possible (1-inch max.). In addition to the minimum decoupling capacitors, the designer should place bypass capacitors at vias that transition the AGP signal from one reference signal plane to another. On a typical four
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layer PCB design, the signals transition from one side of the board to the other. One extra 0.01-F capacitor is required per 10 vias. The capacitor should be placed as close as possible to the center of the via field.
6.3.5.
AGP Routing Ground Reference

Intel strongly recommends that at least the following critical signals be referenced to ground from the MCH-M to an AGP connector controller ), using a minimum number of vias on each net: AD_STB0, AD_STB0#, AD_STB1, AD_STB1#, SB_STB, SB_STB#, G_TRDY#, G_IRDY#, G_GNT#, and ST[2:0]. In addition to the minimum signal set listed previously, Intel strongly recommends that half of all AGP signals be referenced to ground, depending on the board layout. In an ideal design, the complete AGP interface signal field would be referenced to ground. This recommendation is not specific to any particular PCB stack-up, but should be applied to all Intel 845MP/845MZ chipset designs.
6.3.6.
Pull-ups
AGP control signals require pull-up resistors to VDDQ on the motherboard to ensure they contain stable values when no agent is actively driving the bus. Intel 845MP/845MZ MCH-M has integrated the following pull-up resistors, however, the following signals may still require pull-up resistors: 1X Timing Domain Signals: FRAME# TRDY# IRDY# DEVSEL# STOP# SERR# PERR# RBF# PIPE# REQ# WBF# GNT# ST[2:0] PAR
It is critical that these signals be pulled up to 1.5 V.
The trace stub to the pull-up resistor on 1X timing domain signals should be kept at less than 0.5 inches, to avoid signal reflections from the stub.
The strobe signals require pull-ups/pull-downs on the motherboard to ensure that they contain stable values when no agent is driving the bus.
INTA# and INTB# should be pulled to 3.3 V, not VDDQ. The 2X/4X Timing Domain Signals are:
AD_STB[1:0] SB_STB
(pull up to 1.5 V) (pull up to1.5 V)
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AD_STB[1:0]# SB_STB#
(pull down to ground) (pull down to ground)
The trace stub to the pull-up/pull-down resistor on 2X/4X timing domain signals should be kept to less than 0.1 inch, to avoid signal reflections from the stub. The pull-up/pull-down resistor value requirements are shown in Table 30.
Table 30. AGP 2.0 Pull-up Resistor Values
Rmin 4 K Rmax 16 K
The recommended AGP pull-up/pull-down resistor value is 8.2 K. The MCH-M ST[0] signal needs a site for an external pull-down resistor to ground.
6.3.7.
AGP VDDQ and Vref

AGP specifies two separate power planes: VCC and VDDQ. VCC is the core power for the graphics controller. AGP specifies VCC voltage plane as ALWAYS 3.3 V. VDDQ is the interface voltage. The external graphics controller may ONLY power the MCH-M AGP I/O buffers with the 1.5-V VDDQ power pins. In AGP 1.0 implementations, VDDQ was also 3.3 V. For the designer developing an AGP 1.0 motherboard, there is no distinction between VCC and VDDQ as both are tied to the 3.3-V power plane on the motherboard. AGP 2.0 requires that these power planes are separate. In conjunction with the 4X data rate, the AGP 2.0 Interface Specification provides for low-voltage (1.5 V) operation. The VCC and VDDQ power supplies are such that the VDDQ voltage level is never more than 0.5 V above the VCC voltage level.
6.3.8.
6.3.8.1.
Vref Generation for AGP 2.0(2X & 4X)

3.3-V AGP Interface (AGP 2x)
The 3.3-V AGP interfaces will use only one Vref. That is, only one resistor divider on the AGP controller that will divide VDDQ down to Vref for MCH-M and AGP controller. For Intel 845MP/845MZ platforms, only 1.5-V interface will be supported.
6.3.8.2.
1.5-V AGP interface (AGP 2x & 4x)

In order to account for potential differences between VDDQ and GND at the MCH-M and graphics controller, both devices use source generated Vref. That is, the Vref signal is generated at the graphics controller and sent to the MCH-M, and another Vref is generated at the MCH-M and sent to the graphics controller. Both the graphics controller and the MCH-M are required to generate Vref. The voltage divider networks consist of AC and DC elements.
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The Vref divider network should be placed as close to the AGP interface as is practical to get the benefit of the common mode power supply effects. However, the trace spacing around the Vref signals must be a minimum of 25 mils to reduce crosstalk and maintain signal integrity. All resistors used in above reference generation schemes should have 1% tolerance.
6.3.9.
Compensation
The MCH-M AGP interface supports resistive buffer compensation (RCOMP). For Printed Circuit Boards with Characteristics impedance of 55 , tie the AGP_RCOMP pin to a 36.5 , 1% pull-down resistor (to ground) via a 10-mil wide, very short (0.5 inches) trace.
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7.
7.1.
MCH-M PLL Requirements

MCH-M PLL Power Delivery
VCCA1 and VSSA1, and VCCA0 and VSSA0 are power sources required by the MCH-Ms PLL clock generators.
Figure 42. Intel 845MP/845MZ PLL0 Filter

V_1P5_CORE VCCA0 (ball T13) L C PLL VSSA0 (ball U13) MCH MCH-M
Length A
Table 31. PLL0 Filter Routing Guidelines

Parameter Trace Width Trace Spacing Trace Length A Capacitor C Inductor L 5 mils 10 mils 1.5 33 F 4.7 H Routing Guidelines
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Figure 43. Intel 845MP/845MZ PLL1 Filter

V_1P5_CORE VCCA1 (ball T17) L C PLL VSSA1 (ball U17) MCH
Length A
Table 32. PLL1 Routing Guidelines

Parameter Trace Width Trace Spacing Trace Length A Capacitor C Inductor L 5 mils 10 mils 1.5 33 F 4.7 H Routing Guidelines
Table 33. Recommended Inductor Components for MCH-M PLL Filter

Value 4.7H 4.7H 4.7H Tolerance 10% 10% 30% SRF 35 MHz 47 MHz 35 MHz Rated I 30 mA 30 mA 30 mA DCR 0.56 (1 max) 0.7 (50%) 0.3 max
Table 34. Recommended Capacitor Components for MCH-M PLL Filter

Value 33 F 33 F ESL 2.5 nH 2.5 nH ESR 0.225 0.2
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8.
Hub Interface
The MCH-M and ICH3-M ballout assignments have been optimized to simplify the Hub Interface routing between these devices. Intel recommends that the Hub Interface signals be routed directly from the MCH-M to ICH3-M with all signals referenced to VSS. Layer transition should be kept to a minimum. If a layer change is required, use only two vias per net and keep all data signals and associated strobe signals on the same layer. The Hub Interface signals are broken into two groups: data signals (HL) and strobe signals (HL_STB).
Figure 44. Hub Interface Routing Example

HI_STB# HI_STB ICH3-M HI[11:0] CLK66 CLK66 MCH-M
CLK Synthesizer
8.1.
Hub Interface Routing Guidelines

This section documents the routing guidelines for the 10-bit hub interface. This hub interface connects the ICH3-M and the MCH-M. The hub interface uses a compensation signal to adjust buffer characteristics to the specific board characteristic. The hub interface requires Resistive Compensation (RCOMP). The trace impedance must equal 55 15%.
Table 35. Hub Interface RCOMP Resistor Values

Component ICH3-M MCH-M Trace Impedance 55 ohms 15% 55 ohms 15% HICOMP Resistor Value 36.5 1% 36.5 1% HICOMP Resistor Tied to VSS Vcc1_8
8.2.
Hub Interface Data Signals

These data signal traces should be routed 4 mils wide with 8 mils trace spacing (4 on8) and 12 mils spacing from other signals. In order to break out of the MCH-M and ICH3-M packages, the hub interface data signals can be routed 5-mils wide 5-mils spacing. The signal must be separated to 5-mils width with 10-mils spacing within 300 mils from the package.
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The maximum hub interface data signal trace length is six inches. Each data signal must be matched within 200 mils of the HL_STB differential pair. There is no explicit matching requirement between the individual data signals.
Table 36. Hub Interface Signals
Signal Max length (inch) 6 Width (mils) 4 Space (mils) 8 Mismatch length (mils) 200 Relative To Space with other signals (mils) 12 Notes
HUB_PD[10:0]
Differential HUB_PSTRB pair Data lines
HUB_PSTRB and HUB_PSTRB#
200
12
HUB_PSTR B and HUB_PSTR B# must be the same length (10 mils)
8.3.
Hub Interface Strobe Signals

The hub interface strobe signals should be routed as a differential pair, 4-mils wide with 8-mils trace spacing (4 on 8) and 12-mils spacing from other signals. This strobe pair should have a minimum of 12 mils spacing from any adjacent signals. The maximum length for the strobe signals is six inches. Each strobe signal must be the same length, and each data signal must be matched to within 200 mils of the strobe signals.
8.4.
HUBREF Generation/Distribution
HUBREF is the hub interface reference voltage. Depending on the buffer mode, the HUBREF voltage requirement must be set appropriately for proper operation. See the table below for the HUBREF voltage specifications and the associated resistor recommendations for the voltage divider circuit.
Table 37. Hub Interface HUBREF Generation Circuit Specifications

HUBREF Voltage Specification (V) VCC1_8 4% Recommended Resistor Values for the HUBREF Divider Circuit (Ohm) R1 = R2 = 301 1%
The single HUBREF divider should not be located more than four inches away from either the MCH-M or ICH3-M. If the single HUBREF divider is located more than four inches away, locally generated hub interface reference dividers should be used instead. The reference voltage generated by a single HUBREF divider should be bypassed to ground with a 0.1-F capacitor (C1) and at each component with a 0.01-F capacitor (C2) located close to the component HUBREF pin Figure 45. If the reference voltage is generated locally, the bypass capacitor (0.01 F) needs to be close to the component HUBREF pin Figure 46.
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Figure 45. Single HUBREF Voltage Divider
1.8V
R1 MCH-M
HUBREF
4"
4"
ICH3-M
HIREF
C1
R2
C1
C2
Figure 46. Locally Generated HUBREF Divider
1.8V
1.8V
R1 MCH-M
HUBREF
R1 <4" ICH3-M
HIREF
<4"
C2
R2
R2
C2
NOTE:
There is no C1.
8.5.
Hub Interface Decoupling Guidelines

To improve I/O power delivery, use two 0.1-F capacitors per each component (i.e. the ICH3-M and MCH-M). These capacitors should be placed within 150 mils from each package, adjacent to the rows that contain the hub interface. If the layout allows, wide metal fingers running on the VSS side of the board should connect the VCC1_8 side of the capacitors to the VCC1_8 power balls. Similarly, if layout allows, metal fingers running on the VCC1_8 side of the board should connect the groundside of the capacitors to the VSS power balls.
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9.
9.1.
I/O Subsystem
IDE Interface
This section contains guidelines for connecting and routing the ICH3-M IDE interface. The ICH3-M has two independent IDE channels. This section provides guidelines for IDE connector cabling and motherboard design, including component and resistor placement, and signal termination for both IDE channels. The ICH3-M has integrated the series resistors that have been typically required on the IDE data signals (PDD[15:0] and SDD[15:0]) running to the two ATA connectors. Additional series termination resistors may be needed; the designer should verify motherboard signal integrity through simulation. Zero Ohm series resistors can be added into the design as a stuffing option to address possible noise issues on the motherboard. The IDE interface can be routed with 4-mil traces on 7-mil spaces, and must be less than 8 inches long (from ICH3-M to IDE connector). Additionally, the shortest IDE signal (on a given IDE channel) must be less than 0.5 inches shorter than the longest IDE signal (on that channel). See Table 38.
Table 38. IDE Signals

Signal Max length (inch) 8 4 Width (mils) Space (mils) 7 Relative Mismatch max length (mils) 250 Relative To Space with other signals (mils) 8
Signal Group#ide1 IDE_PDD[15:0] IDE_SDD[15:0] IDE_PDA2 IDE_PDCS3# IDE_PATADET IDE_SATADET IDE_SEC_RST# IDE_PRI_RST# IDE_PDA0 IDE_PDA1 IDE_PDCS1# IDE_PDDACK# IDE_PDDREQ IDE_PDIOW# IDE_SDA0 IDE_SDA1 IDE_SDA2 IDE_SDCS1#
Shortest and longest IDE signal in same channel
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Signal
Max length (inch)
Width (mils)
Space (mils)
Relative Mismatch max length (mils)
Relative To
Space with other signals (mils)
IDE_SDCS3# IDE_SDDACK# IDE_SDDREQ IDE_SDIOW# Signal Group#ide2 IDE_PIORDY IDE_PDIOR# IDE_SIORDY IDE_SDIOR# Other signals INT_IRQ1 IDE_PDACTIVE # INT_IRQ15 IDE_SDACTIVE # 8 4 7 5 IDE_PIORDY with IDE_PDIOR# And IDE_SIORDY with IDE_SDIOR# 8
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9.1.1.
Primary IDE Connector Requirements
Figure 47. Connection Requirements for Primary IDE Connector
PCIRST# PDD[15:0] PDA[2:0] PDCS1# PDCS3# PDIOR# PDIOW# PDDREQ

3.3V 3.3V
PCIRST_BUF#*
22 - 47 ohm
Reset#
4.7K ohm
8.2K-10K ohm
PIORDY IRQ14 PDDACK# GPIOx

10K ohm
PDIAG#/ CBLID# CSEL N.C. Pin32,34
ICH3-M
*Due to ringing, PCIRST# must be buffered.
22- to 47- series resistors are required on RESET#. The correct value should be determined for each unique motherboard design, based on signal quality. An 8.2-k to 10-k pull-up resistor is required on IRQ14 and IRQ15 to Vcc3_3. A 4.7-k pull-up resistor to Vcc3_3 is required on PIORDY and SIORDY. Series resistors can be placed on the control and data line to improve signal quality. The resistors are placed as close to the connector as possible. Values are determined for each unique motherboard design. A 10-k pull-down resistor to ground is required on the PDIAG#/CBLID# signal. This is to prevent the GPI pin from floating if a device is not present on the Primary IDE interface.
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Primary IDE Connector
9.1.2.
Secondary IDE Connector Requirements
Figure 48. Connection Requirements for Secondary IDE Connector
PCIRST# SDD[15:0] SDA[2:0] SDCS1# SDCS3# SDIOR# SDIOW# SDDREQ

3.3V 3.3V
PCIRST_BUF#*
22 - 47 ohm
Reset#
4.7K ohm
8.2K-10K ohm
SIORDY IRQ15 SDDACK# GPIOy

10K ohm
PDIAG#/ CBLID# CSEL N.C. Pin32,34
ICH3-M
*Due to ringing, PCIRST# must be buffered.
22- to 47- series resistors are required on RESET#. The correct value should be determined for each unique motherboard design, based on signal quality. An 8.2-k to 10-k pull-up resistor is required on IRQ14 and IRQ15 to Vcc3_3. A 4.7-K pull-up resistor to Vcc3_3 is required on PIORDY and SIORDY Series resistors can be placed on the control and data line to improve signal quality. The resistors are placed as close to the connector as possible. Values are determined for each unique motherboard design.
Design Guide
Secondary IDE Connector

103
A 10-k pull-down resistor to ground is on the PDIAG#/CBLID# signal is now required on the Secondary Connector. This change is to prevent the GPI pin from floating if a device is not present on the Secondary IDE interface.
9.2.
PCI
The ICH3-M provides a PCI Bus interface that is compliant with the PCI Local Bus Specification Revision 2.2. The implementation is optimized for high-performance data streaming when the ICH3-M is acting as either the target or the initiator on the PCI bus. For more information on the PCI Bus interface, refer to the PCI Local Bus Specification Revision 2.2. The ICH3-M supports six PCI Bus masters (excluding the ICH3-M), by providing six REQ#/GNT# pairs. In addition, the ICH3-M supports two PC/PCI REQ#/GNT# pairs, one of which is multiplexed with a PCI REQ#/GNT# pair.
Figure 49. PCI Bus Layout Example
IC H 3
9.3.
AC97
The ICH3-M implements an AC97 2.1 compliant digital controller. Any Codec attached to the ICH3-M AC-link must be AC97 2.1 compliant as well. Please contact your Codec IHV for information on 2.1 compliant products. The AC97 2.1 specification is on the Intel website: http://developer.intel.com/ial/scalableplatforms/audio/index.htm The AC-link is a bi-directional, serial PCM digital stream. It handles multiple input and output data streams, as well as control register accesses, employing a time division multiplexed (TDM) scheme. The AC-link architecture provides for data transfer through individual frames transmitted in a serial fashion. Each frame is divided into 12 outgoing and 12 incoming data streams, or slots. The architecture of the ICH3-M AC-link allows a maximum of two Codecs to be connected. The following figure shows a twoCodec topology of the AC-link for the ICH3-M.
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Figure 50. ICH3-M AC97 Codec Connection
Digital AC '97 2.1 Controller

RESET# AC '97 2.1 controller section of the ICH3-M SDOUT SYNC BIT_CLK SDIN 0 SDIN 1 Primary Codec
AC / MC / AMC
AC / MC
Secondary Codec
9.3.1.
Four-Layer Layout Example

Using the assumed 4-layer stack-up, the AC97 interface can be routed using 5-mil traces with 5-mil space between the traces. Maximum length between ICH3-M to CODEC/CNR is 14 inches in a T topology. Trace impedance should be Z0 = 55 15%. Clocking is provided from the primary Codec on the link via BITCLK, and is derived from a 24.576MHz crystal or oscillator. Refer to the primary Codec vendor for crystal or oscillator requirements. BITCLK is a 12.288-MHz clock driven by the primary Codec to the digital controller (ICH3-M), and any other Codec present. That clock is used as the time base for latching and driving data. The ICH3-M supports wake on ring from S1-S5 via the AC97 link. The Codec asserts AC_SDINn to wake the system. To provide wake capability and/or caller ID, standby power must be provided to the modem Codec. The ICH3-M has weak pull-downs/pull-ups that are only enabled when the AC-Link Shut Off bit in the ICH3-M is set or if both function 5 and function 6 of device 31 are disabled (hidden). This will keep the link from floating when the AC-link is off, or there are no Codecs present. If the Shut-off bit is not set, or if neither function 5 nor function 6 of device 31 are disabled (hidden), it implies that there is a Codec on the link. Therefore, BITCLK and AC_SDOUT will be driven by the Codec and ICH3-M respectively. However, AC_SDIN0 and AC_SDIN1 may not be driven. If the link is enabled, the assumption can be made that there is at least one codec.
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9.3.2.
AC97 Audio Codec Detect Circuit and Configuration Options

The following provides general circuits to implement a number of different Codec configurations. Please refer to Intels White Paper Recommendations for ICHx/AC97 Audio (Motherboard and Communication and Network Riser) for Intels recommended Codec configurations (available at the URL given in Section 9.3). To support more than two channels of audio output, the ICH3-M allows for a configuration where two audio Codecs work concurrently to provide surround sound capabilities. To maintain data-on-demand capabilities, the ICH3-M AC97 controller, when configured for 4 or 6 channels, will wait for all the appropriate slot request bits to be set before sending data in the SDATA_OUT slots. This allows for simple FIFO synchronization of the attached Codecs. It is assumed that both Codecs will be programmed to the same sample rate and that the Codecs have identical (or at least compatible) FIFO depth requirements. Intel recommends that the Codecs be provided by the same vendor, upon the certification of their interoperability in an audio channel configuration.
9.3.3.
Valid Codec Configurations

Valid Codec Configurations AC(Primary) MC(Primary) AMC(Primary) AC(Primary) + MC(Secondary) AC(Primary) + AC(Secondary) AC(Primary) + AMC(Secondary) Invalid Codec Configurations MC(Primary) + X(any other type of Codec) AMC(Primary) + AMC(Secondary) AMC(Primary) + MC(Secondary)
Table 39. Codec Configurations
9.3.4.
SPKR Pin Consideration

SPKR is used as both the output signal to the system speaker and as a functional strap. The strap function enables or disables the TCO Timer Reboot function based on the state of the SPKR pin on the rising edge of PWROK. When enabled, the ICH3-M sends an SMI# to the processor upon a TCO timer timeout. The status of this strap is readable via the NO_REBOOT bit (bit 1, D31: F0, Offset D4h). The SPKR signal has a weak integrated pull-down resistor (the resistor is only enabled during boot/reset). Therefore, its default state is a logical zero or set to reboot. To disable the feature, a jumper can be populated to pull the signal line high (see the following figure). The value of the pull-up must be such that the voltage divider output caused by the pull-up, the effective pull-down (Reff), and the ICH3-Ms integrated pull-down resistor will be read as logic high (0.5 Vcc3_3 to Vcc3_3 + 0.5 V).
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Figure 51. Example Speaker Circuit

VCC3_3 R Value is Im plem entation Specific
Stuff Jum per to Disable Tim eout Feature (No Reboot) Effective Im pedance Due to Speaker and Codec Circuit R eff
ICH3
SPKR
Integrated Pulldown
13K - 38K
9.3.5.
AC97 Routing
To ensure the maximum performance of the codec, proper component placement and routing techniques are required. These techniques include properly isolating the codec, associated audio circuitry, analog power supplies, and analog ground planes, from the rest of the motherboard. This includes plane splits and proper routing of signals not associated with the audio section. Contact your vendor for devicespecific recommendations. The basic recommendations are as follows:
Special consideration must be given for the ground return paths for the analog signals. Digital signals routed in the vicinity of the analog audio signals must not cross the power plane split lines. Analog and digital signals should be located as far as possible from each other. Partition the board with all analog components grouped together in one area and all digital components in another. Separate analog and digital ground planes should be provided, with the digital components over the digital ground plane, and the analog components, including the analog power regulators, over the analog ground plane. The split between planes must be a minimum of 0.05 inches wide. Keep digital signal traces, especially the clock, as far as possible from the analog input and voltage reference pins. Do not completely isolate the analog/audio ground plane from the rest of the board ground plane. There should be a single point (0.25 inches to 0.5 inches wide) where the analog/isolated ground plane connects to the main ground plane. The split between planes must be a minimum of 0.05 inches wide. Any signals entering or leaving the analog area must cross the ground split in the area where the analog ground is attached to the main motherboard ground. That is, no signal should cross the split/gap between the ground planes, which would cause a ground loop, thereby greatly increasing EMI emissions and degrading the analog and digital signal quality. Analog power and signal traces should be routed over the analog ground plane. Digital power and signal traces should be routed over the digital ground plane.
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Bypassing and decoupling capacitors should be close to the IC pins, or positioned for the shortest connections to pins, with wide traces to reduce impedance. All resistors in the signal path or on the voltage reference should be metal film. Carbon resistors can be used for DC voltages and the power supply path, where the voltage coefficient, temperature coefficient, and noise are not factors. Regions between analog signal traces should be filled with copper, which should be electrically attached to the analog ground plane. Regions between digital signal traces should be filled with copper, which should be electrically attached to the digital ground plane. Locate the crystal or oscillator close to the codec.
Clocking is provided from the primary Codec on the link via BITCLK, and it is derived from a 24.576MHz crystal or oscillator. Refer to the primary Codec vendor for the crystal or oscillator requirements. BITCLK is a 12.288-MHz clock driven by the primary Codec to the digital controller (ICH3-M) and by any other Codec present. The clock is used as the time base for latching and driving data.
9.3.6.
Motherboard Implementation
The following design considerations are provided for the implementation of an ICH3-M platform using AC97. These design guidelines have been developed to ensure maximum flexibility for board designers, while reducing the risk of board-related issues. These recommendations are not the only implementation or a complete checklist, but they are based on the ICH3-M platform.
Components such as FET switches, buffers or logic states should not be implemented on the AClink signals, except for AC_RST#. Doing so would potentially interfere with timing margins and signal integrity. The ICH3-M supports wake-on-ring from S1-S5 states via the AC97 link. The Codec asserts AC_SDINn to wake the system. To provide wake capability and/or caller ID, standby power must be provided to the modem codec. If no Codec is attached to the link, internal pull-downs will prevent the inputs from floating, so external resistors are not required.
PC_BEEP should be routed through the audio codec. Care should be taken to avoid the introduction of a pop when powering the mixer up or down.
9.4.
9.4.1.
USB Guidelines and Recommendations

General Routing and Placement
Use the following general routing and placement guidelines when laying out a new design. These guidelines will help to minimize signal quality and EMI problems. The USB validation efforts focused on a four-layer motherboard where the first layer is a signal layer, the second plane is power, the third plane is ground and the fourth is a signal layer. This results in placing most of the routing on the fourth plane closest to the ground plane, and allowing a higher component density on the first plane. For mobile motherboards, with different stackup, all USB signals should be ground referenced when using the appropriate layer for routing.
Place the ICH3-M and major components on the unrouted board first. With minimum trace lengths, route high-speed clock, periodic signals and USB differential pairs first. Maintain maximum possible distance between high-speed clocks/periodic signals to USB differential pairs and any connector leaving the PCB (i.e. I/O connectors, control and signal headers, or power connectors).
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USB signals should be ground referenced. Route USB signals using a minimum of vias and corners. This reduces reflections and impedance changes. When it becomes necessary to turn 90, use two 45 turns or an arc instead of making a single 90 turn. This reduces reflections on the signal by minimizing impedance discontinuities. Do not route USB traces under crystals, oscillators, clock synthesizers, magnetic devices or ICs that use and/or duplicate clocks. Stubs on USB signals should be avoided, as stubs have an effect on signal quality. If a stub is necessary in the design, no stub should be greater than 200 mils. Route all traces over continuous planes, (VCC or GND) with no interruptions. Avoid crossing over anti-etch if at all possible. This increases inductance and radiation levels by forcing a greater loop area. Likewise, avoid changing layers with high-speed traces. Keep USB signals clear of the core logic set. High current transients are produced during internal state transitions, which can be very difficult to filter out. Keep traces at least 50 mils away from the edge of the plane. This helps prevent the coupling of the signal onto adjacent wires and also helps prevent free radiation of the signal from the edge of the PCB.
9.4.2.
USB Trace Separation

Use the following separation guidelines.
Recommended trace width and separation is 4-mil trace with a 6-mil space (90- differential impedance).
The goal is to have a 90- differential impedance and the spacing may need to be different depending on the stackup.
Maintain parallelism between USB differential signals with the trace spacing needed to achieve 90 differential impedance. Use at a minimum 20-mil spacing between USB signal pair and other traces on the PCB. This helps to prevent crosstalk. If possible, keep clock and PCI traces at least 50 mils from the USB differential pairs. Minimize the length of high-speed clock and periodic signal traces that run parallel to USB signal lines to minimize crosstalk.
9.4.3.
USB Trace Length Matching

Use the following trace length matching guidelines.
USB signal pair traces should be trace length matched.
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Table 40. USB Signals

Signal USB Signals Group USB_PN0 to USB_PN5 USB_PP0 to USB_PP5 Width (mils) 4 Space (mils) 6 Mismatch length (mils) 75 Relative To Signal differential pair Space with other signals (mils) 20 Notes Clock and PCI should be 50 mils away from USB signals (min)
9.4.4.
Plane Splits, Voids and Cut-Outs (Anti-Etch)

The following guidelines apply to the use of plane splits voids and cutouts.
9.4.4.1.
VCC Plane Splits, Voids, and Cut-Outs (Anti-Etch)

Use the following guidelines for the VCC plane.
Traces should not cross anti-etch, for it greatly increases the return path for those signal traces. This can be true of USB signals, high-speed clocks, and signal traces as well as slower signal traces that might be coupling to them. Avoid routing of USB signals 50-mil of any anti-etch to avoid coupling to the next split or radiating from the edge of the PCB.
9.4.4.2.
GND Plane Splits, Voids, and Cut-Outs (Anti-Etch)

Use the following guideline for the GND plane.
Avoid anti-etch on the GND plane.
9.4.4.3.
EMI Recommendation
Recommended a 45-pF capacitor for each data line for its USB EMI solution.
9.5.
IOAPIC (I/O Advanced Programmable Interrupt Controller)

Intel 845MP/845MZ platform does not support IOAPIC when C2/C3/C4 states are enabled.
Mobile Systems not using the IOAPIC should disable IOAPIC functionality through the system BIOS.
9.5.1.
9.5.1.1.
IOAPIC Disabling Options

Recommended Implementation
Intel recommends that IOAPIC be disabled in software while the connections to the board are as shown in Figure 52. Software can be used to turn off PICCLK from clock generator.
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To disable IOAPIC in BIOS:

ICH3-M: D31:F0; Offset: D1; bit 0 (0=disable); Mobile Pentium 4 Processor-M: MSR 1Bh bit 11 (0 = disable)
Figure 52. Minimum IOAPIC Disable Topology

33 PCIF0 APICD0 APICD1 APICLK 10K
CK-408
ICH3-M
9.5.2.
PIRQ Routing Example

PCI interrupt request signals E-H are new to the ICH3-M. These signals have been added to lower the latency caused by having multiple devices on one Interrupt line. With these new signals, a system can be designed to minimize sharing of PCI interrupt request lines. Due to different system configurations, IRQ line routing to the PCI slots (swizzling) should be made to minimize the sharing of interrupts between both internal ICH3-M functions and PCI functions. The figure below shows an example of IRQ line routing to the PCI slots (note: it is not necessarily an optimal routing scheme; an optimal scheme depends on individual system PCI IRQ usage).
Figure 53. Example PIRQ Routing
INTA INTB PIRQA# PIRQB# PIRQC# PIRQD# INTC INTD
INTA INTB INTC INTD
INTA INTB INTC INTD
INTA INTB INTC INTD
ICH3 ICH3-M
PIRQE# PIRQF# PIRQG# PIRQH#

Slot 1 PCI Device 0 (AD16 to IDSEL) Slot 2 PCI Device 5 (AD21 to IDSEL) Slot 3 PCI Device 6 (AD22 to IDSEL) Slot 4 PCI Device C (AD28 to IDSEL)
Example PIRQ Routing
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Figure 53 is an example. It is up to the board designer to route these signals in a way that will prove the most efficient for their particular system. A PCI slot can be routed to share interrupts with any of the ICH3-Ms internal device/functions (but at a higher latency cost).
9.6.
SMBus 2.0/SMLink Interface

The SMBus interface on the ICH3-M is the same as that on the ICH2-M. It uses two signals SMBCLK and SMBDATA to send and receive data from components residing on the bus. These signals are used exclusively by the SMBus Host Controller. The SMBus Host Controller resides inside the ICH3-M. If the SMBus is used only for the RAMBUS SPD EEPROMs (one on each RIMM*), both signals should be pulled up with a 4.7-k resistor to 3.3 V. The ICH3-M incorporates a SMLink interface supporting AOL*, AOL2* and a slave functionality. It uses two signals SMLINK[1:0]. SMLINK[0] corresponds to an SMBus clock signal and SMLINK[1] corresponds to an SMBus data signal. These signals are part of the SMB Slave Interface. For Alert on LAN* (AOL*) functionality, the ICH3-M transmits heartbeat and event messages over the interface. When using the 82562EM Platform LAN Connect Component, the ICH3-Ms integrated LAN Controller will claim the SMLink heartbeat and event messages and send them out over the network. An external, AOL2*-enabled LAN Controller (i.e. Gamla) will connect to the SMLink signals to receive heartbeat and event messages, as well as access the ICH3-M SMBus Slave Interface. The slave interface function allows an external microcontroller to perform various functions. For example, the slave write interface can reset or wake a system, generate SMI# or interrupts, and send a message. The slave read interface can read the system power state, read the watchdog timer status, and read system status bits. Both the SMBus Host Controller and the SMBus Slave Interface obey the SMBus 1.0 protocol, so the two interfaces can be externally wire-ORd together to allow an external management ASIC (such as Gamla) to access targets on the SMBus as well as the ICH3-M Slave interface. Additionally, the ICH3-M supports slave functionality, including the Host Notify protocol, on the SMLink pins. Therefore, in order to be fully compliant with the SMBus 2.0 specification (which requires the Host Notify cycle), the SMLink and SMBus signals must be tied together externally. This is done by connecting SMLink[0] to SMBCLK and SMLink[1] to SMBDATA.
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Figure 54. SMBUS 2.0/SMLink Interface

Host controller and slave interface SPD data Temperature on thermal sensor SMBus ICH3-M SMLink SMBCLK SMBDATA SMLink0 SMLink1 Wire OR Network interface card on PCI
Microcontroller
Intel(r) Motherboard LAN controller

smbus_smlink_IF
NOTE:
Intel does not support external access of the ICH3-Ms Integrated LAN Controller via the SMLink interface. Also, Intel does not support access of the ICH3-Ms SMBus Slave Interface by the ICH3-Ms SMBus Host Controller.
9.6.1.
9.6.1.1.
SMBus Architecture and Design Considerations

SMBus Design Considerations
There are several possibilities for designing an SMBus using the ICH3-M. Designs can be grouped into three major categories based on the power supply source for the SMBus microcontrollers. This includes two unified designs, where either Vcc_Core or Vcc_Suspend powers all devices, and a mixed design where some devices are powered by each of the two supplies. Primary considerations in choosing a design are based on the following:
Are there devices that must run in STR? Amount of Vcc_Suspend current available, i.e. minimizing load of Vcc_Suspend.
9.6.1.2.
General Design Issues/Notes

Regardless of the architecture used, there are some general considerations. The pull-up resistor size for the SMBus data and clock signals is dependent on the number of devices present on the bus. A typical value is 8.2 K. This should prevent the SMBus signals from floating, which could cause leakage in the ICH3-M and other devices.
9.6.1.3.
The Unified Vcc_ Suspend Architecture

In this design all SMBus devices are powered by the Vcc_Suspend supply. Consideration must be made to provide enough Vcc_Suspend current while in STR.
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Figure 55. Unified Vcc_Suspend Architecture
Vsus Vsus
SMBus DEVICES
Vsus
ICH3-M
SMBus
9.6.1.4.
The Unified Vcc_Core Architecture

In this design, all SMBUS devices are powered by the Vcc_Core supply. This architecture allows none of the devices to operate in STR, but minimizes the load on Vcc_Suspend.
Figure 56. Unified Vcc_Core Architecture
Vcore Vsus
SMBus DEVICES
Vsus
ICH3-M
SMBus
NOTES: 1. The SMBus device needs to be back-drive safe while its supply (Vcore) is off and Vcc_Suspend is still powered. 2. In suspended modes where Vcc_Core is OFF & Vcc_Suspend is on, the Vcc_Core node will be very near ground. In this case the input leakage of the ICH3-M will be approximately 10 A.
9.6.1.5.
Mixed Architecture
This design allows for SMBus devices to communicate while in STR, yet minimizes Vcc_Suspend leakage by keeping non-essential devices on the core supply. This is accomplished by the use of a bus switch to isolate the devices powered by the core and suspend supplies.
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Figure 57. Mixed Vcc_Suspend/Vcc_Core Architecture

Devices running in Standby Non-Standby devices
Vsus Vsus
Vsus
Vsus Vsus
Vcore
Vcore
Vcore
ICH3
SMBus 2.0
BUS SWITCH OE# SLP_S3#
SMBus2.0
Added Considerations for Mixed Architecture:

The bus switch must be powered by Vcc_Suspend If there are 5-V SMBus devices used, then an added level translator must be used to separate those devices driving 5 V from those driving 3-V signal levels. Devices that are powered by the Vcc_Suspend well must not drive into other devices that are powered off. This is accomplished with the bus switch.
9.7.
FWH
The following provides general guidelines for compatibility and design recommendations for supporting the FWH device. The majority of the changes will be incorporated in the BIOS. Refer to the FWH BIOS Specification or equivalent (contact your Field Representative for more information).
9.7.1.
FWH Decoupling
A 0.1-F capacitor should be placed between the Vcc supply pins and the Vss ground pins to decouple high frequency noise, which may affect the programmability of the device. Additionally, a 4.7-F capacitor should be placed between the Vcc supply pins and the Vss ground pins to decouple low frequency noise. The capacitors should be placed no further than 390 mils from the Vcc supply pins.
9.7.2.
In Circuit FWH Programming

All cycles destined for the FWH will appear on PCI. The ICH3-M hub interface to PCI Bridge will put all CPU boot cycles out on PCI (before sending them out on the FWH interface). If the ICH3-M is set for subtractive decode, these boot cycles can be accepted by a positive decode agent on the PCI bus. This enables the ability to boot from of a PCI card that positively decodes these memory cycles (In order to boot off a PCI card it is necessary to keep the ICH3-M in subtractive decode mode). If a PCI boot card is inserted and the ICH3-M is programmed for positive decode, there will be two devices positively decoding the same cycle. In systems with the 82380AB (ISA bridge), it is also necessary to keep the NOGO signal asserted when booting from a PCI ROM. Note that it is not possible to boot off a ROM behind the 82380AB. Once booted from the PCI card, you could potentially program the FWH in circuit and program the ICH3-M CMOS.
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9.8.
FWH Signaling Voltage Compatibility

Depending on the V_CPU_IO of the processor and the manufacturer of the FWH, there may be signaling voltage compatibility issues with the ICH3-M. The range of acceptable V_CPU_IO for the ICH3-M is 1.2 V to 2.5 V. If the processor core voltage is not within this range, translation logic will be required on the processor side before even considering the FWH. Furthermore, the FWH INIT signal trip points need to be considered because they are NOT consistent among different FWH manufacturers. The INIT signal is active low. Therefore, the inactive state of the ICH3-M INIT signal needs to be at a value slightly higher than the VIH min FWH INIT pin specification. The ICH3-M inactive state of this signal is governed by the formula V_CPU_IO - 0.13 V. Therefore if the V_CPU_IO of the processor is 1.5 V and the VIH min spec of the FWH INIT input signal is 1.35 V, there would be no compatibility issue because 1.5 V - 0.13 V = 1.37 V which is greater than the 1.35 V minimum of the FWH. If the VIH min of the FWH was 1.4 V, then there would be an incompatibility and logic translation would need to be used. Note that these examples do not take into account noise that may be encountered on INIT. Care must be taken to ensure that the VIM min specification is met with ample noise margin.
9.8.1.
FWH Vpp Design Guidelines

The Vpp pin on the FWH is used for programming the flash cells. The FWH supports Vpp of 3.3 V or 1 2 V. If Vpp is 12 V the flash cells will program about 50% faster than at 3.3 V. However, the FWH only supports 12 V Vpp for 80 hours. The 12V Vpp would be useful in a programmer environment, which is typically an event that occurs very infrequently (much less than 80 hours). The VPP pin MUST be tied to 3.3 V on the motherboard. In some instances, it is desirable to program the FWH during assembly with the device soldered down on the board. In order to decrease programming time it becomes necessary to apply 12 V to the VPP pin. The following circuit will allow testers to put 12 V on the VPP pin while keeping this voltage separated from the 3.3 V plane to which the rest of the power pins are connected. This circuit also allows the board to operate with 3.3 V on this pin during normal operation.
Figure 58. FWH VPP Isolation Circuitry

3.3V 12V
1K
FET VPP
9.9.
RTC
The ICH3-M contains a real time clock (RTC) with 256 bytes of battery backed SRAM. The internal RTC module provides two key functions: keeping date and time and storing system data in its RAM when the system is powered down. The ICH3-M uses a crystal circuit to generate a low-swing, 32-kHz,input sine wave. This input is amplified and driven back to the crystal circuit via the RTCX2 signal. Internal to the ICH3-M, the
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RTCX1 signal is amplified to drive internal logic as well as generate a free running full swing clock output for system use. This output ball of the ICHn is called SUSCLK. This is illustrated in Figure 59.
Figure 59. RTCX1 and SUSCLK Relationship in ICH3-M
Low-Swing 32.768kHz Sine Wave Source Full-Swing 32.768kHz Output Signal
RTCX1
Internal Oscillator
SUSCLK
ICH3
For further information on the RTC, please consult Application Note AP-728 ICH/ICH2/ICH2M/ICH3S/ICH3M Real Time Clock (RTC) Accuracy and Considerations Under Test Conditions. This section will present the recommended hookup for the RTC circuit for the ICH3-M.
9.9.1.
RTC Crystal
The ICH3-M RTC module requires an external oscillating source of 32.768 kHz connected on the RTCX1 and RTCX2 balls. The following figure documents the external circuitry that comprises the oscillator of the ICH3-M RTC.
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Figure 60. External Circuitry for the ICH3-M RTC
+V3ALWAYS
+V_RTC
1uF 1K
RTC_RST# 15K 1uF 1K 0.047uF BATT_SKT RTC_VBIAS 1K
10M RTC_X1 10pF
10M 32.768KHz RTC_X2
10pF
NOTES: 1. The exact capacitor value needs to be based on what the crystal maker recommends. (Typical values for C2 and C3 are 18 pF.) 2. VCCRTC: Power for RTC Well. 3. RTCX2: Feedback for the external crystal. 4. RTCX1: Input to the internal oscillator. 5. VBIAS: RTC BIAS Voltage This ball is used to provide a reference voltage, and this DC voltage sets a current, which is mirrored throughout the oscillator and buffer circuitry.
Note:
Even if the ICH3-M internal RTC is not used, it is still necessary to supply clock inputs to X1 and X2 of the ICH3-M because other signals are gated off that clock in suspend modes. However, in this case, the frequency (32.768 kHz) of the clock inputs is not critical; a lower-cost crystal can be used or a single clock input can be driven into X1 with X2 left as no connect; Figure 61 illustrates this. This is not a validated configuration with ICH3-M.
Figure 61. RTC Connections When Not Using Internal RTC
X1
32 KHz
5M
X2 Internal External
No Connection
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9.9.2.
External Capacitors
To maintain the RTC accuracy, the external capacitor C3 needs to be 0.047 F, and the capacitor values C1 and C2 should be chosen to provide the manufacturers specified load capacitance (Cload) for the crystal when combined with the parasitic capacitance of the trace, socket (if used), and package. The following equation can be used to choose the external capacitance values:
Equation 2. RTC External Capacitor Equation
Cload = [(C1 + Cin1 + Ctrace1 )*(C2 + Cin2 + Ctrace2) ]/[ (C1 + Cin1 + Ctrace1 + C2 + Cin2 + Ctrace2)] + Cparasitic Where: Cload = Crystals load capacitance. This value can be obtained from crystals specification. Cin1, Cin2 = input capacitances at RTCX1, RTCX2 balls of the ICH3-M. These values can be obtained in the ICH3-Ms datasheet. Ctrace1, Ctrace2 = Trace length capacitances measured from crystal terminals to RTCX1, RTCX2 balls. These values depend on the characteristics of board material, the width of signal traces and the length of the traces. Typical value is approximately equal to: Ctrace = trace length * 2 pF / inch (dependent upon board characteristics) Cparasitic = Crystals parasitic capacitance. This capacitance is created by the existence of two electrode plates and the dielectric constant of the crystal blank inside the crystal part. Refer to the crystals specification to obtain this value. Ideally, C1, C2 can be chosen such that C1 = C2. Using the equation of Cload above, the value of C1, C2 can be calculated to give the best accuracy (closest to 32.768 kHz) of the RTC circuit at room temperature. However, C2 can be chosen such that C2 > C1. Then C1 can be trimmed to obtain 32.768 kHz. In certain conditions, both C1, C2 values can be shifted away from the theoretical values (calculated values from the above equation) to obtain the closest oscillation frequency to 32.768 kHz. When C1, C2 value are smaller then the theoretical values, the RTC oscillation frequency will be higher. The following example will illustrates the use of the practical values C1, C2 in the case that theoretical values can not guarantee the accuracy of the RTC in low temperature condition:
Example 1:
According to a required 12-pF load capacitance of a typical crystal that is used with the ICH3-M, the calculated values of C1 = C2 is 10 pF at room temperature (250 C) to yield a 32.768-kHz oscillation. At 00 C the frequency stability of crystal gives 23 ppm (assumed that the circuit has 0 ppm at 250 C). This makes the RTC circuit oscillate at 32.767246 kHz instead of 32.768 kHz. If the values of C1 , C2 are chosen to be 6.8 pF instead of 10 pF. This will make the RTC oscillate at higher frequency at room temperature (+23 ppm) but this configuration of C1 / C2 makes the circuit oscillate closer to 32.768 kHz at 0C. The 6.8-pF value of C1 and C2 is the practical value. Note that the temperature dependency of crystal frequency is parabolic relationship (ppm / degree square). The effect of changing crystals frequency when operating at 0C (25 below room temperature) is the same when operating at 50C (25C above room temperature).
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9.9.3.
RTC Layout Considerations

Keep the RTC lead lengths as short as possible; around inch is sufficient. Minimize the capacitance between Xin and Xout in the routing. Put a ground plane under the XTAL components. Dont route switching signals under the external components (unless on the other side of the board). The oscillator Vcc should be clean; use a filter, such as an RC lowpass, or a ferrite inductor.
9.9.4.
RTC External Battery Connection

The RTC requires an external battery connection to maintain its functionality and its RAM while the ICH3-M is not powered by the system. Example batteries are: Duracell* 2032, 2025, or 2016 (or equivalent), which can give many years of operation. Batteries are rated by storage capacity. The battery life can be calculated by dividing the capacity by the average current required. For example, if the battery storage capacity is 170 mAh (assumed usable) and the average current required is 3 A, the battery life will be at least:
Equation 3. RTC External Battery Life Equation

170,000 uAh / 3 uA = 56,666 h = 6.4 years
The voltage of the battery can affect the RTC accuracy. In general, when the battery voltage decays, the RTC accuracy also decreases. . The battery voltage of the RTC must be greater than 2V at all time to ensure the accuracy of the RTC clock. The battery must be connected to the ICH3-M via an isolation Schottky diode circuit. The Schottky diode circuit allows the ICH3-M RTC-well to be powered by the battery when the system power is not available, but by the system power when it is available. To do this, the diodes are set to be reverse biased when the system power is not available. The following figure is an example of a diode circuit that is used.
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Figure 62. A Diode Circuit to Connect RTC External Battery

VCC3_3SBY
1K VccRTC 1.0uF
A standby power supply should be used in a mobile system to provide continuous power to the RTC when available, which will significantly increase the RTC battery life and thereby the RTC accuracy.
9.9.5.
RTC Routing Guidelines

All RTC OSC signals (RTCX1, RTCX2, VBIAS) should all be routed with trace lengths of less than 1 inch, the shorter the better. Minimize the capacitance between RTCX1 and RTCX2 in the routing (optimal would be a ground line between them). Put a ground plane under all of the external RTC circuitry. Dont route any switching signals under the external components (unless on the other side of the ground plane).
9.9.6.
VBIAS DC Voltage and Noise Measurements

VBIAS is a DC voltage level that is necessary for biasing the RTC oscillator circuit. This DC voltage level is filtered out from the RTC oscillation signal by the RC Network of R2 and C3 (see Figure 60) therefore it is self-adjusted voltage. Board designers should not manually bias the voltage level on VBIAS. Checking VBIAS level is used for testing purposes only to determine the right bias condition of the RTC circuit. VBIAS should be at least 200-mV DC. The RC network of R2 and C3 will filter out most of AC signal that exist on this ball, however, the noise on this ball should be kept minimal in order to guarantee the stability of the RTC oscillation. Probing VBIAS requires the same technique as probing the RTCX1, RTCX2 signals (using Op-Amp). See Application Note AP-728 for further details on measuring techniques.
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Note that VBIAS is also very sensitive to environmental conditions.
9.9.7.
SUSCLK
SUSCLK is a square waveform signal output from the RTC oscillation circuit. Depending on the quality of the oscillation signal on RTCX1 (largest voltage swing), SUSCLK duty cycle can be between 30-70%. If the SUSCLK duty cycle is beyond 30-70% range, it indicates a poor oscillation signal on RTCX1 and RTCX2. SUSCLK can be probed directly using normal probe (50- input impedance probe) and it is an appropriated signal to check the RTC frequency to determine the accuracy of the ICH3-Ms RTC Clock (see Application Note AP-728 for further details).
9.9.8.
RTC-Well Input Strap Requirements

All RTC-well inputs (RSMRST#, RTCRST#, INTRUDER# and PWROK) must be either pulled up to VCCRTC or pulled down to ground while in G3 state. RTCRST# when configured meets this requirement. RSMRST# should have a weak external pull-down (8-22 K) to ground and INTRUDER# should have a weak external pull-up to VCCRTC. This will prevent these nodes from floating in G3, and correspondingly will prevent ICCRTC leakage that can cause excessive coin-cell drain. The PWROK input signal should also be configured with an external weak pull-down of 8-22 K. The details are shown in the figure below. The arrows in bold indicate the leakage paths if appropriate pull-ups and pulldowns are not present.
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9.10.
Internal LAN Layout Guidelines

The ICH3-M provides several options for integrated LAN capability. The platform supports several components depending on the target market. These guidelines use the 82562ET to refer to both the 82562ET and 82562EM. The 82562EM is specified in those cases where there is a difference.
Table 41. Integrated LAN Capability

Platform LAN Connect component 82562EM 82562ET 82562EH Connection Advanced 10/100 Ethernet 10/100 Ethernet 1 Mb HomePNA* LAN Features AOL* & Ethernet 10/100 Connection Ethernet 10/100 Connection 1 Mb HomePNA* connection
Intel developed a dual footprint for 82562ET and 82562EH to minimize the required number of board builds. A single layout with the specified dual footprint will allow the OEM to install the appropriate Platform LAN Connect component to meet the market need.
Figure 63. ICH3-M/LAN Connect Section (Dual Footprint Option)
ICH3-M ICH3
82562EH/ 82562ET
Magnetics Module
Connector
Dual Footprint
Refer to 82562EH/82562ET Section
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Table 42. LAN Design Guide Section Reference

Layout Section ICH3-M LAN Interconnect General Routing Guidelines 82562EH 82562ET /82562EM Dual Layout Footprint Figure 13-22 Reference A B,C,D B C D Design Guide Section ICH3-M LAN Interconnect Guidelines
9.10.1.
ICH3-M LAN Interconnect Guidelines

This section contains guidelines to the design of motherboards and riser cards to comply with LAN Connect. It should not be treated as a specification and the system designer must ensure through simulations or other techniques that the system meets the specified timings. Special care must be given to matching the LAN_CLK traces to those of the other signals, as shown below. The following are guidelines for the ICH3-M to LAN component interface. The following signal lines are used on this interface:
LAN_CLK LAN_RSTSYNC LAN_RXD[2:0] LAN_TXD[2:0]
This interface supports both 82562EH and 82562ET/82562EM components. Signal lines LAN_CLK, LAN_RSTSYNC, LAN_RXD[0], and LAN_TXD[0] are shared by both components. Signal lines LAN_RXD[2:1] and LAN_TXD[2:1] are not connected when 82562EH is installed. Dual footprint guidelines are found in Figure 63.
Bus Topologies
The LAN Connect Interface can be configured in several topologies:

Direct point-to-point connection between the ICH3-M and the LAN component Dual Footprint LOM/CNR Implementation
9.10.1.1.
Point-to-point Interconnect
The following are guidelines for a single solution motherboard. Either 82562EH, 82562ET, or CNR is installed.
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Figure 64. Single Solution Interconnect
L
LAN_CLK LAN_RSTSYNC Platform LAN Connect (PLC)
ICH3-M ICH3
LAN_RXD[2:0] LAN_TXD[2:0]
Table 43. LAN Design Guide Point-to-Point Length Requirements

Length Requirements From the Previous Figure Configuration: 82562EH 82562ET CNR A L = 4.5 to 10 (Signal Lines LAN_RXD[2:1] and LAN_TXD[2:1] not connected) L = 3.5 to 10 L = 3 to 9 (0.5 to 3 on card)
9.10.1.2.
Signal Routing and Layout

LAN Connect signals must be carefully routed on the motherboard to meet the timing and signal quality requirements of this interface specification. The following are some general guidelines that should be followed. Intel recommends that the board designer simulate the board routing to verify that the specifications are met for flight times and skews due to trace mismatch and crosstalk. On the motherboard the length of each data trace is either equal in length to the LAN_CLK trace or up to 0.5 inches shorter than the LAN_CLK trace. (LAN_CLK should always be the longest motherboard trace in each group.)
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Figure 65. LAN_CLK Routing Example
LAN_CLK
LAN RXD0
9.10.1.3.
Crosstalk Consideration
Noise due to crosstalk must be carefully controlled to a minimum. Crosstalk is the key cause of timing skews and is the largest part of the tRMATCH skew parameter. tRMATCH is the sum of the trace length mismatch between LAN_CLK and the LAN data signals. To meet this requirement on the board, the length of each data trace is either equal to or up to 0.5 inches shorter than the LAN_CLK trace. Maintaining at least 100 mils of spacing should minimize noise due to crosstalk from non-PLC signals.
9.10.1.4.
Impedances
The motherboard impedances should be controlled to minimize the impact of any mismatch between the motherboard and the daughtercard. An impedance of 60 10% is strongly recommended; otherwise, signal integrity requirements may be violated.
9.10.1.5.
Line Termination
Line termination mechanisms are not specified for the LAN Connect interface. Slew rate controlled output buffers achieve acceptable signal integrity by controlling signal reflection, over/undershoot, and ringback. A 33- series resistor can be installed at the driver side of the interface should the developer have concerns about over/undershoot. Note that the receiver must allow for any drive strength and board impedance characteristic within the specified ranges.
9.10.2.
9.10.2.1.
General LAN Routing Guidelines and Considerations

General Trace Routing Considerations
Trace routing considerations are important to minimize the effects of crosstalk and propagation delays on sections of the board where high-speed signals exist. Signal traces should be kept as short as possible to decrease interference from other signals, including those propagated through power and ground planes. Observe the following suggestions to help optimize board performance.
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Note:
Some suggestions are specific to a 4.5-mil stackup.

Maximum mismatch between the length of the clock trace and the length of any data trace is 0.5 inches (clock trace must be longest). See Table 44 below for summary of recommendations Maintain constant symmetry and spacing between the traces within a differential pair. Keep the signal trace lengths of a differential pair equal to each other. Keep the total length of each differential pair under 4 inches. [Many customer designs with differential traces longer than 5 inches have had one or more of the following issues: IEEE phy conformance failures, excessive EMI, and/or degraded receive BER.] Do not route the transmit differential traces closer than 100 mils to the receive differential traces. Do not route any other signal traces both parallel to the differential traces, and closer than 100 mils to the differential traces (300 mils is recommended). Keep maximum separation between differential pairs to 7 mils. For high-speed signals, the number of corners and vias should be kept to a minimum. If a 90 bend is required, Intel recommends using two 45 bends instead. Traces should be routed away from board edges by a distance greater than the trace height above the ground plane. This allows the field around the trace to couple more easily to the ground plane rather than to adjacent wires or boards. Do not route traces and vias under crystals or oscillators. This will prevent coupling to or from the clock. And as a general rule, place traces from clocks and drives at a minimum distance from apertures by a distance that is greater than the largest aperture dimension.
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Table 44. LAN Signals

Signal Max length (inch) Widt h (mils) Space btwn diff pair (mils) *4 Space btwn trans. recv. diff pair or other signals(mils ) 8 Mismatc h relative max. (mils) Relative To Notes
Signals Group#lan1 LAN_RXD0 to LAN_RXD2 LAN_TXD0 to LAN_TXD2 LAN_RST Signals Group#lan2 TDP (pin9, J23A) TDN (pin10, J23A) LAN_RDP LAN_RDN LAN_JCL LAN_JCLK
10 (min 3.5)
-500
LAN_JCLK
Diff. Pair must be the same length (10 mils)
100
+/-10
Signals Group#lan2 diff pair
Diff. Pair must be the same length (10 mils)
10 (min 3.5)
none
16
+500
Signals Group#lan1
LAN_JCLK is equal to Signals Group#lan 1 or longer by 500 mil (max)
NOTE: *This parameter is not for diff pairs, it is the space between datalines.
Figure 66. Trace Routing
45
Trace Routing
9.10.2.1.1.
Trace Geometry and Length

The key factors in controlling trace EMI radiation are the trace length and the ratio of trace-width to trace-height above the ground plane. To minimize trace inductance, high-speed signals and signal layers that are close to a ground or power plane should be as short and wide as practical. Ideally, this trace width to height above the ground plane ratio is between 1:1 and 3:1. To maintain trace impedance, the width of the trace should be modified when changing from one board layer to another if the two layers
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are not equidistant from the power or ground plane. Differential trace impedances should be controlled to be ~100 ohms. It is necessary to compensate for trace-to-trace edge coupling, which can lower the differential impedance by up to 10 ohms, when the traces within a pair are closer than 30 mils (edge to edge). Traces between decoupling and I/O filter capacitors should be as short and wide as practical. Long and thin traces are more inductive and would reduce the intended effect of decoupling capacitors. Also for similar reasons, traces to I/O signals and signal terminations should be as short as possible. Vias to the decoupling capacitors should be sufficiently large in diameter to decrease series inductance. Additionally, the PLC should not be closer than one inch to the connector/magnetic/edge of the board.
9.10.2.1.2.
Signal Isolation
Some rules to follow for signal isolation:
Separate and group signals by function on separate layers if possible. Maintain a gap of 100 mils between all differential pairs (Phone line and Ethernet) and other nets, but group associated differential pairs together.
NOTE: Over the length of the trace run, each differential pair should be at least 0.3 inches away from any parallel signal traces.
Physically group together all components associated with one clock trace to reduce trace length and radiation. Isolate I/O signals from high speed signals to minimize cross talk, which can increase EMI emission and susceptibility to EMI from other signals. Avoid routing high-speed LAN or Phone line traces near other high-frequency signals associated with a video controller, cache controller, CPU, or other similar devices.
9.10.2.2.
Power and Ground Connections

Some rules and guidelines to follow for power and ground connections:
All Vcc pins should be connected to the same power supply. All Vss pins should be connected to the same ground plane. Four to six decoupling capacitors, including two 4.7-F capacitors are recommended Place decoupling as close as possible to power pins.
9.10.2.2.1.
General Power and Ground Plane Considerations

To properly implement the common mode choke functionality of the magnetic module the chassis or output ground (secondary side of transformer) should be separated from the digital or input ground (primary side) by a physical separation of 100 mils minimum.
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Figure 67. Ground Plane Separation
Separate Chassis Ground Plane
Good grounding requires minimizing inductance levels in the interconnections and keeping ground returns short, signal loop areas small, and power inputs bypassed to signal return, will significantly reduce EMI radiation. Some rules to follow that will help reduce circuit inductance in both backplanes and motherboards.
Route traces over a continuous plane with no interruptions (dont route over a split plane). If there are vacant areas on a ground or power plane, avoid routing signals over the vacant area. This will increase inductance and EMI radiation levels. Separate noisy digital grounds from analog grounds to reduce coupling. Noisy digital grounds may affect sensitive DC subsystems. All ground vias should be connected to every ground plane; and every power via should be connected to all power planes at equal potential. This helps reduce circuit inductance. Physically locate grounds between a signal path and its return. This will minimize the loop area. Avoid fast rise/fall times as much as possible. Signals with fast rise and fall times contain many high frequency harmonics that can radiate EMI. The ground plane beneath the filter/transformer module should be split. The RJ45 and/or RJ11 connector side of the transformer module should have chassis ground beneath it. By splitting ground planes beneath transformer, noise coupling between the primary and secondary sides of the transformer and between the adjacent coils in the transformer is minimized. There should not be a power plane under the magnetic module. Create a spark gap between pins 2 through 5 of the Phone line connector(s) and shield ground of 1.6 mm (59.0 mil). This is a critical requirement needed to past FCC part 68 testing for phone line connection. Note: For worldwide certification, a trench of 2.5 mm is required. In North America, the spacing requirement is 1.6 mm. However, home networking can be used in other parts of the world, including Europe, where some Nordic countries require the 2.5-mm spacing.
9.10.2.3.
9.10.2.3.1.
A Four-Layer Board Design (Example)

Top Layer Routing
Sensitive analog signals are routed completely on the top layer without the use of vias. This allows tight control of signal integrity and removes any impedance inconsistencies due to layer changes.
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9.10.2.3.2.
Ground Plane
A layout split (100 mils) of the ground plane under the magnetic module between the primary and secondary side of the module is recommended. It is also recommended to minimize the digital noise injected into the 82562 common ground plane. Suggestions include optimizing decoupling on neighboring noisy digital components, isolating the 82562 digital ground using a ground cutout, etc.
9.10.2.3.3.
Power Plane
Physically separate digital and analog power planes must be provided to prevent digital switching noise from being coupled into the analog power supply planes VDD_A. Analog power may be a metal fill island, separated from digital power, RC filtered from the digital power.
9.10.2.3.4.
Bottom Layer Routing

The digital high-speed signals that include all of the LAN interconnect interface signals are routed on the bottom layer.
9.10.2.4.
Common Physical Layout Issues

Here is a list of common physical layer design and layout mistakes in LAN On Motherboard Designs.
Unequal length of the two traces within a differential pair. Inequalities create common-mode noise and will distort the transmit or receive waveforms. Lack of symmetry between the two traces within a differential pair. [Each component and/or via that one trace encounters, the other trace must encounter the same component or a via at the same distance from the PLC.] Asymmetry can create common-mode noise and distort the waveforms. Excessive distance between the PLC and the magnetic or between the magnetic and the RJ-45/11 connector. Beyond a total distance of about 4 inches, it can become extremely difficult to design a spec-compliant LAN product. Long traces on FR4 (fiberglass epoxy substrate) will attenuate the analog signals. Also, any impedance mismatch in the traces will be aggravated if they are longer (see #9 below). The magnetic should be as close to the connector as possible (less than or equal to one inch). Routing any other trace parallel to and close to one of the differential traces. Crosstalk getting onto the receive channel will cause degraded long cable BER. Crosstalk getting onto the transmit channel can cause excessive emissions (failing FCC) and can cause poor transmit BER on long cables. At a minimum, other signals should be kept 0.3 inches from the differential traces. Routing the transmit differential traces next to the receive differential traces. The transmit trace that is closest to one of the receive traces will put more crosstalk onto the closest receive trace and can greatly degrade the receiver's BER over long cables. After exiting the PLC, the transmit traces should be kept 0.3 inches or more away from the nearest receive trace. The only possible exceptions are in the vicinities where the traces enter or exit the magnetic, the RJ-45/11, and the PLC. Use of an inferior magnetic module. The magnetic modules that we use have been fully tested for IEEE PLC conformance, long cable BER, and for emissions and immunity. (Inferior magnetic modules often have less common-mode rejection and/or no auto transformer in the transmit channel.)
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Use of an 82555 or 82558 physical layer schematic in a PLC design. The transmit terminations and decoupling are different. There are also differences in the receive circuit. Please follow the appropriate reference schematic or Ap-Note. Not using (or incorrectly using) the termination circuits for the unused pins at the RJ-45/11 and for the wire-side center-taps of the magnetic modules. These unused RJ pins and wire-side center-taps must be correctly referenced to chassis ground via the proper value resistor and a capacitance or termplane. If these are not terminated properly, there can be emissions (FCC) problems, IEEE conformance issues, and long cable noise (BER) problems. The Ap-Notes have schematics that illustrate the proper termination for these unused RJ pins and the magnetic center-taps. Incorrect differential trace impedances. It is important to have ~100 ohms impedance between the two traces within a differential pair. This becomes even more important as the differential traces become longer. It is very common to see customer designs that have differential trace impedances between 75 ohms and 85 ohms, even when the designers think they've designed for 100 ohms. (To calculate differential impedance, many impedance calculators only multiply the single-ended impedance by two. This does not take into account edge-to-edge capacitive coupling between the two traces. When the two traces within a differential pair are kept close to each other the edge coupling can lower the effective differential impedance by 5 to 20 ohms. A 10-ohm to 15-ohm drop in impedance is common.) Short traces will have fewer problems if the differential impedance is a little off. Use of capacitor that is too large between the transmit traces and/or too much capacitance from the magnetic's transmit center-tap (on the 82562ET side of the magnetic) to ground. Using capacitors more than a few pF in either of these locations can slow the 100 Mbps rise and fall time so much that they fail the IEEE rise time and fall time specs. This will also cause return loss to fail at higher frequencies and will degrade the transmit BER performance. Caution should be exercised if a cap is put in either of these locations. If a cap is used, it should almost certainly be less than 22 pF. [6 pF to 12-pF values have been used on past designs with reasonably good success.] These caps are not necessary, unless there is some overshoot in 100-Mbps mode.
It is important to keep the two traces within a differential pair close to each other. Keeping them close helps to make them more immune to crosstalk and other sources of common-mode noise. This also means lower emissions (i.e. FCC compliance) from the transmit traces, and better receive BER for the receive traces. Close should be considered to be less than 0.030 inches between the two traces within a differential pair. 0.007 inch trace-to-trace spacing is recommended.
9.10.3.
9.10.3.1.
82562EH Home/PNA* Guidelines

Related Docs
82562EH HomePNA* 1 Mb/s Physical Layer Interface Product Preview Datasheet RS-82562EH 1Mb/s Home PNA LAN Connect Option Application Note Both of the above documents are available at: http://developer.intel.com/design/network/home/82562eh.htm
For correct LAN performance, designers must follow the general guidelines outlined in Section 9.10.2. Additional guidelines for implementing an 82562EH Home/PNA* Platform LAN Connect component are provided below.
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9.10.3.2.
Power and Ground Connections

Some rules to follow for power and ground connections:
For best performance place decoupling capacitors on the backside of the PCB directly under the 82562EH with equal distance from both pins of the capacitor to power/ground. The analog power supply pins for 82562EH (VCCA, VSSA) should be isolated from the digital VCC and VSS through the use of ferrite beads. In addition, adequate filtering and decoupling capacitors should be provided between VCC and VSS, and VCCA, and VSSA power supplies.
9.10.3.3.
Guidelines for 82562EH Component Placement

Component placement can affect signal quality, emissions, and temperature of a board design. This section will provide guidelines for component placement. Careful component placement can:
Decrease potential problems directly related to electromagnetic interference (EMI), which could cause failure to meet FCC specifications. Simplify the task of routing traces. To some extent, component orientation will affect the complexity of trace routing. The overall objective is to minimize turns and crossovers between traces.
Minimizing the amount of space needed for the HomePNA* LAN interface is important because all other interface will compete for physical space on a motherboard near the connector edge. As with most subsystems, the HomePNA* LAN circuits need to be as close as possible to the connector. Thus, it is imperative that all designs be optimized to fit in a very small space.
9.10.3.4.
Crystals and Oscillators

To minimize the effects of EMI, clock sources should not be placed near I/O ports or board edges. Radiation from these devices may be coupled onto the I/O ports or out of the system chassis. Crystals should also be kept away from the HomePNA* magnetic module to prevent interference of communication. The retaining straps of the crystal (if they should exist) should be grounded to prevent possibility radiation from the crystal case and the crystal should lay flat against the PC board to provide better coupling of the electromagnetic fields to the board. For a noise free and stable operation, place the crystal and associated discretes as close as possible to 82562EH, keeping the length as short as possible and do not route any noisy signals in this area.
9.10.3.5.
Phoneline HPNA Termination

The transmit/receive differential signal pair is terminated with a pair of 51.1- (1%) resistors. This parallel termination should be placed close to the 82562EH. The center, common point between the 51.1 resistors is connected to a voltage divider network. The opposite end of one 806- resistor is tied to VCCA (3.3 V), and the opposite end of the other 806- resistor and the cap are connected to ground. The termination is shown in the following figure.
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Figure 68. 82562EH Termination
The filter and magnetic component T1, integrates the required filter network, high-voltage impulse protection, and transformer to support the HomePNA* LAN interface. One RJ-11 jack (labeled LINE in the above figure) allows the node to be connected to the phoneline, and the second jack (labeled PHONE in the above figure) allows other downline devices to be connected at the same time. This second connector is not required by HomePNA*. However, typical PCI adapters and PC motherboard implementations are likely to include it for user convenience. A low-pass filter, setup in-line with the second RJ-11 jack is also recommended by the HomePNA* to minimize interference between the HomeRun connection and a POTs voice or modem connection on the second jack. This places a restriction of the type of devices connected to the second jack as the pass-band of this filter is set approximately at 1.1 MHz. Please refer to the HomePNA* website: www.homepna.org for up-to-date information and recommendations regarding the use of this low-pass filter to meet HomePNA* certifications.
9.10.3.6.
Critical Dimensions
There are three dimensions to consider during layout. Distance A from 82562EH to the magnetic module, distance B from the line RJ11 connector to the magnetic module, and distance C from the phone RJ11 to the LPF (if implemented).
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Figure 69. Critical Dimensions for Component Placement
B C
ICH3-M
Gilad
Magnetics Module
Line RJ11
LPF
Phone RJ11
EEPROM
Table 45. 82562EH Home/PNA* Critical Dimensions for Component Placement

Distance B A C Priority 1 2 3 Guideline < 1 inch < 1 inch < 1 inch
9.10.3.6.1.
Distance from Magnetic Module to Line RJ11

This distance B should be given highest priority and should be less then 1 inch. In regards to trace symmetry, route differential pairs with consistent separation and with exactly the same lengths and physical dimensions. Asymmetrical and unequal length in the differential pairs contribute to common mode noise and this can degrade the receive circuit performance and contribute to radiated emissions from the transmit side.
9.10.3.6.2.
Distance from 82562EH to Magnetic Module

Due to the high-speed of signals present, distance A between the 82562EH and the magnetic should also be less than 1 inch, but should be second priority relative to distance form connects to the magnetic module. And in general, any section of trace that is intended for use with high-speed signals should observe proper termination practices. Proper signal termination can reduce reflections caused by impedance mismatches between device and traces route. The reflections of a signal may have a high-frequency component that may contribute more EMI than the original signal itself.
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9.10.3.6.3.
Distance from LPF to Phone RJ11

This distance C should be less then 1 inch. In regards to trace symmetry, route differential pairs with consistent separation and with exactly the same lengths and physical dimensions. Asymmetrical and unequal length in the differential pairs contribute to common mode noise and this can degrade the receive circuit performance and contribute to radiated emissions from the transmit side.
9.10.4.
9.10.4.1.
82562ET / 82562EM Guidelines

Related Docs
82562ET LAN on Motherboard Design Guide (AP-414): OR-2336 82562ET/EM PCB Design Platform LAN Connect (AP-412): OR-2059 82562ET 10/100 Mbps Platform LAN Connect (PLC) Product Datasheet (Order# A00358-004), available at http://www-niooem.jf.intel.com/components.htm and on IBL
For correct LAN performance, designers must follow the general guidelines outlined in Section 9.10.2. Additional guidelines for implementing an 82562ET or 82562EM Platform LAN Connect component are provided below.
9.10.4.2.
Guidelines for 82562ET / 82562EM Component Placement

Component placement can affect signal quality, emissions, and temperature of a board design. This section will provide guidelines for component placement. Careful component placement can:
Decrease potential problems directly related to electromagnetic interference (EMI), which could cause failure to meet FCC and IEEE test specifications. Simplify the task of routing traces. To some extent, component orientation will affect the complexity of trace routing. The overall objective is to minimize turns and crossovers between traces.
Minimizing the amount of space needed for the Ethernet LAN interface is important because all other interface will compete for physical space on a motherboard near the connector edge. As with most subsystems, the Ethernet LAN circuits need to be as close as possible to the connector. Thus, it is imperative that all designs be optimized to fit in a very small space.
9.10.4.3.
Crystals and Oscillators

To minimize the effects of EMI, clock sources should not be placed near I/O ports or board edges. Radiation from these devices may be coupled onto the I/O ports or out of the system chassis. Crystals should also be kept away from the Ethernet magnetic module to prevent interference of communication. The retaining straps of the crystal (if they should exist) should be grounded to prevent possibility radiation from the crystal case and the crystal should lay flat against the PC board to provide better coupling of the electromagnetic fields to the board. For a noise free and stable operation, place the crystal and associated discrete as close as possible to the 82562ET or 82562EM, keeping the trace length as short as possible and do not route any noisy signals in this area.
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9.10.4.4.
82562ET/82562EM Termination Resistors

The 100- (1%) resistor used to terminate the differential transmit pairs (TDP/TDN) and the 100- (1%) receive differential pairs (RDP/RDN) should be placed as close to the Platform LAN Connect component (82562ET or 82562EM) as possible. This is due to the fact these resistors are terminating the entire impedance that is seen at the termination source (i.e. 82562ET), including the wire impedance reflected through the transformer.
Figure 70. 82562ET/82562EM Termination
LAN Interface
82562ET
Magnetics Module
RJ45
Place termination resistors as close to the 82562ET as possible
9.10.4.5.
Critical Dimensions
There are two dimensions to consider during layout. Distance B from the line RJ45 connector to the magnetic module and distance A from the 82562ET or 82562EM to the magnetic module. The combined total distances A and B must not exceed 4 inches (preferably, less than 2 inches). See Figure 71 below.
Figure 71. Critical Dimensions for Component Placement
ICH3-M ICH2
82562EM/ 82562ET
Magnetics Module
Line RJ45
EEPROM
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Table 46. 82562ET / 82562EM Critical Dimensions for Component Placement

Distance A B Priority 1 2 Guideline < 1 inch < 1 inch
9.10.4.5.1.
Distance from Magnetic Module to RJ45

The distance A in the above figure should be given the highest priority in board layout. The distance between the magnetic module and the RJ45 connector should be kept to less than one inch of separation. The following trace characteristics are important and should be observed:
Differential Impedance: The differential impedance should be 100 . The single ended trace impedance will be approximately 50 . However, the differential impedance can also be affected by the spacing between the traces. Trace Symmetry: Differential pairs (such as TDP and TDN) should be routed with consistent separation and with exactly the same lengths and physical dimensions (for example, width).
Caution:
Asymmetric and unequal length traces in the differential pairs contribute to common mode noise. This can degrade the receive circuits performance and contribute to radiated emissions from the transmit circuit. If the 82562ET must be placed further than a couple of inches from the RJ45 connector, distance B can be sacrificed. Keeping the total distance between the 82562ET and RJ-45 will as short as possible should be a priority. Measured trace impedance for layout designs targeting 100 often result in lower actual impedance. OEMs should verify actual trace impedance and adjust their layout accordingly. If the actual impedance is consistently low, a target of 105-110 should compensate for second order effects.
9.10.4.5.2.
Distance from 82562ET to Magnetic Module

Distance B should also be designed to be less than one inch between devices. The high-speed nature of the signals propagating through these traces requires that the distance between these components be closely observed. In general, any section of traces that is intended for use with high-speed signals should observe proper termination practices. Proper termination of signals can reduce reflections caused by impedance mismatches between device and traces. The reflections of a signal may have a high frequency component that may contribute more EMI than the original signal itself. For this reason, these traces should be designed to a 100- differential value. These traces should also be symmetric and equal length within each differential pair.
9.10.4.6.
Reducing Circuit Inductance

The following guidelines show how to reduce circuit inductance in both back planes and motherboards. Traces should be routed over a continuous ground plane with no interruptions. If there are vacant areas on a ground or power plane, the signal conductors should not cross the vacant area. This increases inductance and associated radiated noise levels. Noisy logic grounds should be separated from analog signal grounds to reduce coupling. Noisy logic grounds can sometimes affect sensitive DC subsystems such as analog to digital conversion, operational amplifiers, etc. All ground vias should be connected to every ground plane; and similarly, every power via, to all power planes at equal potential. This helps reduce circuit inductance. Another recommendation is to physically locate grounds to minimize the loop area between a signal path and its return path. Rise and fall times should be as slow as possible because signals with fast rise and fall times contain many high frequency harmonics that can radiate significantly.
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The most sensitive signal returns closest to the chassis ground should be connected together. This will result in a smaller loop area and reduce the likelihood of crosstalk. The effect of different configurations on the amount of crosstalk can be studied using electronics modeling software.
9.10.4.6.1.
Terminating Unused Connections

In Ethernet designs it is common practice to terminate unused connections on the RJ-45 connector and the magnetic module to ground. Depending on overall shielding and grounding design, this may be done to the chassis ground, signal ground, or a termination plane. Care must be taken when using various grounding methods to insure that emission requirements are met. The method most often implemented is called the Bob Smith Termination. In this method a floating termination plane is cut out of a power plane layer. This floating plane acts as a plate of a capacitor with an adjacent ground plane and couples capacitively to the ground plane creating the required 1500 pF of capacitance. The signals can be routed through 75- resistors to the plane. Stray energy on unused balls is then carried to the plane.
9.10.4.6.2.
Termination Plane Capacitance

It is recommended that the termination plane capacitance equal a minimum value of 1500 pF. This helps reduce the amount of crosstalk on the differential pairs (TDP/TDN and RDP/RDN) from the unused pairs of the RJ45. Pads may be placed for an additional capacitance to chassis ground, which may be required if the termplane capacitance is not large enough to pass EFT (Electrical Fast Transient) testing. If a discrete capacitor is used, to meet the EFT requirements it should be rated for at least 1000 Vac.
Figure 72. Termination Plane

TDP
N/C
TDN RDP RDN Magnetics Module
RJ-45
Termination Plane
Addition Capacitance that may need to be added for EFT testing
9.10.5.
82562ET/82562EH Dual Footprint Guidelines

These guidelines characterize the proper layout for a dual footprint solution. This configuration enables the developer to install either the 82562EH or the 82562ET/82562EM components while having only one motherboard design. The following are guidelines for the 82562ET/82562EH Dual Footprint option.
Design Guide 139
The dual footprint for this particular solution uses a SSOP footprint for 82562ET and a TQFP footprint for 82562EH. The combined footprint for this configuration is shown in the below two figures.
Figure 73. Dual Footprint LAN Connect Interface
L
8 2 5 6 2 E T
S S O P
ICH3-M
LAN_CLK LAN_RSTSYNC LAN_RXD[2:0] LAN_TXD[2:0]
ICH3
82562EH
TQFP
Stub
Figure 74. Dual Footprint Analog Interface
82562EH/82562ET
Tip TDP TDN RDP RDN Ring
RJ11
Magnetics Module
82562EH Config.
TXP TXN
RJ45 82562ET Config.
The following are additional guidelines for this configuration:

L = 0.5 inches to 6.5 inches Stub < 0.5 inches Either 82562EH or 82562ET/82562EM can be installed. Not both 82562ET pins 28, 29, and 30 overlap with 82562EH pins 17, 18, and 19. Overlapping pins are tied to ground. No other signal pads should overlap or touch. The 82562EH and 82562ET configurations share signal lines LAN_CLK, LAN_RSTSYNC, LAN_RXD[0], LAN_TXD[0], RDP, RDN, RXP/Ring, and RXN/Tip.
140
Design Guide
No stubs should be present when 82562ET is installed. Packages used for the Dual Footprint are TQFP for 82562EH and SSOP for 82562ET. A 22- resistor can be placed at the driving side of the signal line to improve signal quality on the LAN connect interface. Resistor should be placed as close as possible to the component. Use components that can satisfy both the 82562ET and 82562EH configurations (i.e. magnetic module). Install components for either the 82562ET or the 82562EH configuration. Only one configuration can be installed at a time. Route shared signal lines such that stubs are not present or are kept to a minimum. Stubs may occur on shared signal lines (i.e. RDP and RDN). These stubs are due to traces routed to an uninstalled component. In an optimal layout, there should be no stubs. Use 0- resistors to connect and disconnect circuitry not shared by both configurations. Place resistor pads along the signal line to reduce stub lengths. Traces from magnetic to connector must be shared and not stubbed. An RJ-11 connector that fits into the RJ-45 slot is available. Any amount of stubbing will destroy both HomePNA* and Ethernet performance.
Design Guide
141
10.
10.1.
Platform Clock Routing Guidelines

Clock Generation
Only one clock generator component is required in an Intel 845MP/845MZ chipset-based system. Clock synthesizers that meet the Intel CK-408 Clock Synthesizer/Driver Specification are suitable for an Intel 845MP/845MZ chipset based system. For more information on CK-408 compliance, refer to the CK-408 Clock Synthesizer/Driver Specification Document. The following tables and figure list and detail the Intel 845MP/845MZ clock groups, the platform system clock cross-reference, and the platform clock distribution:
Table 47. Intel 845MP/845MZ Clock Groups

Clock Name Frequency Receiver
Host_CLK CLK66 AGPCLK CLK33 CLK14 PCICLK USBCLK APIC_CLK
100 MHz 66 MHz 66 MHz 33 MHz 14.318 MHz 33 MHz 48 MHz 33 MHz
CPU, Debug Port, and MCH-M MCH-M and Intel ICH3-M AGP Connector or AGP Device Intel ICH3-M, SIO, Glue Chip, and FWH Intel ICH3-M and SIO PCI Connector Intel ICH3-M Intel ICH3-M (not used on 845MP/845MZ platform)
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Design Guide
Table 48. Platform System Clock Cross-reference

Clock Group CK-408 Pin Component Component Pin Name
HOST_CLK
CPU# CPU CPU# CPU CPU# CPU
CPU CPU Debug Port Debug Port MCH-M MCH-M MCH-M ICH3-M
BCLK[0] BCLK[1] BCLK[0] BCLK[1] BCLK[0] BCLK[1] 66IN CLK66 CLK PCICLK PCI_CLK CLK_IN CLK CLK14 CLOCKI CLK CLK CLK CLK48 APICCLK
CLK66
66BUFF
AGPCLK CLK33
66BUFF PCIF PCI PCI PCI
AGP Connector or AGP Device ICH3-M SIO Glue Chip FWH ICH3-M SIO
CLK14
REF0
PCICLK
PCI
PCI Connector #1 PCI Connector #2 PCI Connector #3
USBCLK APICCLK
USB PCIF
ICH3-M ICH3-M
Design Guide
143
Figure 75. Processor BCLK Topology

100 MHz 100 MHz
CPU# CPU
CPU
BCLK0 BCLK1
CPU# CPU
100 MHz 100 MHz
Debug Port
BCK# BCK
MCH-M
CPU# CPU 66Buff
100 MHz 100 MHz 66 MHz
HCLKINN HCLKINP 66IN
66Buff 66Buff
66 MHz 66 MHz 33 MHz 48 MHz
AGP Connector
CLK
ICH3-M
CLK66 PCICLK CLK48
CK-408
PCIF USB
14.318 MHz
CLK14
PCI Connectors
PCI PCI PCI
33 MHz
CLK CLK CLK
33 MHz 33 MHz
REFO PCI PCI
14.318 MHz 33 MHz 33 MHz
SIO
CLOCKI PCI_CLK
Glue Chip
CLK_IN
FWH
PCI
33 MHz
CLK
NOTE:
Debug Port must always be BCLK3.
144
Design Guide
10.2.
10.2.1.
Clock Control
CK-408 Delay Circuit Recommendation
Ensure the processor gets power before receiving the clock. Follow Figure 76.
Figure 76. ICH3-M Follows the CK-408 Power-up
CK 408 VTT_PWRGD#
VCC_CORE
Delay Circuit 8-9ms
ICH3-M V_GATE
10.2.2.
SLP_S1#
When asserted SLP_S1# indicates that the system is in the S1-M power state. SLP_S1# needs to be connected to clock generator PWRDWN# to shut off the system clocks in S1-M state. While entering S3 state, SLP_S1# initially asserts, but then goes high briefly when PCIRST# asserts, and then fades to low/off when the ICH3-M main I/O power rail is switched off. The duration of SLP_S1# going high is platform dependent since it is related to turning off of the ICH3-M main I/O power rail. If SLP_S1# is directly connected to the PWRDWN# pin of a CK-408 compatible clock generator, then during S3 entry, the clock generator's outputs may be momentarily turned ON when SLP_S1# deasserts (due to PCIRST# assertion); and then turned OFF when the ICH3-MM main I/O power rail is switched off (causing SLP_S1# to fade to low/off) or when power to the clock generator is turned off, whichever occurs first. The clock restart and the subsequent clock stop are not guaranteed to be clean. In systems that incorporate any peripherals which are not reset during S3 and which do not use SUS_STAT# as an indicator of clock validity, ensure that the PWRDWN# pin of the CK-408-compatible clock generator is not deasserted during S3 entry for a long enough duration such that the system clocks can restart.
10.2.3.
SLP_S3#
When asserted SLP_S3# indicates that the system is in the S3 power state. If systems have problem with clocks being turned on during S1M to S3 transition, the designer can use following recommendation. SLP_S3# pin be connected to clock generator PWRDWN# in combination with the SLP_S1# signal to shut off the system clocks in S3 and during S1M to S3 transition.
Design Guide 145
Figure 77. PWRDWN# to CK-408

V3.3S
SLP_S1# PWRDWN# (CK-408) SLP_S3#
NOTES: 1. CK-408 Minimum power up latency should be 100 S to guarantee functionality of AND logic. In systems that incorporate any peripherals which are not reset during S3 and which do not use SUS_STAT# as an indicator of clock validity, ensure that the PWRDWN# pin of the CK-408-compatible clock generator is not deasserted during S3 entry for a long enough duration such that the system clocks can restart. 2. If platform does not support S1M state, designer may connect SLP_S3 to PWRDWN# pin of CK-408.
10.3.
10.3.1.
Clock Group Topology and Layout Routing Guidelines

HOST_CLK Clock Group
The clock synthesizer provides four sets of 100-MHz differential clock outputs. The 100-MHz differential clocks are driven to the Processor the Intel 845MP/845MZ and the processor debug port as shown in figure below. The clock driver differential bus output structure is a Current Mode Current Steering output which develops a clock signal by alternately steering a programmable constant current to the external termination resistors Rt. The resulting amplitude is determined by multiplying IOUT by the value of Rt. The current IOUT is programmable by a resistor and an internal multiplication factor so the amplitude of the clock signal can be adjusted for different values of Rt to match impedances or to accommodate future load requirements.
Note:
Designer should use one or the other topologies for CPU, MCH-M, and ITP. Make sure to route all clocks pairs in the same fashion (layer, layer transition, same number of via).
10.3.1.1.
End Of Line Termination Topology

The recommended termination for the differential bus clock is a End of Line Termination. Refer to Figure 78 for an illustration of this terminology scheme. Parallel Rt 55- resistors perform a dual function, converting the current output of the clock driver to a voltage and matching the driver output impedance to the transmission line. The series resistors Rs provide isolation from the clock drivers output parasitic, which would otherwise appear in parallel with the termination resistor Rt. The value of Rt should be selected to match the characteristic impedance of the system board and Rs should be between 20 and 33 Ohms. Simulations have shown that Rs values above 33 Ohms provide no benefit to signal integrity but only degrade the edge rate.
Mult0 pin (pin #43) connected to HIGH making the multiplication factor as 6.
146
Design Guide
Iref pin (pin # 42) is connected to ground through a 475-Ohm (1 % tol.) resistor making the Iref as 2.32 mA.
Figure 78. End of Line Termination Topology

RS L1 L2
L1' RS
L2'
Clock Driver
L3 L3' RT
CPU or MCH-M
RT
Design Guide
147
Table 49. End of Line Termination Topology BCLK [1:0]# Routing Guidelines
Layout Guideline Value Illustration Notes
BCLK Skew between agents
400 ps totalBudget:150 ps for Clock driver250 ps for interconnect S max. 4 S- 5 S mils 4.0 mils 100 15% 55 15% 0.5 max Figure 80 Figure 80 Figure 80 --Figure 79
1, 2, 3, 4
Differential pair spacing Spacing to other traces Line width Systemboard Impedance Differential Systemboard Impedance odd mode Processor routing length L1, L1': Clock driver to Rs Processor routing length L2, L2' Processor routing length L3, L3: RS-RT node to Rt Processor routing length L4, L4': RS-RT Node to Load MCH-M routing length L1, L1: Clock Driver to RS MCH-M routing length L2, L2' MCH-M routing length L3, L3: RS-RT node to Rt Clock driver to Processor and clock driver to Chipset length matching (L1+L2) BCLK0 BCLK1 length matching Rs Series termination value Rt Shunt termination value
5, 6 -7 8 9 13
0 0.2" 0 - 0.5" 2 8" 0.5 max 2 8" 0 0.2" +260 mils -190 mils 10 mils 33 5% 55 1% (for 55 MB impedance)
Figure 79 Figure 79 Figure 79 Figure 79 Figure 79 Figure 79 Figure 79
13 13
13 13 13 10
-11 12
10.3.1.2.
Source Shunt Termination Topology

The recommended termination for the differential bus clock is a Source Shunt Termination. Refer to Figure 79 for an illustration of this terminology scheme. Parallel Rt 49.9 resistors perform a dual function, converting the current output of the clock driver to a voltage and matching the driver output impedance to the transmission line. The series resistors Rs provide isolation from the clock drivers output parasitic, which would otherwise appear in parallel with the termination resistor Rt. The value of Rt should be selected to match the characteristic impedance of the system board and Rs should be between 20 and 33 Ohms. Simulations have shown that Rs values above 33 ohms provide no benefit to signal integrity but only degrade the edge rate.
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Design Guide
Mult0 pin (pin #43) connected to HIGH making the multiplication factor as 6. Iref pin (pin # 42) is connected to ground through a 475-Ohm ( 1 % tol.) resistor making the Iref as 2.32 mA.
Figure 79. Source Shunt Termination Topology

L1 RS L2 L4
L1' Clock Driver RS
L2'
L4' CPU or MCH-M
L3'
L3 RT
RT
Table 50. Source Shunt Termination Topology BCLK [1:0]# Routing Guidelines
Layout Guideline Value Illustration Notes
BCLK Skew between agents
400 ps totalBudget:150 ps for Clock driver250 ps for interconnect S max. 4 S- 5 S mils 4.0 mils 100 15% 55 15% 0.5 max Figure 80 Figure 80 Figure 80 --Figure 79
1, 2, 3, 4
Differential pair spacing Spacing to other traces Line width Systemboard Impedance Differential Systemboard Impedance odd mode Processor routing length L1, L1': Clock driver to Rs Processor routing length L2, L2' Processor routing length L3, L3: RS-RT node to Rt Processor routing length L4, L4': RS-RT Node to Load MCH-M routing length L1, L1: Clock Driver to RS MCH-M routing length L2, L2' MCH-M routing length L3, L3: RSRT node to Rt MCH-M routing length L4, L4': RSRT Node to Load Clock driver to Processor and clock di t Chi tl th t hi
5, 6 -7 8 9 13
0 0.2" 0 - 0.5" 2 8"
Figure 79 Figure 79 Figure 79
13 13
0.5 max 0 0.2" 0 0.2" 2 8" +260 mils
Figure 79 Figure 79 Figure 79 Figure 79 Figure 79
13 13 13
10
Design Guide
149
Layout Guideline
Value
Illustration
Notes
driver to Chipset length matching (L1+L2+L4) BCLK0 BCLK1 length matching Rs Series termination value Rt Shunt termination value
-190 mils 10 mils 33 5% 55 1% (for 55 MB impedance) -11 12
NOTES: 1. This number does not include clock driver common m. 2. The skew budget includes clock driver output pair to output pair jitter (differential jitter), and skew, clock skew due to interconnect process variation, and static skew due to layout differences between clocks to all bus agents. 3. The interconnect portion of the total budget for this specification assumes clock pairs are routed on multiple routing layers and routed no longer than the maximum recommended lengths. 4. Skew measured at the load between any two bus agents. Measured at the crossing point. 5. Edge to edge spacing between the two traces of any differential pair. Uniform spacing should be maintained along the entire length of the trace. 6. Clock traces are routed in a differential configuration. Maintain the minimum recommended spacing between the two traces of the pair. Do not exceed the maximum trace spacing, as this will degrade the noise rejection of the network. 7. Set line width to meet correct systemboard impedance. The line width value provided here is a recommendation to meet the proper trace impedance based on the recommended stackup. 8. The differential impedance of each clock pair is approximately 2*Zsingle-ended*(1-2*Kb) where Kb is the backwards cross-talk coefficient. For the recommended trace spacing, Kb is very small and the effective differential impedance is approximately equal to 2 times the single-ended impedance of each half of the pair. 9. The single ended impedance of both halves of a differential pair should be targeted to be of equal value. They should have the same physical construction. If the BCLK traces vary within the tolerances specified, both traces of a differential pair must vary equally. 10. Length compensation for the processor socket and package delay is added to chipset routing to match electrical lengths between the chipset and the processor from the die pad of each. Therefore, the systemboard trace length for the chipset will be longer than that for the processor. Details of this additional length will be included in a future revision of the processor package files. 11. Rs values between 20 33 have been shown to be effective. 12. Rt shunt termination value should match the systemboard impedance. 13. Minimize L1, L2 and L3 lengths. Long lengths on L2 and L3 degrade effectiveness of source termination and contribute to ring back. 14. The goal of constraining all bus clocks to one physical routing layer is to minimize the impact on skew due to variations in Er and the impedance variations due to physical tolerances of circuit board material.
BCLK General Routing Guidelines: 1. When routing the 100-MHz differential clocks do not split up the two halves of a differential clock pair between layers and route to all agents on the same physical routing layer referenced to ground. 2. If a layer transition is required, make sure that the skew induced by the vias used to transition between routing layers is compensated in the traces to other agents. 3. Do not place Vias between adjacent complementary clock traces, and avoid differential Vias. Vias placed in one half of a differential pair must be matched by a via in the other half. Differential Vias can be placed within length L1, between clock driver and RS, if needed to shorten length L1. EMI constraints:
Clocks are a significant contributor to EMI and should be treated with care. Following recommendations can aid in EMI reduction: Maintain uniform spacing between the two halves of differential clocks
Route clocks on physical layer adjacent to the VSS reference plane only
150
Design Guide
Figure 80. Clock Skew as Measured from Agent to Agent
Figure 81. Trace Spacing
10.3.2.
CLK66 Clock Group

The driver is the clock synthesizer 66-MHz clock output buffer and the receiver is the 66- MHz clock input buffer at the MCH-M and the Intel ICH3-M. Note that the goal is to have as little skew between the clocks within this group.
Design Guide
151
Figure 82. Topology for CLK66
R1
A B
Clock Driver
Table 51. CLK66 Routing Guidelines
Parameter Routing Guidelines
MCH and ICH2
Clock Group Topology Reference Plane Characteristic Trace Impedance (Zo) Trace Width Trace Spacing Spacing to other traces Trace Length A Trace Length B Resistor Skew Requirements Clock Driver to MCH-M Clock Driver to ICH
CLK66 Point to point Ground Referenced (Contiguous over entire Length) 55 Ohms 15% 4 mils 20 mils 20 mils 0.00 to 0.50 4.00 to 8.50 R1 = 33 Ohms +/- 1% All the clocks in the CLK66 group should have minimal skew (~ 0) between each other with tolerance of 500 pS X X 100 mils
If the trace length from the clock driver to the MCH-M is X, the trace length from clock to ICH must be X 100 mils.
10.3.3.
AGPCLK Clock Group

The driver is the clock synthesizer 66-MHz clock output buffer and the receiver is the 66-MHz clock input buffer at the AGP device. Note that the goal is to have minimal (~ 0) skew between this clock and the clocks in the clock group CLK66.
152
Design Guide
Figure 83. Topology for AGPCLK to AGP Connector
R1
A B C Trace on AGP Card
Clock Driver
AGP Connector
AGP Device
Figure 84. Topology for AGPCLK to AGP Device Down
R1
A B
Clock Driver
AGP Device
Table 52. AGPCLK Routing Guidelines

Clock Group Topology Reference Plane Characteristic Trace Impedance (Zo) Trace Width Trace Spacing Spacing to other traces Trace Length A Trace Length B Trace Length C Resistor Skew Requirements
AGPCLK Point to point Ground Referenced (Contiguous over entire Length) 55 Ohms 15% 4 mils 20 mils 20 mils 0.00 to 0.50 (CLK66 Trace B) 4 Routed 4 per the AGP Specification R1 = 33 Ohms 1% Should have minimal (~ 0) skew between the AGPCLK and the clocks in the CLK66 clock group.
Design Guide
153
10.3.4.
CLK33 Clock Group

The driver is the clock synthesizer 33-MHz clock output buffer and the receiver is the 33-MHz clock input buffer at the Intel ICH3-M, FWH, Glue Chip, and SIO. Note that the goal is to have minimal (~ 0) skew between the clocks within this group, and also minimal (~ 0) skew between the clocks of this group and that of group CLK66.
R1
A B
Clock Driver
ICH2, SIO, Glue Chip, FWH

Clock Group Topology Reference Plane Characteristic Trace Impedance (Zo) Trace Width Trace Spacing Spacing to other traces Trace Length A
CLK33 Point to point Ground Referenced (Contiguous over entire Length) 55 Ohms 15% 4 mils 20 mils 20 mils Same as CLK66 Trace A This trace must be exactly length matched to CLK66 Trace A
Trace Length B
Same as CLK66 Trace B This trace must be exactly length matched to CLK66 Trace B
Resistor Skew Requirements
R1 = 33 ohms 1% Should have minimal (~ 0) skew between the clocks within this group, and also minimal (~ 0) skew between the clocks of this group and that of group CLK66.
10.3.5.
CLK14 Clock Group

The driver is the clock synthesizer 14.318-MHz clock output buffer and the receiver is the 14.318-MHz clock input buffer at the ICH3-M and SIO. Note that the clocks within this group should have minimal skew (~ 0) between each other, however each of the clocks in this group are asynchronous to clocks of any other group.
154
Design Guide
R1
A B
Clock Driver
ICH3 and SIO

Clock Group Topology Reference Plane Characteristic Trace Impedance (Zo) Trace Width Trace Spacing Spacing to other traces Trace Length A Trace Length B Resistor Skew Requirements
CLK14 Point to point Ground Referenced (Contiguous over entire Length) 60 Ohms 15% 5 mils 10 mils 10 mils 0.00 to 0.50 4.00 to 8.50 R1 = 33 Ohms 1% Should have minimal skew (~ 0) between each other, however each of the clocks in this group is asynchronous to clocks of any other group.
Design Guide
155
10.3.6.
PCICLK Clock Group

The driver is the clock synthesizer 33-MHz clock output buffer and the receiver is the 33-MHz clock input buffer at the PCI devices on the PCI cards. Note that the goal is to have a maximum of 1 ns skew between the clocks within this group, and also a maximum of 1 ns skew between the clocks of this group and that of group CLK33.
Figure 87. Topology for PCICLK to PCI Device Down
R1
A B
Clock Driver
PCI Device
Table 55. PCICLK Routing Guidelines

PCICLK Point to point Ground Referenced (Contiguous over entire Length) 60 Ohms 15% 5 mils 20 mils 20 mils Same as CLK33 Trace A This trace must be exactly length matched to CLK33 Trace A
Trace Length B
Same as CLK33 Trace B This trace must be exactly length matched to CLK33 Trace B
Resistor Skew Requirements
R1 = 33 Ohms 1% Should have a maximum of 1 ns skew between the clocks within this group, and also a maximum of 1 ns skew between the clocks of this group and that of group CLK33.
156
Design Guide
Figure 88. Topology for PCICLK to PCI Slot
R1
A B C Trace on PCI Card
Clock Driver
PCI Connector
PCI Device
Table 56. PCICLK Routing Guidelines

PCICLK Point to point Ground Referenced (Contiguous over entire Length) 50 Ohms 15% 5 mils 10 mils 10 mils Same as CLK33 Trace A This trace must be exactly length matched to CLK33 Trace A
Trace Length B Trace Length C Resistor Skew Requirements
(Routed equal to CLK33 Trace B) 2.5 Routed 2.50 per the PCI Specification R1 = 33 Ohms 1% Should have a maximum of 1 ns skew between the clocks within this group, and also a maximum of 1 ns skew between the clocks of this group and that of group CLK33. 1
Maximum via Count per signal
Design Guide
157
10.3.7.
USBCLK Clock Group

The driver is the clock synthesizer USB clock output buffer and the receiver is the USB clock input buffer at the Intel ICH3-M. Note that this clock is asynchronous to any other clock on the board.
Figure 89. Topology for USB_CLOCK
R1
A B
Clock Driver
ICH2
Table 57. USBCLK Routing Guidelines

Clock Group Topology Reference Plane Characteristic Trace Impedance (Zo) Trace Width Trace Spacing Spacing to other traces Trace Length A Trace Length B Resistor Skew Requirements Maximum via Count per signal
USBCLK Point to point Ground Referenced (Contiguous over entire Length) 50 Ohms 15% 5 mils 20 mils 0.00 0.50 3.00 12.00 R1 = 33 Ohms 1% None USBCLK is asynchronous to any other clock on the board 2
158
Design Guide
11.
11.1.
Platform Power Guidelines

Definitions
Suspend-To-RAM (STR):
In the STR state, the system state is stored in main memory and all unnecessary systemlogic is turned off. Only main memory and logic required to wake the system remain powered.
Full-power operation:
During full-power operation, all components on the motherboard remain powered. Note that full-power operation includes both the full-on operating state and the S1 (PROCESSOR stop-grant state) state.
Suspend operation:
During suspend operation, power is removed from some components on the motherboard. The customer reference board supports two suspend states: Suspend-to-RAM (S3) and Soft-off (S5).
Core power rail:
A power rail that is only on during full-power operation. These power rails are on when the PSON signal is asserted to the ATX power supply.
Standby power rail:
A power rail that in on during suspend operation (these rails are also on during full-power operation). These rails are on at all times (when the power supply is plugged into AC power). The only standby power rail that is distributed directly from the ATX power supply is: 5 VSB (5 V Standby). There are other standby rails that are created with voltage regulators on the motherboard.
Derived power rail:
A derived power rail is any power rail that is generated from another power rail using an on-board voltage regulator. For example, 3.3 VSB is usually derived (on the motherboard) from 5VSB using a voltage regulator.
Dual power rail:
A dual power rail is derived from different rails at different times (depending on the power state of the system). Usually, a dual power rail is derived from a standby supply during suspend operation and derived from a core supply during full-power operation. Note that the voltage on a dual power rail may be misleading.
Design Guide
159
11.2.
11.2.1.
Platform Power Requirements

Platform Power Delivery Architectural Block Diagram
Figure 90. Platform Power Delivery Block Diagram

Mobile Processor
VCC_CORE = IMVP-III VCC_VID = 1.2V
System Bus 400 MT/S
DDR200 X 2 Or DDR266 X 2
PC1600/ 2100
+V2.5 +V1.25
AGP
+V1.5S +V3.3S +V5S +V12S
AGP4X(1.5V) 1.06GB/s
MCH-M
VTT = VCC_CORE +V1.5S +V1.8S +V2.5 +V1.25
8-Bit Hub Interface 266MB/s
USB
+V3.3 +V5
ICH3-M
CPUIO = VCC_CORE +VCC_LAN1.8 +VCC_SUS1.8 +VCC1.8 +V3.3Always +VCC3.3 +VCC_LAN3.3 VCC_RTC V5RefSUS, V5Ref
FWH
+V3.3S
ATA 66/100 IDE

+V3.3S +V5S
PCI Bus
Moon2
+V5S
AC97
+V3.3 +V3.3Always +V5
CardBus
+V3.3
LAN
+V3.3
SMC
+V3.3Always
SIO
+V3.3S
KBC
+V3.3Always
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Design Guide
11.3.
11.3.1.
Voltage Supply
Power Management States
SIGNAL STATE SLP_S1# SLP_S3# SLP_S5# +V*ALW +V* +V*S CLOCKS
Table 58. Power Management States
FULL ON S1 (Power on Suspend) S3 (Suspend to RAM) S4 (Suspend to Disk) S5 (Soft Off)
HIGH LOW LOW LOW LOW
HIGH HIGH LOW LOW LOW
HIGH HIGH HIGH LOW LOW
ON ON ON ON ON
ON ON ON OFF OFF
ON ON OFF OFF OFF
ON LOW LOW OFF OFF
11.3.2.
Power Supply Rail Descriptions

Signal Names Voltage (V) Current (A)* Tolerance Enable Description
Table 59. Power Supply Rail Descriptions (* Currents are Estimates Only)
+V1_25
1.25
2.0
+ 2% DC
SLP_S5# HIGH
845MP/845MZ MCH-M DDR Reference & Termination. SLP_S5# for VTT is ON, SLP_S3# for VTT OFF 845MP/845MZ MCH-M Core & AGP, AGP VDDQ ICH3-M ICH3-M ICH3-M, 845MP/845MZ MCH-M 845MP/845MZ MCH-M DDR I/O, DDR SO-DIMM ICH3-M, SMC/KBC, AC97 ICH3-M, Cardbus, AC97, RS232 ICH3-M, CK-408, AGP Core, DDR SO-DIMM, FWH, SIO, AC97 USB, AC97, HDD,+V2_5, AGP, +V1_25, DVD/CDROM, ICH3-M, AGP I/O, MSE/KBD, FDD, HDD, DV/CDROM AGP, Cardbus See IMVP-III Mobile Processor Core Voltage Regulator Specification Design Guide for details. Reference voltage for processor PLL d VID i it
+V1_5S +V1_8ALWAYS +V1_8 +V1_8S +V2_5 +V3ALWAYS +V3 +V3S +V5 +V5S +V12S +VCC_CORE
1.5 1.8 1.8 1.8 2.5 3.3 3.3 3.3 5.0 5.0 12.0 IMVP-III
3.5 0.21 0.5 0.8 6.1 0.4 0.9 7.0 9.0 1.0 0.2 40.0
+ 5% + 5% + 5% + 5% + 5% + 5% + 5% + 5% + 5% + 5% + 5% IMVP-III
SLP_S3# HIGH +VDC ON SLP_S5# HIGH SLP_S3# HIGH SLP_S5# HIGH +VDC ON SLP_S5# HIGH SLP_S3# HIGH SLP_S5# HIGH SLP_S3# HIGH SLP_S3# HIGH +VCC_VID HIGH
+VCC_VID
1.2
0.300
+ 5% DC
VR_ON
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Signal Names
Voltage (V)
Current (A)*
Tolerance
Enable
Description
+ 9% AC
PLL and VID circuitry.
11.3.3.
11.3.3.1.
Power Supply Control Signals

SLP_S3#
SLP_S3# is a signal coming from the ICH3-M. Deassertion of SLP_S3# enables the outputs for the following rails: +V1.25, +V1_5S, +V1_8S, +V3_3S, +V5S, and +V12S. SLP_S3# will be asserted when the system enters S3/S4/S5 or powers off. SLP_S3# is deasserted when the system boots up or exits from S3, S4, and S5.
11.3.3.2.
SLP_S5#
SLP_S5# is a signal coming from the ICH3-M. Deassertion of SLP_S5# enables the outputs for the following rails: +V1_8, +V2_5, +V3_3, and +V5. SLP_S5# will be asserted when the system enters S4/S5 or powers off. SLP_S5# is deasserted when the system boots up or exits from S4 and S5.
11.4.
11.4.1.
11.4.1.1.
Platform Power Sequencing Requirements

Processor Power Sequencing
Core Converter Soft Start Timer
Refer to 4.4.2.2.
11.4.2.
11.4.2.1.
ICH3-M Power Sequencing

1.8 V/3.3 V Sequencing
The ICH3-M has three pairs of associated 1.8-V and 3.3-V supplies. These are +V1.8ALWAYS & +V3ALWAYS, +V1.8 & +V3, and +V1.8S & +V3S. These pairs are assumed to power up and power down together. The difference between the two associated supplies must never be greater than 2.0 V. The 1.8-V supply may come up before the 3.3 V supply without violating this rule. One serious consequence of violation of this "2 V Rule" is electrical overstress of oxide layers, resulting in component damage. The majority of the ICH3-M I/O buffers are driven by the 3.3-V supplies, but are controlled by logic that is powered by the 1.8-V supplies. Thus, another consequence of faulty power sequencing arises if the 3.3-V supply comes up first. In this case, the I/O buffers will be in an undefined state until the 1.8-V logic is powered up. Some signals that are defined as "Input-only" actually have output buffers that are normally disabled, and the ICH3-M may unexpectedly drive these signals if the 3.3-V supply is active while the 1.8-V supply is not. Figure 91 is an example power-on sequencing circuit that ensures the 2 V Rule is obeyed. This circuit uses a NPN (Q2) and PNP (Q1) transistor to ensure the 1.8-V supply tracks the 3.3-V supply. The NPN transistor controls the current through PNP from the 3.3 V supply into the 1.8 V power plane by varying
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Design Guide
the voltage at the base of the PNP transistor. By connecting the emitter of the NPN transistor to the 1.8 V plane, current will not flow from the 3.3-V supply into 1.8-V plane when the 1.8-V plane reaches 1.8 V.
Figure 91. Example 1.8-V/3.3-V Power Sequencing Circuit
+3.3V +1.8V
220 220 Q2 NPN Q1 PNP
470
When analyzing systems that may be "marginally compliant" to the 2 V Rule, please pay close attention to the behavior of the ICH3-M's RSMRST#, PWROK, and LAN_RST# in ICH3-M signals, since these signals control internal isolation logic between the various power planes:
RSMRST# controls isolation between the RTC well and the Resume wells PWROK controls isolation between the Resume wells and Main wells LAN_RST# controls isolation between the LAN wells and the Resume wells (applies only to ICH3M)
If one of these signals goes high while one of its associated power planes is active and the other is not, a leakage path will exist between the active and inactive power wells. This could result in high, possibly damaging, internal currents.
11.4.2.2.
3.3-V/V5REF and 3.3SUS/V5REF_SUS Sequencing

V5REF is the reference voltage for 5-V tolerance on inputs to the ICH3-M. V5REF must be powered up before VCC3_3, or after VCC3_3 within 0.7V. Also, V5REF must power down after VCC3_3, or before VCC3_3 within 0.7 V. The rule must be followed in order to ensure the safety of the ICH3-M. If the rule is violated, internal diodes will attempt to draw power sufficient to damage the diodes from the VCC3_3 rail. Figure 92 shows a sample implementation of how to satisfy the V5REF/3.3V sequencing rule. This rule also applies to the standby rails, but in most platforms, the VCCSUS3_3 rail is derived from the VCCSUS5 rail and therefore, the VCCSUS3_3 rail will always come up after the VCCSUS5 rail. As a result, V5REF_SUS will always be powered up before VCCSUS3_3. In platforms that do not derive the VCCSUS3_3 rail from the VCCSUS5 rail, this rule must be comprehended in the platform design.
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Figure 92. Example 3.3-V/V5REF Sequencing Circuitry

V C C S u p p ly (3 .3 V ) 5 V S u p p ly
1 K
1 u F
T o S y s te m
V R E F
T o S y s te m
In compliance with USB 2.0 specification requirements for continuous short conditions, V5REF_Sus pins must be connected to 5 V. 5VREF_Sus affects 5-V tolerance for all USB signals, both over-current and data pins. USB 2.0 specification requires that USB controller to withstand a continuous short between the USB 5-V connector supply to a USB signal at the connector for 24 hours. Figure 93 and Figure 94 provide options for connecting V5REF_Sus to 5 volts on mobile platforms. Figure 93 is for platforms that support +V5_Always (5 V always ON). Figure 94 represents a connection to V5REF_Sus for platforms that do not support +V5_Always.
Figure 93. V5REF_Sus Option 1: +V5_Always Available in Platform
+V5_Always
V5Ref_Sus1 V5Ref_Sus2
0.1uF
Customer specific or Intel recommended USB power circuit USB Power (5V)
ICH3-M
USB D+ USB D-
Customer specific or Intel recommended USB interface circuits GND
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Design Guide
Figure 94. V5REF_Sus Option 1: +V5_Always Not Available in Platform
+V5 or +V5S Customer specific or Intel recommended USB power circuit

D2*
+3.3V_Always
D1*
V5Ref_Sus1 V5Ref_Sus2
0.1uF
USB Power (5V)
ICH3-M
USB D+ USB D-
Customer specific or Intel recommended USB interface circuits GND
D1 and D2 are BAT54 or Equivalent Schottky Diode
11.4.3.
MCH-M Power Sequencing Requirements

There are no MCH-M power sequencing requirements. All MCH-M power rails should be stable before deasserting reset, but the power rails can be brought up in any order desired. Good design practice would have all MCH-M power rails come up as close in time as practical, with the core voltage (1.5 V) coming up first.
11.4.4.
DDR Power Sequencing Requirements

No DDR-SDRAM power sequencing requirements are specified during power up or power down if the following criteria are met:
VDD and VDDQ are driven from a single power converter output. VTT is limited to 1.44 V (reflecting VDDQ(max)/2 + 50 mV VREF variation + 40 mV VTT variation) VREF tracks VDDQ/2 A minimum resistance of 42 Ohm (22 Ohm series resistor + 22 Ohm parallel resistor -5% tolerance) limits the input current from the VTT supply into any pin.
If the above criteria cannot be met by the system design, then the following table must be adhered to during power up:
Table 60. Power-up Initialization Sequence (Should Above Listed Requirements Not be Met)
Voltage Description Sequencing Voltage Relationship to Avoid Latch-up
VDDQ VTT VREF
After or with VDD After or with VDDQ After or with VDDQ
< VDD + 0.3 V < VDDQ + 0.3 V < VDDQ + 0.3 V
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11.5.
Decoupling Recommendations
Intel recommends proper design and layout of the system board bulk and high frequency decoupling capacitor solution to meet the transient tolerances for each component. To meet the component transient load steps, it is necessary to properly place bulk and high frequency capacitors close to the component power and ground pins.
11.5.1.
Transient Response
The inductance of the motherboard power planes slows the voltage regulators ability to respond quickly to a current transient. Decoupling a power plane can be broken into several independent parts. The closer to the load the capacitor is placed the more stray inductance is bypassed. By bypassing the inductance of leads, power planes, etc., less capacitance is required. However, areas closer to the load have less room for capacitor placement. Therefore tradeoffs must be made. It is the responsibility of the system designer to provide adequate high frequency decoupling to manage the highest frequency components of the current transients. Larger bulk storage capacitors supply current during longer lasting changes in current demand. High Frequency decoupling is typically done with ceramic capacitors with a very low ESR. Because of there low ESR, these capacitors can act very quickly to supply current at the beginning of a transient event. However, because the ceramic capacitors are small, i.e. they can only store a small amount of charge, Bulk capacitors are needed too. Bulk capacitors are typically polarized with high capacitance values and unfortunately higher ESRs. The higher ESR of the Bulk capacitor limits how quickly it can respond to a transient event. The Bulk and HF capacitors working together can supply the charge needed to stay in regulator before the regulator can react during a transient. The bulk capacitors and the high frequency capacitors should be placed as close to the load as possible and in the path of current flow. Power must be distributed as a plane. This plane can be constructed as an island on a layer used for other signals, on a supply plane with other power islands, or as a dedicated layer of the PCB. Power should never be distributed by traces alone. Intel recommends that all layers of the stack-up be used for power and ground routing.
11.5.2.
Processor Decoupling Recommendations

See Processor Power Delivery Design Recommendations.
11.5.3.
11.5.3.1.
ICH3-M Decoupling Recommendations

1.8-V Power Supply Rails
Seven 0.1 F, 0603, X7R capacitors and one 22.0 F, X5R capacitors should be placed between the VCCPHL and VCCCORE supply pins and the VSS ground pins. Place the all capacitors as close to the ICH3-M package as possible, but ensure the 0603 capacitors are the closest to the package. Connections should be done to minimize loop area and loop inductance of these capacitors. Eight 0.1 F, 0603, X7R capacitors and one 22.0 F, X5R capacitors should be placed between the VCCPUSB and the VCCPSUS supply pins and the VSS ground pins. Place the all capacitors as close to the ICH3-M package as possible, but ensure the 0603 capacitors are the closest to the package. Connections should be done to minimize loop area and loop inductance of these capacitors.
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Design Guide
Two 0.1 F, 0603, X7R capacitors and one 4.7 F, X5R capacitors should be placed between the VCCPAUX supply pins and the VSS ground pins. Place the all capacitors as close to the ICH3-M package as possible, but ensure the 0603 capacitors are the closest to the package. Connections should be done to minimize loop area and loop inductance of these capacitors.
11.5.3.2.
3.3-V Power Supply Rails

Twelve 0.1 F, 0603, X7R capacitors and one 22.0 F, X5R capacitors should be placed between the VCCPPCI supply pins and the VSS ground pins. Place the all capacitors as close to the ICH3-M package as possible, but ensure the 0603 capacitors are the closest to the package. Connections should be done to minimize loop area and loop inductance of these capacitors. Three 0.1 F, 0603, X7R capacitors and one 10.0 F, X5R capacitors should be placed between the VCCSUS supply pins and the VSS ground pins. Place the all capacitors as close to the ICH3-M package as possible, but ensure the 0603 capacitors are the closest to the package. Connections should be done to minimize loop area and loop inductance of these capacitors. Two 0.1 F, 0603, X7R capacitors and one 22 F, X5R capacitors should be placed between the VCCAUX supply pins and the VSS ground pins. Place the all capacitors as close to the ICH3-M package as possible, but ensure the 0603 capacitors are the closest to the package. Connections should be done to minimize loop area and loop inductance of these capacitors.
11.5.4.
11.5.4.1.
MCH-M Decoupling Recommendations

VCC_CORE, VTT Processor System Bus, VTT
Ten 0.1 F, 0603, X7R capacitors and three 10.0 F, 1206, X5R capacitors should be placed between the VTTFSB supply pins and the VSS ground pins. Place the all capacitors as close to the MCH-M package as possible, but ensure the 0603 capacitors are the closest to the package. Connections should be done to minimize loop area and loop inductance of these capacitors.
11.5.4.2.
1.5-V AGP/CORE
Six 0.1 F, 0603, X7R capacitors and two 10.0 F, 1206, X5R capacitors should be placed between the VCCAGP/VCCCORE supply pins and the VSS ground pins. Place the all capacitors as close to the MCH-M package as possible, but ensure the 0603 capacitors are the closest to the package. Connections should be done to minimize loop area and loop inductance of these capacitors.
11.5.4.3.
1.8-V Hub Interface

Three 0.1 F, 0603, X7R capacitors and one 10.0 F, 1206, X5R capacitors should be placed between the VCCHL supply pins and the VSS ground pins. Place the all capacitors as close to the MCH-M package as possible, but ensure the 0603 capacitors are the closest to the package. Connections should be done to minimize loop area and loop inductance of these capacitors.
11.5.5.
2.5-V MCH-M System Memory High Frequency Decoupling

Every MCH-M ground and power ball in the system memory interface should have its own via. For 2.5V high frequency decoupling, a minimum of six 0603 0.1-F high frequency capacitors is required, and must be within 150 mils of the MCH-M package. The six capacitors should be evenly distributed along
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the MCH-M DDR system memory interface and must be placed perpendicular to the MCH-M with the power (2.5 V) side of the capacitors facing the MCH-M. The trace from the power end of the capacitor should be as wide as possible and it must connect to a 2.5-V power ball on the outer row of balls on the MCH-M. Each capacitor should have their 2.5-V via placed directly over and connected to a separate 2.5 V copper finger, and they should be as close to the capacitor pad as possible, within 25 mils. The ground end of the capacitors must connect to the ground flood and to the ground plane through a via. This via should be as close to the capacitor pad as possible, within 25mils with as thick a trace as possible.
11.5.6.
2.5-V MCH-M System Memory Low Frequency Bulk Decoupling

The MCH-M system memory interface requires low frequency bulk decoupling. Place two 100-F electrolytic capacitors between the MCH-M and the first SO-DIMM connector. The power end of the capacitors must connect to 2.5 V, and the ground end of the capacitors must connect to ground. Also, the output of the 2.5-V regulator must have enough bulk decoupling to ensure the stability of this regulator. The amount of bulk decoupling required at the output of the 2.5 V regulator will vary according to the needs of different OEM design targets.
11.5.7.
2.5-V SO-DIMM System Memory High Frequency Decoupling

Discontinuities in the DDR signal return paths will occur when the signals transition between the motherboard and the SO-DIMMs. To account for this ground to 2.5 V discontinuity, a minimum of nine 0603 0.1 uF high-frequency bypass capacitors are required between the SO-DIMMs to help minimize any anticipated return path discontinuities that will be created. The bypass capacitors should connect to 2.5 V and ground. The ground trace should connect to a via that transitions to the ground flood and to the ground plane. The ground via should be placed as close to the ground pad as possible. The 2.5-V trace should connect to a via that transitions to the 2.5 V copper flood and to the 2.5-V plane. It should connect to the closet 2.5-V SO-DIMM pin on either the first or second SO-DIMM connector, with a wide trace. The capacitors 2.5 V traces should be distributed as evenly as possible amongst the two SODIMMs.
11.5.8.
2.5-V SO-DIMM System Memory Low Frequency Decoupling

The DDR SO-DIMMs require low frequency bulk decoupling. Place a total of four 100-F capacitors, one at each corner of each SO-DIMM connector. The power end of the capacitors must connect to a 2.5V plane, and the ground end of the capacitors must connect to ground plane. The output of the 2.5-V regulator must have enough bulk decoupling to ensure the stability of the regulator. The amount of bulk decoupling required at the output of the 2.5-V regulator will vary according to the needs of different OEM design targets.
11.5.9.
1.25-V DDR VTT High Frequency Decoupling Requirements

The VTT Island must be decoupled using high-speed bypass capacitors, one 0603 0.1-F capacitor per two DDR signals. These decoupling capacitors connect directly to the VTT Island and to ground, and must be spread-out across the termination Island so that all the parallel termination resistors are near high-frequency capacitors. The capacitor ground via should be as close to the capacitor pad as possible, within 25 mils with as thick a trace as possible. The ground end of the capacitors must connect to the ground flood on layer two and to the ground plane on layer three through a via. Finally, the distance from any DDR termination resistor pin to a VTT capacitor pin must not exceed more then 100 mils.
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Design Guide
11.5.10. 1.25-V DDR VTT Low Frequency Bulk Decoupling Requirements

The VTT Termination Island requires low frequency bulk decoupling. Place one 220-F electrolytic capacitor at each end of the termination island. The power end of the capacitors must connect to the Vtt termination island directly, and the ground end of the capacitors must connect to ground. Also, the output of the 1.25-V regulator must have enough bulk decoupling to ensure the stability of the regulator. The amount of bulk decoupling required at the output of the 1.25-V regulator will vary according to the needs of different OEM design targets.
11.5.11. 1.5-V AGP Decoupling

The following routing guidelines are recommended for the optimal system design. The main focus of these guidelines is to minimize signal integrity problems on the AGP interface of the Intel 845MP/845MZ chipset (MCH-M). The following guidelines are not intended to replace thorough system validation on Intel 845MP/845MZ chipset-based products.
A minimum of six 0.01-F capacitors are required and must be as close as possible to the MCH-M. These should be placed within 70 mils of the outer row of balls on the MCH-M for VDDQ decoupling. The closer the placement, the better. The designer should evenly distribute placement of decoupling capacitors in the AGP interface signal field. Intel recommends that the designer use a low-ESL ceramic capacitor, such as with a 0603 body-type X7R dielectric. In order to add the decoupling capacitors within 70 mils of the MCH-M and/or close to the vias, the trace spacing may be reduced as the traces go around each capacitor. The narrowing of space between traces should be minimal and for as short a distance as possible (1-inch max.). In addition to the minimum decoupling capacitors, the designer should place bypass capacitors at vias that transition the AGP signal from one reference signal plane to another. One extra 0.01-F capacitor is required per 10 vias. The capacitor should be placed as close as possible to the center of the via field.
11.5.12. 1.8-V Hub Interface Decoupling

To improve I/O power delivery, use two 0.1-F capacitors per each component (i.e. the ICH3-M and MCH-M). These capacitors should be placed within 150 mils from each package, adjacent to the rows that contain the hub interface. If the layout allows, wide metal fingers running on the VSS side of the board should connect the +V1.8 side of the capacitors to the +V1.8 power pins. Similarly, if layout allows, metal fingers running on the +V1.8 side of the board should connect the groundside of the capacitors to the VSS power pins.
11.5.13. 3.3-V FWH Decoupling

A 0.1-F capacitor should be placed between the Vcc supply pins and the Vss ground pins to decouple high frequency noise, which may affect the programmability of the device. Additionally, a 4.7-F capacitor should be placed between the Vcc supply pins and the Vss ground pins to decouple low frequency noise. The capacitors should be placed no further than 390 mils from the Vcc supply pins.
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11.5.14. 3.3-V General LAN Decoupling

All Vcc pins should be connected to the same power supply. All Vss pins should be connected to the same ground plane. Four to six decoupling capacitors, including two 4.7-F capacitors are recommended Place decoupling as close as possible to power pins.
11.6.
3.3-V Clock Driver Decoupling

The decoupling caps should be connected taking care to connect the Vdd pins directly to the Vdd side of the caps. However, the Vss pins should not be connected directly to the Vss side of the caps. Instead they should be connected to the ground flood under the part that is viaed to the ground plane. This is done to avoid Vdd glitches propagating out, getting coupled through the decoupling caps to the Vss pins. This method has been shown to provide the best clock performance. The decoupling requirements for a CK-408 compliant clock synthesizer are as follows:
One 10-f bulk decoupling cap in a 1206 package placed close to the Vdd generation circuitry. Six 0.1-f high frequency decoupling caps in a 0603-package placed close to the Vdd pins on the Clock driver. Three 0.1-f high frequency decoupling caps in a 0603-package placed close to the VddA pins on the Clock driver. One 10-f bulk decoupling cap in a 1206-package placed close to the VddA generation circuitry
11.7.
DDR Power Delivery Design Guidelines

The following sections summarize the DDR system voltage and current requirements as of the release this document. This document is not the original source for these specifications. For more information refer to Section 1.1Related Documentation. The following guidelines are recommended for a MCH-M DDR system memory design. The main focus of these MCH-M guidelines is to minimize signal integrity problems and improve the power delivery of the MCH-M system memory interface and the DDR SO-DIMMs.
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Design Guide
Figure 95. DDR Power Delivery Block Diagram

+V5
Vin
Switching Regulator
Vout Sense Adj.
+VDDR2.5
10K
+
10K
+ -
+VDDREF
+V5
Vin
Switching Regulator
Vout Sense Adj.
+VDDR1.25
11.7.1.
DDR Memory Bypass Capacitor Guidelines

Discontinuities in the DDR signal return paths will occur when the signals transition between the motherboard and the SO-DIMMs. To account for this ground to 2.5-V discontinuity a minimum of nine, 0603, 0.1-F, high-frequency bypass capacitors are required between the SO-DIMMs to help minimize any anticipated return path discontinuities that will be created. The bypass capacitors should connect to 2.5 V and ground. The ground via should be placed as close to the ground pad as possible. The 2.5-V trace should connect to a via that transitions to the 2.5-V copper flood and it should connect to the closet 2.5-V SO-DIMM pin on either the first or second SO-DIMM connector, with a wide trace. The capacitors 2.5-V traces should be distributed as evenly as possible amongst the two SO-DIMMs. Finally, the 2.5-V via should be placed as close to the 2.5-V pad as possible.
11.7.2.
2.5-V Power Delivery Guidelines

The 2.5-V power for the MCH-M system memory interface and the DDR-SO-DIMMs is delivered around the DDR command, control, and clock signals. Special attention must be paid to the 2.5-V copper flooding to ensure proper MCH-M and SO-DIMM power delivery. This 2.5-V flood must extend from the MCH-M 2.5-V power vias all the way to the 2.5-V DDR voltage regulator and its bulk capacitors, located at the end of the DDR channel beyond the second SO-DIMM connector. The 2.5-V DDR voltage regulator must connect to the 2.5-V flood with a minimum of six vias, and the SO-DIMM connector 2.5-V pins as well as the MCH-M 2.5-V power vias must connect to the 2.5-Vcopper flood. The copper flooding to the MCH-M should include at least seven fingers to allow for the routing of the
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DDR signals and for optimal MCH-M power delivery. The copper fingers must be kept as wide as possible in order to keep the loop inductance path from the 2.5-V voltage regulator to the MCH-M at a minimum. In the areas where the copper flooding necks down around the MCH-M make sure to keep these neck down lengths as short as possible. The 2.5-V copper flooding under the SO-DIMM connectors must encompass all the SO-DIMM 2.5-V pins and must be solid except for the small areas where the clocks are routed within the SO-DIMM pin field where they connect to their specified SODIMM pins. Additionally, a small 2.5-V cooper flood shape should be placed under the MCH-M, to encompass and increase the copper flooding to the back row of 2.5-V MCH-M pins. This flood must not be placed under any of the DDR signals. In order to maximize the copper flooding these signals should be kept as short as possible in order to reduce the amount of serpentining needed in this area on the bottom layer. Also, a minimum of 12-mil isolation spacing should be maintained between the copper flooding and the DDR signals. Finally, the six MCH-M 2.5V high frequency decoupling capacitors, located on the top signal layer, should have their 2.5-V via placed directly over and connected to a separate 2.5-V copper finger. Refer to Section 11.5 for decoupling capacitors.
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11.7.3.
Intel 845MP/845MZ Chipset DDR Reference Board Power Delivery

Figure 96 shows the power delivery architecture for the Intel 845MP/845MZ Chipset DDR memory subsystem. This power delivery example provides support for the suspend-to-RAM (STR) and the full Power-on State.
Figure 96. Intel 845MP/845MZ Chipset DDR Power Delivery Example

+VDC
DDR VR Vout = 2.5V DDR VR Vout = 1.25V, VREF IN
MCH-M Memory Interface
VTT: 1.25V TERM RES
VREF DIVIDER AND BUFFER CIRCUIT
VCCSM:2.50V 1.9A , 4.75W SMRCOMP: 1.25V,80mA SDREF: 1.25V,50uA
VDD & VDDQ: 2.5V,5.9A, 14.8W VREF: 1.25V,1mA
SO-DIMM
NOTES: 1. Designer must follow following recommendations. 2. VDD & VDDQ (2.5 V) must stay on to drive CKE signals in S3 state. 3. During S3 state VTT and SMRCOMP can be turned off. 4. VTT must have smooth soft start to prevent glitches. 5. VREF(DDR) & SDREF(MCH-M) must stay on to acknowledge the state of CKE signals in S3 state.
Following requirements must be met in order to turn off DDR Vtt in the S3 power state: MCH-M VCCSM (2.5 V) and SDREF must stay on to drive CKE signals in S3. DDR Vtt must have a smooth soft start to prevent glitches that can affect CKE pins being driven low. DDR Vtt must be stable and within voltage tolerance specification before ICH deasserts reset (PCIRST) to the MCH-M. Optional: Vtt to SMRCOMP can be off in S3 following the same above requirements. Please note MCHM will enable a weak pull-up when reset is asserted, so the command signals should all be high during S3.
11.7.4.
DDR Reference Voltage

The table below has grouped the voltage and current specifications together for each the MCH-M, memory and termination voltage. There are 7 voltages specified here for a DDR VR system. Although, there are only 2 unique voltage regulators for 2.5 V and 1.25 V nominal, each specific power rail described here has a unique specification. Described below are the memory components themselves first
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(the top 3 listed) and the MCH-M requirements (next row of 3) and finally the termination voltage and current requirements. For convenience, tolerances are given in both % and Volts though validation should be done using the spec exactly as it is written. The voltage specs are clearly defined under Specification Definition. If this states a tolerance in terms of volts (as Vref says 0.050 V) then that specific voltage tolerance should be used, not the a percentage of the measured value. Likewise, percentages should be used where stated. If not stated then either way if fine. Voltage specs are defined as either Absolute or Relative. These are described below:
Type Of Specification
Description
Absolute Specification
This is a standard specification most commonly used. This means that the voltage limits are based on a fixed nominal voltage and have a symmetric tolerance added to determine the acceptable voltage range. For example, Vdds spec does not depend on any other voltage levels. It is simply 2.5 V 8%. This is a specification whose nominal value is not fixed but is relative to or is a function of another voltage. This means that the other voltage must be measured to know what the nominal value is and then the symmetrical tolerance added to that measured value. For example, Vrefs spec depends on the actual value of Vdd to determine Vdd/2 and then tolerance 0.050 V from this calculated value.
Relative Specification
From the table below, it can be seen that only the 2.5-V supply is fixed an absolute specification, whereas all of the 1.25-V nominal supplies are relative to the 2.5-V supply directly or another 1.25-V supply which is then relative to the 2.5-V supply. Due to these 1.25-V relative specifications, it becomes very important that the 1.25-V supply can track the variations in the 2.5V supply and respond according to the 2.5 V variations. This can be implemented as shown in the block diagram in Figure 96 where the 2.5-V output is divided in half and used to generate the 1.25-V reference into the 1.25-V VR controller design. In this manner, the 1.25-V VR will respond proportionally to variations in the 2.5-V supply improving the voltage margin of the relative supply requirements and overall memory system stability. It should be noted that at launch, all of specifications in this document were current, however it is the current specifications are considered to be higher than actually expected and will be reduced in future specifications.
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Design Guide
Table 61. DDR SDRAM Memory Voltage & Current Specification

Name "Vdd" "Vddq" "Vref" Description
PURPOSE
CORE SUPPLY VOLTAGE, STATIC Vdd 2.500 8.0% 0.200 2.700 2.300 na
I/O SUPPLY VOLTAGE , STATIC Vddq 2.500 8.0% 0.200 2.700 2.300 na
I/O REFERENCE SUPPLY VOLTAGE, STATIC Vref = (Vdd/2) 0.050 V 1.250 4.0% 0.050 1.400 1.100 (measuredVdd/2)+0.050 V ((2.5 V+8%)/2)+0.050 V ((2.5 V-8%)/2)-0.050 V ((2.5 V+/-8%)/2) 0.050 V
SPECIFICATION DEFINITION VOLTAGE Nominal (V) TOLERANCE (%) TOLERANCE (-V) MAX ABSOLUTE SPEC VALUE (V) MIN ABSOLUTE PEC VALUE (V) MAX RELATIVE SPEC (calculated from measured "Vdd" value) MIN RELATIVE SPEC (calculated from measured "Vdd" value)
na
na
(measuredVdd/2)-0.050 V
Idd (max) ABSOLUTE MAXIMUM CURRENT REQUIREMENTS 5.000
Iddq (max) 0.920
Iref (max) 0.001
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Table 62. MCH-M DDR Voltage and Current Specifications

Name "VCCSM" "SDREF" "Vtt"= "SMRCOMP" Description
PURPOSE
MCH-M DDR SUPPLY VOLTAGE (I/O), STATIC VCCSM 2.500 5.0% 0.125 2.625 2.375 na
MCH-M REFERENCE SUPPLY VOLTAGE, STATIC
SMRCOMP TERMINATION SUPPLY VOLTAGE, STATIC
DEFINITION VOLTAGE Nominal (V) TOLERANCE (%) TOLERANCE (V) MAX ABSOLUTE SPEC VALUE (V) MIN ABSOLUTE SPEC VALUE (V) MAX RELATIVE SPEC (calculated from measured "VCCSM" value) MIN RELATIVE SPEC (calculated from measured "VCCSM" value)
SDREF=(VCCSM/2) 2% 1.250 2.0% 0.025 1.339 1.164 (measuredVCCSM/2)+ 2%
Vtt = ("Vref")+/-0.040V 1.250 3.2% 0.040 1.440 1.060 (measured Vref)+0.04V
(((2.5 V+/-8%)/2)+/0.050 V)+/-0.040)
(((2.5 V+8%)/2) + 0.050 V)+0.040) (((2.5 V-8%)/2) -0.050 V)-0.040)
na
(measuredVCCSM/2) 2%
(measured Vref)-0.040V
Ivccsm (max) ABSOLUTE MAXIMUM CURRENT REQUIREMENTS 1.900
Isdref (max) 0.010
Ittrc (max) 0.040
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Table 63. Termination Voltage and Current Specifications

Name "Vtt" Description
PURPOSE DEFINITION VOLTAGE Nominal (V) TOLERANCE (%) TOLERANCE (V) MAX ABSOLUTE SPEC VALUE (V) MIN ABSOLUTE SPEC VALUE (V) MAX RELATIVE SPEC (calculated from measured "VCCSM" value) MIN RELATIVE SPEC (calculated from measured "VCCSM" value)
TERMINATION SUPPLY VOLTAGE, STATIC Vtt = ("Vref") 0.040 V 1.250 3.2% 0.040 1.440 1.060 (measured Vref)+0.040 V (measured Vref)-0.040 V Itt (max) (((2.5 V+8%)/2)+0.050 V)+0.040 (((2.5 V-8%)/2)-0.050 V)-0.040 (((2.5 V+/-8%)/2) 0.050 V) 0.040
ABSOLUTE MAXIMUM CURRENT REQUIREMENTS
2.400
11.7.4.1.
VREF Generation
It may also be noted in Figure 95 that when the 1.25-V reference is generated from the 2.5-V supply a buffer is used. A buffer has also been used to provide this reference to the system for the MCH-M and memory. Specifically, this is the VREF signal to the memory and the SDREF signal to the MCH-M. Our reference design utilizes this buffer to provide the necessary current to these devices, which the simple resistor divider is not capable of providing. This SDREF voltage to the MCH-M has the tightest tolerance in the memory system of 2%. Using common 1% resistors consumes 1% of this 2% tolerance. This means SDREF must now be controlled to a 1% tolerance (i.e. be able to divide VCCSM/2 within 1%). A simple resistor divider is not a voltage regulator and is most definitely not a current source. Any current drawn across the resistor divider used to generate this 1.25-V reference will cause a voltage drop across the top resistor that distorts or biases this reference to a lower voltage.
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Table 64. MCH-M DDR I/O

NAME VCCSM1 SDREF
PURPOSE
MCH-M DDR SUPPLY VOLTAGE (I/O), STATIC VCCSM
MCH-M REFERENCE SUPPLY VOLTAGE, STATIC SDREF =( VCCSM 5%) / 2 1.250 " 2%"
VOLTAGE Nominal (V)
2.500 " 5%"
TOLERANCE (+/-V) Vmax(V) Vmin(V)
0.125 2.625 2.375 Ivccsm (max)
0.025 1.275 1.225 Isdref (max) 0.010
Imax
NOTE:
1.400
MCH-M VREF REQUIREMENTS: the MCH-M core is called "VCCSM" =+2.5 V 5%. SDREF is ("VCCSM" 5%) /2 2%. This means that whether the 2.5v is 5% high or low, we need to be able to divide that voltage by 2 with a 2% accuracy. This basically means to use 1% resistors, or better.
As shown in Table 64, the max current required by the MCH-M for the SDREF input is 0.010 A. This is too big of a load for a resistor divider. Some sample calculations are shown in the table below. It is not possible to maintain regulation within 2% using a resistive divider without using a resistor so small that the 2.5-V current requirement becomes prohibitive. Hence, a buffer is required due to the 10-mA current requirement of the MCH-M SDREF.
Table 65. Effects of Varying Resistor Values in the Divider Circuit
Rdivider (ohms) Leakage (A) Rtop Vdroop (V) I(2.5) total=2.5v/2R (A)
1 10 100 1000
10000
0.01 0.01 0.01 0.01

0.01
0.01 0.1 1 10
100
1.25 0.125 0.0125 0.00125 0.000125 1.25E-05 1.25E-06
100000 1000000
0.01 0.01
1000 10000
Rdivider: This is the resistor value selected to form the divider. Assumes both top and values are equal as required for divide by 2. Leakage: This is the amount of leakage current which needs to sourced from the 2.5-V supply, across the dividers top resistor (Rtop) and out to the MCH-M SDREF input or the DDR VREF input. This current does not go across the bottom resistor. Rtop Vdroop: This is the resulting voltage droop across Rtop as a result of the leakage current. I(2.5) total=2.5 V/2R This is the total current through divider. This is calculated to consider the amount of current & power used as a DC current through the divider.
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The implementation of a buffer is also required by the DDR. The same VREF may be used for both MCH-M and the DDR as well.
11.7.4.2.
DDR VREF Requirements

Making the same calculations for the DDR loading, results to find the max Vref load of 1 mA, a divider is STILL NOT feasible here as the load of 1 mA causes unacceptable drop across even small Rs, which waste power.
Table 66. MCH-M VREF Calculation

NAME Vdd Vref
PURPOSE
CORE SUPPLY VOLTAGE , STATIC

Vdd
I/O REFERENCE SUPPLY VOLTAGE, STATIC

Vref = (Vdd=/-8%) / 2 1.250
VOLTAGE Nominal (V) TOLERANCE (+/-V) Vmax(V) Vmin(V)
2.500(+/-8%)
0.200 2.700 2.300 Idd
0.050 1.300 1.200 Iref

0.001
Section 11.7.3
5.000
Note:
The DDR core is called "Vdd" =+2.5 V +/-8% (= 0.2 V). VREF is ("Vdd"+/-8% )/2 50 mV. This means that whether the 2.5 V is 8% high or low, we need to be able to divide that voltage by 2 within a 50-mV accuracy. This basically means to use 1% resistors, or better.
Table 67. Reference Distortion Due to Load Current

R(ohms) I(A) Vdroop(V) I2.5 total=2.5v/2R(A)
1 10 100 1000
10000
0.001 0.001 0.001 0.001 0.001 0.001 0.001
0.001 0.01 0.1 1

10
1.25 0.125 0.0125 0.00125 0.000125 1.25E-05 1.25E-06
100000 1000000
100 1000
Note:
As for the MCH-M, a calculation can be made for the DDR. This shows that even with the slight load of 1 mA by the DDR it is still not feasible to use a simple resistor divider. Using the max leakage specs provided today and trying to maintain an error of less than 1%( 12.5 mV) one needs to decrease the resistor values such that the current just to source the divider becomes unacceptable. A divider alone does not become an acceptable solution until current requirements are in the 100-A range. Today, it is not possible to guarantee this type of current requirement for these applications. Hence, the use of a buffer is highly recommended for these reference voltage requirements.
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11.7.5.
DDR SMRCOMP Resistive Compensation

The MCH-M uses a compensation signal to adjust the system memory buffer characteristics over temperature, process, and voltage variations. The DDR system memory (SMRCOMP) must be connected to the DDR termination voltage (1.25 V) through a 30 1% resistor and one 0603 0.1-F decoupling capacitor to ground. Place the resistor and capacitor as close to the MCH-M as possible, within 1.0 inch of the MCH-M package. The compensation signal and the VTT trace should be routed with as wide a trace as possible, minimum of 12-mils wide and isolated from other signals with a minimum of 10-mils spacing.
Figure 97. SMRCOMP Recommendation

DDR Vtt (1.25 V)
Less than 1"
MCH-M
SMRCOMP
30.1 Ohms +/- 1%
0.1 uF
11.7.6.
DDR VTT Termination

All DDR signals, except the command clocks, must be terminated to 1.25 V (VTT) using 5% resistors at the end of the channel opposite the MCH-M. Place a solid 1.25-V (VTT) termination island on the top signal layer, just beyond the last SO-DIMM connector. The VTT Termination Island must be at least 50mils wide. Use this termination island to terminate all DDR signals, using one resistor per signal. Resistor packs are acceptable, with the understanding that the signals within an RPACK are from the same DDR signal group. No mixing of signals from different DDR signal groups is allowed within an RPACK. The parallel termination resistors connect directly to the VTT Island on the top signal layer.
11.8.
Clock Driver Power Delivery Design Guidelines

Special care must be taken to provide a quiet VddA supply to the Ref Vdd, VddA and the 48MHz Vdd. These VddA signals are especially sensitive to switching noise induced by the other Vdds on the cock chip. They are also sensitive to switching noise generated elsewhere in the system such as CPU VRM. The CLC Pie filter should be designed to provide the best reasonable isolation. Intel recommends that a solid ground plane be underneath the clock chip on layer 2. (Assuming top trace is layer 1). It is also recommended that a ground flood be placed directly under the clock chip to provide a low impedance connection for the Vss pins. For ALL power connections to planes, decoupling caps and vias , the MAXIMUM trace width allowable and shortest possible lengths should be used to ensure lowest possible inductance. The decoupling caps should be connected as shown in the illustration taking care to connect the Vdd pins directly to the Vdd side of the caps. However the Vss pins should not be connected directly to the Vss side of the caps. Instead they should be connected to the ground flood under the part that is viaed to the ground plane. This is done to avoid Vdd glitches propagating out, getting coupled through the decoupling caps to the Vss pins. This method has been shown to provide the best clock performance.
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The ground flood should be viaed through to the ground plane with no less than 12-16 vias under the part. It should be well connected. For all power connections, heavy duty and/or dual vias should be used. It is imperative that the standard signal vias and small traces not be used for connecting decoupling caps and ground floods to the power and ground planes. VddA should be generated by using a CLC filter. This VddA should be connected to the Vdd side of the three capacitors that require it using a hefty trace on the top layer. This trace should be routed from the CLC filter using a star topology.
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Figure 98. Decoupling Capacitors Placement and Connectivity

VddA Vdd XTAL_In XTAL_Out Vss PCIF 0 PCIF 1 C1 Vs s PCIF 2 Vdd Vss Vdd PCI 0 PCI 1 PCI 2 C2 Vss PCI 3 Vdd Vss Vdd PCI 4 PCI 5 PCI 6 Vdd Vss 66Buff0 / 3V66_2 66Buf f1 / 3V66_ 66Buf 3 f2 / 3V66_ 4 66In / 3V66_5 PWRD WN# VddA Vdd A Vss A
Vtt_Pwr gd #
1 2 3 4
56 55 54 53 52 51 50 49 48 47
REF 0 S1 Vss Plane Vias S0 CPU_Sto p# CPU 0 CPU /0 Vdd CPU 1 CPU /1 Vss Vdd CPU 2 CPU /2 Mult 0 IRE F Vss Iref S2 US B 48 MHz DO T 48 MHz Vdd 48 MHz Vss 48 MHz
3V66_1 / VCH
5 6 7 8 9
C6
Vss
Vdd
10 11
C5
46 45 44 43 Vs s Gr ou nd Flo od 42 41
Vss
12 13 14
Vdd
15 16 17 18 19 20
40 39
C3 Vss
38 37 36
VddA
Vdd
21 22 23 24 25 26 27
35 34 33
PCI_Sto p# 3V66 _0 C4 Vss
Vd SCL 32 Vss d Vdd K 31 Vs s SCL K SDAT A
Vdd
30 29
28
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12.
12.1.
System Design Checklist

Host Interface
Mobile Intel Pentium 4-M Resistor Recommendations Signal System Pull-up/ Pull-down Notes
Table 68. Resistor Recommendations
H_A[35:3]#
Connect A[31:3]# to MCH-M. Leave A[35:32]# as No Connect Pull-up to VCC_CORE Pull-up to VCC_CORE Pull-up to VCC_CORE Pull-down to GND Pull-up to V3.3S Pull-up to VCC_CORE 51.1 1% 1 k 51 1% 10 k
A[35:32]# are not supported by the chipset. Has internal pull-up to VCC_CORE Place resistor < 0.1 from CPU interface Required pull-up for noise reduction Use Voltage Translation Circuit Individual pull-down resistor
H_RESET# H_IERR# H_FERR# COMP[1:0] CPU_VR_VID [4:0] TESTHI0/BYPASSEN# TESTHI1/H_ODT TESTHI2/H_MCLK0 TESTHI3/ H_MCLK1 TESTHI4/ H_MCLK2 TESTHI5/ H_MCLK3 TESTHI8/H_BR3# TESTHI9/H_BR2# TESTHI10/H_BR1#
The TESTHI pins should be tied to the processor VCC using a matched resistor, where a matched resistor has a resistance value within + 20% of the impedance of the board transmission line traces. For example, If the trace impedance is 50 ohm, then a value between 40 and 60 is required. The TESTHI pins may use individual pullup resistors or be grouped together as detailed below. A matched resistor should be used for each group: 1) TESTHI[1:0] 2) TESTHI[5:2] 3) TESTHI[10:8]
TESTHI6/ITPCLKOUT0 TESTHI7/ITPCLKOUT1
These pins as differential clock for an ITP port designed on the motherboard. if the ITPCLKOUT[1:0] pins are not used then they may be connected individually to VCC using matched resistors or grouped with TESTHI[5:2] with a single matched resistor. If they are being used, individual termination with 1-K resistors is required. Tying ITPCLKOUT[1:0] directly to VCC or sharing a pull-up resistor to VCC will prevent use of debug interposers.
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This implementation is strongly discouraged for system boards that do not implement an onboard debug port. As an alternative, group 2 (TESTHI[5:2]), and the ITPCLKOUT[1:0] pins may be tied directly to the processor VCC. This has no impact on system functionality. TESTHI[0] may also be tied directly to processor VCC if resistor termination is a problem, but matched resistor termination is recommended. In the case of the ITPCLKOUT[1:0] pins, direct tie to VCC is strongly discouraged for system boards that do not implement an onboard debug port. MCERR# AP[1:0] BINIT# DP[3:0] RSP# H_A20M# H_IGNNE# H_INTR H_NMI H_STPCLK# H_SMI# H_DPSLP# H_CPUSLP# H_INIT# H_BR0# H_BPM[5:0] PM_CPUPERF# H_PWRGD NC NC NC NC NC Pull-up to VCC_CORE Pull-up to VCC_CORE Pull-up to VCC_CORE Pull-up to VCC_CORE Pull-up to VCC_CORE Pull-up to VCC_CORE Pull-up to VCC_CORE Pull-up to VCC_CORE Pull-up to VCC_CORE Pull-up to VCC_CORE Pull-up to VCC_CORE Terminate to VCC_CORE Pull-up to VCC CORE 200 200 200 200 200 200 200 200 200 220 51 200 300
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Design Guide
VCC_CORE
NOTE:
Default tolerance for resistors is 5% unless otherwise specified.
12.2.
In Target Probe (ITP)

Mobile Intel Pentium 4 Processor-M ITP (In Target Probe) Signal System Pullup/Pull-down Series Damping Notes
Table 69. In Target Probe (ITP)
ITP_TDI ITP_TDO ITP_TRST# ITP_PREQ# ITP_PRDY#
Pull-up to VCC_CORE Pull-up to VCC_CORE Pull-down to GND Pull-up to VCC_CORE Pull-up to VCC_CORE
150 75 680 51 51 240 Place resistor < 1 from port; Debug port must be at end of trace; See Spec. Update for latest details If ITP/TAP unused pull-down with 1.5 k
ITP_D_TMS ITP_D_TCK ITP_RST# DBRESET# ITP_POWERON
Pull-up to VCC_CORE Pull-down to GND Pull-up to VCC_CORE Pull-up to V3.3 Pull-up to VCC_CORE
39 27.4 51 + 1% 150 1.5 k
Place resistor < 1 from port; Debug port must be at end of trace Place resistor < 1 from port; Debug port must be at end of trace Place resistor < 1 from port; Debug port must be at end of trace
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12.3.
Thermal Sensor
Mobile Intel Pentium 4 Processor-M Thermal Sensor Signal System Pull-up/Pulldown Notes
Table 70. Thermal Sensor Signals
ADD[1:0] STBY# SMBDATA SMBCLK THRM_ALERT# DXP, DXN
Pull-up to V3.3S Pull-up to V3.3S Pull-up to V3.3S Pull-up to V3.3S Pull-up to V3.3S
1 k 10 k 10 k 10 k 10 k To enable alert, ALERT# can be connected to THRM# on ICH-M Route both signals on same layer
12.4.
PLL[2:1] PLC Filter

Mobile Intel Pentium 4 Processor-M PLL[2:1] RLC Filter Device Value Notes
Table 71. PLL[2:1] RLC Filter
L C
4.7 H at 80 mA or 10 H at 60 mA 22-100 F
Rated for DC current > 60 mA ESR<0.3 ESL<5 nH Tolerance 20%
12.5.
Decoupling Recommendation
Mobile Intel Pentium 4 Processor-M High Frequency Decoupling Recommendations* Signal Configuration F Qty Notes
Table 72. Decoupling Recommendation
+VCC_CORE
See Processor Power Delivery Design Recommendations
10 F_6.3 V
38
Use 2-3 vias per pad for reduced inductance during layout. Placement should be near processor for all
NOTE:
*All decoupling guidelines are recommendations based on our reference board design. Customers will need to take their layout and PCB board design into consideration when deciding on their overall decoupling solution.
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Design Guide
12.6.
CK-408 Clock Checklist

Checklist Items Recommendations Reason/Impact
Table 73. Resistor Recommendation
66_BUFF0 66_BUFF1 66_BUFF2 66_INPUT CPU0 CPU0# CPU1 CPU1# CPU2 CPU2# CPU_STOP# DOT_48 MHz IREF MULT0 PCI [6:0] PCIF [2:0] PCI_STOP# ** PWRDWN# REF0 SEL_0 SEL_1
Connect to MCH-M. Series resistor of 33 1% Connect to ICH3-M. Series resistor of 33 1% Connect to AGP. Series resistor of 33 1% No Connect.
Refer to the reference schematics. Refer to the reference schematics. Refer to the reference schematics. Refer to the reference schematics. Refer to the reference schematics. Refer to the reference schematics. Refer to the reference schematics. Refer to the reference schematics. Refer to the reference schematics. Refer to the reference schematics.
Connect to ICH3-M STPCPU# No Connect Terminate to ground through a 475 1% resistor. Brought in through V3.3S coming through a series resistor of 10 k 5% Series resistor of 33 1% Series resistor of 33 1% Connect to ICH3-M STPPCI# Connect to ANDED SLP_S1# and SLP_S3# powered by non-switch +V3.3. Series resistor of 33 5% Pull up to VCC3_CLK with a 1 K resistor. Pull down to GND with 1 K resistor.
Internal Pull-up Refer to the reference schematics. Refer to the reference schematics. Refer to the reference schematics. Refer to the reference schematics. Refer to the reference schematics. Refer to the reference schematics. Refer to the reference schematics. Refer to the reference schematics. Refer to the reference schematics. Refer to the reference schematics.
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Checklist Items
Recommendations
Reason/Impact
SEL_2 SCLK SDATA USB_48MHZ VDD VDD_48MHZ VDDA VSS VSS_48MHZ VSS_IREF VTT_PWRGD# XTAL_IN XTAL_OUT
Pull down to ground through a1 K 5% resistor. Connect to SO-DIMMs. Connect to SO-DIMMs. Connect to ICH3-M. 33 5% series resistor Connect to VCC3_CLK and decouple with 0.1 F 5% value. Connect to VCC3_CLK and decouple with 0.1 F 5% value. Connect to VCC3_CLK and decouple with 0.1 F 5% value. Connect to ground. Connect to ground. Connect to ground. Connect to inverted and delayed VCC_CORE pwrgd
Refer to the reference schematics. Refer to the reference schematics.
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Design Guide
12.7.
DDR SO-DIMM0 Connector

Table 74. DDR S0-DIMM0 Recommendations
S#[0]
Connect to SCS#[0] pin on MCH-M Connect to a 56 ohm 5% parallel termination resistor tied to Vtt (1.25 V DDR Termination Voltage)
Refer to the reference schematics.
S#[1]
CKE[0]
Connect to the MCH-M SCKE[0] pin Connect to a 56 ohm 5% parallel termination resistor tied to Vtt (1.25 V DDR Termination Voltage)
CKE[1]
A[12:0]
Connect to the MCH-M SMA[12:0] pins Connect to SO-DIMM1 with a 10 5% resistor
RAS#
Connect to the MCH-M SRAS# pin Connect to SO-DIMM1 with a 10 5% resistor
CAS#
Connect to the MCH-M SCAS# pin Connect to SO-DIMM1 with a 10 5% resistor
WE#
Connect to the MCH-M SWE# pin Connect to SO-DIMM1 with a 10 5% resistor
BA[1:0]
Connect to the MCH-M SBS[1:0] pins Connect to SO-DIMM1 with a 10 5% resistor
DQ[63:0]
Connect to MCH-M SDQ[63:0] signals through 22 ohm 5% series resistors Connect to a 56 ohm 5% parallel termination resistors tied to Vtt (1.25V DDR Termination Voltage)
CB[7:0]
Connect to MCH-M SCB[7:0] signals through 22 ohm 5% series resistors Connect to a 56 ohm 5% parallel termination resistors tied to Vtt (1.25 V DDR Termination Voltage)
For systems not implementing ECC SODIMMS CB[7:0] can be left as no connect For systems not implementing ECC SODIMMS DQS[8] can be left as no connect
DQS[8:0]
Connect to MCH-M SDQS[8:0] signals through 22 ohm 5% series resistors Connect to a 56 ohm 5% parallel termination resistors tied to Vtt (1.25 V DDR Termination Voltage)
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Checklist Items
Recommendations
Reason/Impact
DM[8:0] / DQS[17:9] CK[2:0] CK#[2:0] SA[2:0] SDA SCL VDD VDDQ VREF
Connect to Ground Connect to the MCH-M SCK[2:0] pins Connect to the MCH-M SCK#[2:0] pins Connect to ground. Connect to SMB_DATA and SMB_CLK with 10 K resistor pull-ups to +V3.3Always Connect to DDR 2.5 V Connect to DDR 2.5 V Connect to DDR Reference Voltage (Vref) Connect to a 0.1 F capacitor tied to ground
VSS VDDSPD
Connect to ground. Serial EEPROM positive power supply (wired to a separate pin at the connector, which supports operation from a minimum of 2.3 V to a maximum of 3.6 V). This pin is isolated from the Vdd/Vddq supply voltages. Recommend connecting this to 3.3VAlways
VDDID
No Connect.
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Design Guide
12.8.
DDR SO-DIMM1 Connector

Table 75. DDR S0-DIMM0 Recommendations
S#[0]
S#[1]
CKE[0]
CKE[1]
A[12:0] RAS# CAS# WE# BA[1:0] DQ[63:0]
Connect to a 56 ohm 5% parallel termination resistors tied to Vtt (1.25 V DDR Termination Voltage) Connect to a 56 ohm 5% parallel termination resistors tied to Vtt (1.25 V DDR Termination Voltage) Connect to a 56 ohm 5% parallel termination resistors tied to Vtt (1.25 V DDR Termination Voltage) Connect to a 56 ohm 5% parallel termination resistors tied to Vtt (1.25 V DDR Termination Voltage) Connect to a 56 ohm 5% parallel termination resistors tied to Vtt (1.25 V DDR Termination Voltage) Connect to the MCH-M SDQ[63:0] pins through 22 ohm 5% series resistors described in Sect. 6 Connect to a 56 ohm 5% parallel termination resistors tied to Vtt (1.25 V DDR Termination Voltage)
Refer to the reference schematics. Refer to the reference schematics. Refer to the reference schematics. Refer to the reference schematics. Refer to the reference schematics. Refer to the reference schematics.
CB[7:0]
Connect to the MCH-M SCB[7:0] pins through 22 ohm 5% series resistors described in Sect. 6 Connect to a 56 ohm 5% parallel termination resistors tied to Vtt (1.25 V DDR Termination Voltage)
For systems not implementing ECC SODIMMS CB[7:0] can be left as no connect For systems not implementing ECC, SODIMMS DQS[8] can be left as no connect. Refer to the reference schematics. Refer to the reference schematics. Refer to the reference schematics.
DQS[8:0]
Connect to the MCH-M SDQS[8:0] pins through 22 ohm 5% series resistors described in Section 6. Connect to a 56 ohm 5% parallel termination resistors tied to Vtt (1.25 V DDR Termination Voltage).
DM[8:0] / DQS[17:9] CK[2:0] CK#[2:0]
Connect to Ground Connect to the MCH-M SCK[5:3] pins Connect to the MCH-M SCK#[5:3] pins
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Checklist Items
Recommendations
Reason/Impact
SA[2:0]
Connect SA2 and SA1 to ground Connect SA0 to V3.3S
Refer to the reference schematics. Refer to the reference schematics. Refer to the reference schematics. Refer to the reference schematics. Refer to the reference schematics. Refer to the reference schematics. Refer to the reference schematics.
SDA SCL VDD VDDQ VREF
Connect to SMB_DATA and SMB_CLK with 10K resistor pull-ups to +V3.3Always Connect to DDR 2.5 V Connect to DDR 2.5 V Connect to DDR Reference Voltage (Vref) Connect to a 0.1-F capacitor tied to ground
VSS VDDSPD
Connect to ground. Serial EEPROM positive power supply (wired to a separate pin at the connector, which supports operation from a minimum of 2.3 V to a maximum of 3.6 V). This pin is isolated from the Vdd/Vddq supply voltages. Recommend connecting this to 3.3VAlways
VDDID
No Connect.
Table 76. DDR Extra

Checklist Items RCVENOUT# RCVENIN# VCCSM[38:0] SDREF Recommendations Connect to MCH-M RCVENIN# pin Connect to MCH-M RCVENOUT# pin Connect MCH-M VCCSM pins to 2.5 V Connect to DDR Reference Voltage (Vref) Connect to a 0.1-F capacitor tied to ground Reason/Impact
192
Design Guide
12.9.
MCH-M Signals
MCH-M Processor System Bus (PSB) Signals Signal System Pull-up/Pull-down Notes
Table 77. Processor System Bus Signals
H_D#[63:0], H_A#[31:3], H_REQ#[4:0], H_RS#[2:0] H_RESET#
Route all signals between processor and MCHM with board trace impedance
Route all signals between processor and MCHM with 55 1% trace impedance; Also drives H_RESETX w/ 0 series damping Route all signals between processor and MCHM with 55 1% trace impedance
H_ADS#, H_BNR#, H_BPRI#, H_DBSY#, H_DEFER#, H_DRDY#, H_HIT#, H_HITM#, H_LOCK#, H_TRDY# H_XRCOMP H_YRCOMP SCK6/CLK6, SCK#6/CLK7, SCK7/CLK10, SCK#7/CLK11, SCK8/CLK9, SCK#8/CLK8 HXSWING HYSWING
NOTE:
Connect to GND
24.9 1%
Referencing a 50- buffer impedance
No Connect No Connect No Connect No Connect No Connect No Connect
Please refer to Customer Reference Board schematic for SCKE[3:0] connection. Also SCS#[5:4] are NC. Intel does not support SCS[5:4].
Design Guide
193
Table 78. Miscellaneous Signals

MCH-M Miscellaneous Signals Signal System Pull-up/Pull-down Notes
AGP_RCOMP
Connect to GND
36.5 1%
For AGP devices Referencing a 55- board impedance
HUB_RCOMP SMRCOMP
Pull-up to VCC1_8 Connect to DDR Termination Voltage (Vtt) through a 30.1 1% pull-up resistor. Connect to a 0.1-F capacitor tied to ground.
36.5 1%
Referencing a 55- board impedance

MCH-M High Speed Decoupling Recommendations Signal Configuration F Qty Notes
HUB_VREF SM_VREF +VCC_CORE (VTTFSB) +V1.5S_MCH (VCCAGP)
Decouple to GND Decouple to GND Decouple to GND Decouple to GND Decouple to GND Decouple to GND
0.01 F 0.1 F 0.1 F 10.0 F 0.1 F 10.0 F 100 F
1 1 10 3 6 2 1 3 1 6(min) 2 3
Place close to MCH-M Place as close as possible to the MCH-M SDREF Input (J21/J9) Distribute as close as possible to MCH-M VTTFSB Quadrant Distribute as close as possible to MCH-M AGP/Core Quadrant
+V1.8S_MCH (VCCHL) +V2.5 for MCH
Decouple to GND Decouple to GND Decouple to GND
0.1 F 10 F 0.1 F 22.0 F 100 F 150 F
Distribute as close as possible to MCH-M Hub Interface Quadrant Distribute as close as possible to MCH-M System Memory Quadrant;
+V2.5 for DDR
Decouple to GND
0.1 F 100 F 150 F
9(min) 4 5 54(min)
One 0.1 F cap per power pin. Place each cap close to DDR pin.
+V1.25V
Decouple to GND
0.1 F
Place one cap close to every 2 pull up resistors termination.
NOTE:
Please check on Low Frequency Decoupling values for the 2.5 DDR and 2.5 MCH-M.
194
Design Guide
Table 80. Reference Voltage Dividers

MCH-M Reference Voltage Dividers* Signal System Pull-up/Pulldown F Notes
SM_VREF HUB_VREF Voltage divider with w/ cap and 0 in parallel to bottom resistor 301 1% (both) 0.01 F Place divider pair in middle of bus. Divided voltage is [1/2]*1.8 V.
Design Guide
195
12.10.
AGP
AGP Resistor Recommendations Signal System Pull-up/Pulldown Series Damping Notes
Table 81. Resistor Recommendation
AGP_SBSTB# AGP_ADSTB[1:0]# ST[0] ST[2:1] Pull-down to GND Pull-up to V1.5S 2 k 8.2 k
Have internal pull-downs.
ST[0] signal pulled low indicates that system memory is DDR SDRAM It is required that ST[2:1] have site for external pull-down resistor to ground, but the resistor should not be populated.
AGP_PERR# AGP_SERR# AGP_PIPE# AGP_GNT# AGP_ADSTB[1:0] AGP_SBSTB AGP_FRAME# AGP_TRDY# AGP_STOP# AGP_DEVSEL# AGP_IRDY# AGP_RBF# AGP_REQ# AGP_WBF# AGP_BUSY#
Pull-up to V1-5S
8.2 k
Have internal pull-ups.
Pull-up to V3_3S_ICH
10 k
Connect to ICH AGP_BUSY# pin AGPBUSy# must be connected to AGP Graphics controller supporting AGP Busy/Stop protocol
STP_AGP#
NOTE:
Connect to ICH C3_STAT# pin
196
Design Guide

AGP High Speed Decoupling Recommendations* Signal Configuration F Qty Notes
AGP_VREF +V1-5S_AGP
Decouple to GND Decouple to GND
0.1 F 150 F 0.1 F 22 F
2 2 7 1 1 3 2 2 1 1
Place one capacitor near MCH-M and one near AGP connector Distribute as close as possible to AGP connector VDDQ and VDDQ1.5 Quadrants Distribute as close as possible to AGP connector VCC3.3 Quadrant
+V3S_AGP
Decouple to GND
100 F 0.1 F 22 F
+V5S_AGP
Decouple to GND
0.1 F 22 F
Distribute as close as possible to AGP connector V5.0 Pins Distribute as close as possible to AGP connector 12 V Pin
+V12S
Decouple to GND
0.1 F

AGP Reference Voltage Dividers* Signal System Pull-up/Pull-down Notes
AGP_VREF
1 k (Each resistor in divider)
Place in between video controller and MCH-M. (1/2)VDDQ to video controller and MCH-M.
NOTE:
All decoupling guidelines are recommendations based on our reference board design. Customers will need to take their layout and PCB board design into consideration when deciding on their overall decoupling solution.
Design Guide
197
12.11.
ICH3-M Checklist
ICH3-M PCI Resistor Recommendations Signal System Pull-up/Pull-down Series Damping Notes
Table 84. PCI Resistor Recommendation
PCI_FRAME#, PCI_IRDY#, PCI_TRDY#, PCI_STOP# PCI_PERR#, PCI_SERR#, PCI_DEVSEL#, PCI_LOCK# PCI_GPIO0/ REQA#, PCI_GPIO1/ REQB#/REQ5#, PCI_REQ#[4:0] PCI_RST#
Pull-up to V3.3S
8.2 k
Alternative system can be 2.7 k pull-up to V5S
Pull-up to V3.3S
8.2 k
Pull-up to V3.3S
8.2 k
22 or 33
Should be buffered to form IDE_RST# for improved signal integrity Has integrated pull-up
PCI_PME# PCI_GNT#[4:0] External pull-up not required. If external resistors implemented, they must be pulled up to V3.3S
PCI_GPIO16/ GNTA#, PCI_GPIO17/ GNTB#/GNT5#
Has integrated pull-up; GNT[A] has an added strap function of top block swap. The signal is sampled on the rising edge of PWROK. Default value is high or disabled due to pull-up. A Jumper to a pull down resistor can be added to manually enable the function. Pull-up to V3.3S Pull-up to V3.3S Pull-up to V3.3S Connect to GND Connect to GND 8.2 k 8.2 k 8.2 k 10 k Open drain signal. Alternative system can be 2.7 k pull-up to V5S Alternative system can be 2.7 k pull-up to V5S Connect both signals through one 10 k resistor
INT_IRQ[15:14], INT_SERIRQ INT_PIRQ[D:A]# INT_PIRQ[H:E]#/ GPIO[5:2] INT_APICD[1:0] INT_APICCLK

NOTE:
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Design Guide
Table 85. System Management Interface (SM-BUS)

ICH3-M System Management Interface Signal System Pull-up/Pull-down Notes
SM_LINK[1:0] SM_INTRUDER# SMB_ALERT#/ GPIO11 SMB_CLK, SMB_DATA
Pull-up to V3_3ALWAYS Pull-up to V3_3ALWAYS Pull-up to V3_3ALWAYS Pull-up to V3_3ALWAYS
4.7 k 100 k 10 k 10 k Pull signal to VCCRTC (VBAT) if not needed Pull-up only if using this signal as SMB_ALERT#
Table 86. AC 97 Interface

ICH3-M AC 97 Interface Signal System Pull-up/Pull-down Series Damping Notes
AC_BITCLK
Has internal pull-down 20 k enabled only when AC_SHUT bit is set to 1 33 No extra pull-down resistors required. Some implementations add termination for signal integrity. External pull-down not required Has internal pull-down 20 k enabled only when AC_SHUT bit is set to 1
AC_SYNC
AC_SDATAIN [1:0] AC_SDATAOUT
Table 87. Power Management Interface

ICH3-M Power Management Interface Signal System Pull-up/Pulldown Series Damping Notes
PM_CLKRUN#/ GPIO24 PM_RI# PM_THRM#
Pull-up to V3.3S Pull-up to V3_3ALWAYS Pull-up to V3.3S
10 k 8.2 k 8.2 k Pull-up required only if temperature sensor not used; Alternative system can be 2.7 k to V5S; External pull-up/down not required if connecting to temperature sensor
Design Guide
199
ICH3-M Power Management Interface Signal System Pull-up/Pulldown Series Damping Notes
DPRSLPVR , PM_SLP_S3#, PM_SLP__S5# PM_PWRBTN# PM_LANPWROK , PM_RSMRST#
External pull-up/down not required.
Has integrated pull-up of 24 k Timing Requirement: Signal should be connected to power monitoring logic, and should go high no sooner than 10 ms after both Vcc3_3 and Vcc1_8 have reached their nominal voltages Refer to the reference schematics.
PWROK
This signal should be connected to power monitoring logic, and should go high no sooner than 10 ms after both VCC3_3 and VCC1_8 have reached their nominal voltages.
8 K22 K
RTC well input requires pull-down to reduce leakage from coin cell battery in G3. Input must not float in G3.
200
Design Guide
Table 88. LPC Interface

ICH3-M LPC Interface Signal System Pull-up/Pull-down Notes
LPC_AD[3:0], LPC_DRQ#[1:0]
Has integrated weak internal pull-up
Table 89. USB Interface

ICH3-M USB Interface Signal System Pull-up/Pull-down Series Damping Notes
USB_RBIAS HUB_VREF
Pull-down to GND
18.2 1%
22.6 for ICH3-M B0 ES Samples only
12.12.
HUB Interface
ICH3-M Hublink Decoupling Recommendations* Signal Configuration F Qty Notes
HUB_VREF HUB_VSWING
Pull-down to GND Pull-down to GND
0.01 F 0.1 F
1 ea. 1 ea.
Table 91. Reference Recommendation

ICH3-M Hublink Reference Voltage Dividers* Signal System Pull-up/Pull-down Notes
HUB_VSWING
Voltage divider w/ bottom resistor parallel to RC in series (0.1 F)
301 1% (for both)
Place divider pair in middle of bus; Range for voltage divider resistors: 100 1 k
NOTE:
Design Guide
201
Table 92. RTC Circuitry

ICH3-M RTC Circuitry Recommendations Signal System Pull-up/Pull-down Notes
CLK_VBIAS
Connect 10 M across to CLK_RTCX1 and 0.047 F decoupling cap in series with 1 k Connect a 32.768 kHz crystal oscillator across these pins with a 10 M resistor and use 12 pF decoupling caps at each signal.
10 M 1 k
Cap for noise immunity This DC Voltage is a self-adjusted voltage. Board designers should not manually bias the voltage level on VBIAS. VBIAS should be at least 200 mV DC. Refer to reference schematics. RTCX1 may optionally be driven by an external oscillator, instead of a crystal. These signals are 1.8 V only, and must not be driven by a 3.3V source. Circuitry is required since the new RTC oscillator is sensitive to step voltage changes in VCCRTC and VBIAS. A negative step on power supply of more than 100 mV will temporarily shut off the oscillator for hundreds of milliseconds.
CLK_RTCX1, CLK_RTCX2
10 M
NOTES: 1. Connect supply clock inputs to X1 and X2 of the ICH3-M because other signals are gated off that clock in suspend modes. However, in this case, the frequency (32.768 kHz) of the clock inputs is not critical; a lowercost crystal can be used or a single clock input can be driven into X1 with X2 left as no connect 2. To maintain RTC accuracy, the external capacitor C3 needs to be 0.047 F and capacitor values C1 and C2 should be chosen to provide the manufacturers specified load capacitance (Cload) for the crystal when combined with the parasitic capacitance of the trace, socket (if used), and package. The following equation can be used to choose the external capacitance values:
Cload = [(C1 + Cin1 + Ctrace1 )*(C2 + Cin2 + Ctrace2) ]/[ (C1 + Cin1 + Ctrace1 + C2 + Cin2 + Ctrace2)] + Cparasitic
Table 93. LAN Interface
ICH3-M LAN Interface Recommendations Signal System Pull-up/Pull-down Notes
LAN_JCLK
No resistor required; If LAN interface not used, leave unconnected (NC)
LAN_RXD[2:0]
No resistor required, has integrated weak internal pull-up; If LAN interface not used, leave unconnected (NC)
LAN_TXD[2:0], LAN_RSTSYNC
See notes
Connect to LAN_TXD on Platform LAN Connect Device.
If LAN interface not used, leave unconnected (NC).
202
Design Guide

ICH3-M High Speed Decoupling Recommendations Signal Configuration F Qty Notes
+VCC_CORE
Pull-down to GND
0.1 F 1.0 F, 16 V
2 1 7 1 1 3 1 2 1 12 2 8 1 2 1 1
Place close to ICH3-M VCCPCPU pins as possible.
+V1.8S
Pull-down to GND
0.1 F 22 F 100 F
Place as close as possible to the ICH3-M VCCPHL and VCCCORE Quadrants Place as close as possible to the ICH3-M VCCSUS Quadrant and one between balls C23 and B23 Place as close as possible to the ICH3-M VCCAUX Quadrant Place as close as possible to the ICH3-M VCCPPCI Quadrant Place as close as possible to the ICH3-M VCCPUSB and VCCPSUS Quadrants Place as close as possible to the ICH3-M VCCPAUX Quadrant
+V1.8Always
Pull-down to GND
0.1 F 10 F
+V1.8
Pull-down to GND
0.1 F 22 F
+V3.3S
0.1 F 22 F 0.1 F 22 F
+V3.3Always
Pull-down to GND
+V3.3
Pull-down to GND
0.1 F 4.7 F 22 F

ICH3-M Reference Voltage Dividers* Signal System Pull-up/Pull-down Notes
+V5S_ICHREF
NOTE:
Pull-up to V5S
Note
Table 96. ICH3-M Miscellaneous Signals

ICH3-M Reference Voltage Dividers* Signal System Pull-up/Pull-down Notes
SPKR
Has integrated pull-down; Integrated pull-down is only enabled at boot/reset for strapping functions, otherwise disabled
Design Guide
203
12.13.
USB Checklist
USB Resistor Recommendations Signal System Pull-up/Pull-down Series Damping Notes
Table 97.Resistor Recommendations
USB_PN[5:0], USB_PP[5:0] USB_OC[5:0]

NOTE:
Place near ICH3-M Pull-up to V3.3Always 10 k Pull-up voltage rail will depend on usage
Table 98. Decoupling Recommendations

USB Decoupling Recommendations* Signal Configuration F Qty Notes
USBPWRCONN [D:A] +V5_USB[2:1]

NOTE:
Pull-down to GND
0.1 F 100 F_16V
1 ea.
Pull-down to GND
0.01 F
1 ea.
12.14.
FWH Checklist
FWH Resistor Recommendations Signal System Pull-up/Pull-down Series Damping Notes
Table 99. Resistor Recommendations
FGPI[4:0]
Configuration different depending on implementation. Terminate to GND with 10 k resistor if not used.
INIT# IC
Pull-up to V3_3S Pull-down to GND
See note 10 k
Configuration depends on FWH implementation
204
Design Guide
12.15.
LAN/HomePNA Checklist
LAN Resistor Recommendations* Signal System Pull-up/Pull-down Series Damping Notes
Table 100. LAN Resistor Recommendations
RBIAS100 RBIAS10 TDP, TDN RDP, RDN RJ45_7, RJ45_4 RJ45_SPDLED#, RJ45_ACTLED# ISOL_TCK, ISO_TI, ISOL_EX, TESTEN
619 +/-1% 549 +/-1% 100 +/-1% 124 +/-1% Crossover resistor Crossover resistor
Pull-down
75 +/-1% 470
Pull-up to V3.3
10 k
12.16.
EEPROM Interface
Table 101. EEPROM Interface Recommendation
EE_DOUT
Prototype Boards should include a placeholder for a pull-down resistor* on this signal line, but do not populate the resistor. Connect to EE_DIN of EEPROM or CNR Connector.
ICH3-M contains integrated pull-up resistor for this Signal. Connected to EEPROM data input signal (Input from EEPROM perspective and output from ICH3-M perspective.)
EE_DIN
No extra circuitry required. Connect to EE_DOUT of EEPROM or CNR Connector.
ICH3-M contains integrated pull-up resistor for this Signal. Connected to EEPROM data output signal. (Output from EEPROM perspective and input from ICH3-M perspective.)
NOTE:
* If resistor is stuffed the value is 1 Kohm 5%
Design Guide
205
12.17.
Interrupt Interface
Table 102. Interrupt Interface Recommendation
PIRQ[D:A]#
These signals require a pull-up resistor. Recommend a 2.7 K pull-up resistor to VCCVCC5 or 8.2 K to VCCCC3_.3.
In Non-APIC Mode the PIRQx# signals can be routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as described in the Interrupt Steering section. Each PIRQx# line has a separate Route Control Register. In Non-APIC Mode the PIRQx# signals can be routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as described in the Interrupt Steering section. Each PIRQx# line has a separate Route Control Register. Open drain signal
PIRQ[H:E]#/GPIO[5 :2]
These signals require a pull-up resistor. Recommend a 2.7 K pull-up resistor to VCCVCC5 or 8.2 K to VCCCC3_.3.
SERIRQ
External weak (8.2 K) pull-up resistor to VCCCC3_.3 is recommended.
206
Design Guide
12.18.
GPIO
Checklist Items Recommendations GPIO[7, 5:0]: These balls are in the Main Power Well. Pullups must use the VCC3_3 plane. Unused core well inputs must be pulled up to VCC3_3. GPIO[1:0] can be used as REQ[B:A]#. GPIO[1] can be used as PCI REQ[5]#. GPIO[5:2] can be used as PIRQ[H:E]#. These signals are 5V tolerant GPIO[8] & [13:11]: These balls are in the Resume Power Well. Pull-ups go to VCCSus3_3 plane. Unused resume well inputs must be pulled up to VCCSus3_3. These are the only GPIs that can be used as ACPI compliant wake events. These signals are not 5V tolerant. GPIO[11] can be used as SMBALERT#. GPIO[24:16]: Reason/Impact Ensure ALL unconnected signals are OUTPUTS ONLY!
Table 103. GPIO Recommendation
GPIO Balls
These are the only GPI signals in the resume well with associated status bits in the GPE1_STS register.
Fixed as output only. Can be left NC. In Main Power Well (VCC3_3). GPIO[22] is open drain. GPIO[17:16] can be used as GNT[B:A]#. GPIO[17] can be used as PCI GNT[5]#. GPIO[18] / STP_PCI# GPIO[19] / SLP_S1# GPIO[20] / STP_CPU# GPIO[21] can be used as C3_STAT# GPIO[22] / CPUPERF# GPIO[23] / SSMUXSEL
Main power well GPIO are 5 V tolerant, except for GPIO[43:32]. Resume power well GPIOs are not 5 V tolerant. Muxed pins with Power Management functionality are used for their respective power management functions
GPIO[28,27,25,24]: I/O balls. Default as outputs. Can be left NC. GPIO[24]/CLKRUN# From resume power well (VCCSus3_3). GPIO[24] / CLKRUN# (Note: use pull-up to VCC3_3 if this signal is pulled-up) GPIO[43:32]: I/O balls. From main power well (VCC3_3). Default as outputs when enabled as GPIOs.
Design Guide
207
12.19.
CPU Signals
Signal Group Recommendation Reason
Table 104. CPU Signals
FERR#,IERR#,PROCHOT#, *THRMTRIP#
**Translation circuit is required between CPU and ICH3 Pullup at Rtt_CPU=56_5% Pullup at Vcc_Rcvr=300_5%
Voltage translation
LINT1/INTR, LINT0/NMI, DPSLP#, SLP#, STPCLK#, IGNNE#, SMI#, A20M#, CPUPERF# PWRGOOD INIT#
Pullup 200 Ohm_5% to Vtt_CPU
VCC_CORE<1.3 V
Pullup 300 Ohm_5% to Vtt_CPU **Translation circuit is required between ICH3 and FWH Pullup at Rtt_CPU=200_5% Rtt_FWH=300_5%
VCC_CORE<1.3 V
12.20.
IDE Checklist
Table 105. IDE Checklist
PDD[15:0], SDD[15:0]
No extra series termination resistors or other pull-ups/pull-downs are required.

PDD7/SDD7 does not require a 10 K pull-down resistor.
These signals have integrated series resistors.

NOTE: Simulation data indicates that the integrated series termination resistors are a nominal 33, but can range from 31 to 43 .
Refer to ATA ATAPI-4 specification. PDIOW#, PDIOR#, PDDACK#, PDA[2:0], PDCS1#, PDCS3#, SDIOW#, SDIOR#, SDDACK#, SDA[2:0], SDCS1#, SDCS3# PDREQ, SDREQ No extra series termination resistors. Pads for series resistors can be implemented should the system designer have signal integrity concerns.
These signals have integrated series resistors.

NOTE: Simulation data indicates that the integrated series termination resistors are a nominal 33 , but can range from 31 ohms to 43 .
No extra series termination resistors. No pull-down resistors needed.
These signals have integrated series resistors in the ICH3. These signals have integrated pull-down resistors in the ICH3-M.
PIORDY, SIORDY
No extra series termination resistors. Pull up to VCCVCC3.33_3 via a 4.7 K resistor. Recommend 8.2 K10 K pull-up resistors to VCCVCC3.33_3. No extra series termination resistors.
These signals have integrated series resistors in the ICH3-M.
IRQ14, IRQ15
Open drain outputs from drive.
208
Design Guide
12.21.
HomePNA - Resistor Recommendation

HomePNA Resistor Recommendations* Signal System Pull-up/Pull-down Series Damping Notes
Table 106. HomePNA - Resistor Recommendation
TX_EN, MDC, MDIO, ISOLATE, HMII/JORD XO RX_TX_P, RX_TX_N TEST_EN LEDA_L, LEDL_L PHAD4/GPSI
NOTE:
Pull-down to GND
1 k
Pull-down Pull-up Pull-down to GND Pull-up Pull-down to GND
121 1% 51.1 1% 1K 470 10 k
With crossover resistor 10 k to XI
Design Guide
209
13.
Customer Reference Board Schematics

See the following page for the customer reference board schematics.
210
Design Guide
INTEL (R) 845MP/MZ PLATFORM SCHEMATICS

4 4
CPU VR
PG 37
ITP
PG 5 CPU Thermal Sensor PG 5
MOBILE INTEL(R) PENTIUM(R) 4 PROCESSOR-M (Micro-FCPGA)

PG 3,4,5
CK-408 Clocking
PG 14
Fan Header
PG 35
PG 10
PG 10
SODIMM0
1.5V AGP SLOT

AGP PM Header
3
AGP 1.5V, 66MHz, 1\2\4x, 32b
INTEL(R) 845MP/MZ MCH-M
DDR SDRAM 2.5V, 200/266MHz, 64b (1.6/2.1 GB/s)
SODIMM1
PSB 100MHz x4, 64b (3.2GB/s)
PG 9
593 BGA
PG 6,7,8 AGPBUSY# Hub Interface 1.8V, 8b, 66MHz x4 (266MB/s) ATA 66/100
DDR VR
PG 39
PG 23,24 IDE0 IDE1
INTEL(R) ICH3-M
USB AC97
33MHz, 32b PCI
PG 26 USB5 (Docking)
PG 26 USB2
PG 26 USB4
421 BGA
PG 15,16,17 LAN CONNECT PG 18
PG 20 PG 21
5V PCI SLOT 1 5V PCI SLOT 2 5V PCI SLOT 3

PG 34 3.3V LPC, 33MHz
2
PG 25 USB0
PG 25 USB1 82562ET PG 27
PG 18 PG 19
RJ45
MDC Header
PG 24
FWH
8 Mbit PG 28
Docking Connector
Q-Switch
SIO Turner System DC/DC Connector

PG 40 Serial
1
PORT80
Suspend Timer
SMC/KBC
Hitachi H8S 2149
PS/2
PG 33
PC87393 PG 31
PG 30
PG 29
Scan KB
PS/2
PG 33
PG 30 Parallel PG 32 FIR PG 32 FDD PG 32
PG 34
PG 32
PG 33
LPC SLOT
LPC PM Headers
Title
BLOCK DIAGRAM
Project: 845MP/MZ Platform m Sheet 1
E
of
4 2
Design Guide
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SCHEMATIC ANNOTATIONS AND BOARD INFORMATION

4
Voltage Rails
+VDC +VCC_CORE +VCC_VID +V1.25 +V1.5S +V1.8ALWAYS +V1.8 +V1.8S +V2.5 +V3.3ALWAYS +V3.3 +V3.3S +V5 +V5S +V12S -V12S Primary DC system power supply (10 to 17V) Core voltage for CPU 1.2V For CPU PLL and VID circuitry DDR Termination voltage 1.5V switched power rail (off in S3-S5) 1.8V always on power rail 1.8V power rail (off in S4-S5) 1.8V switched power rail (off in S3-S5) 2.5V power rail for DDR 3.3V always on power rail 3.3V power rail (off in S4-S5) 3.3V switched power rail (off in S3-S5) 5.0V power rail (off in S4-S5) 5.0V switched power rail (off in S3-S5) 12.0V switched power rail (off in S3-S5) -12.0V switched power rail for PCI (off in S3-S5)
I C / SMB Addresses
Device Clock Generator SO-DIMM0 SO-DIMM1 Thermal Diode Smart Battery Smart Battery Charger Smart Selector LED Address 1101 001x 1010 0000 1010 0001 1001 110x 0001 011x 0001 001x 0001 010x Hex D2 A0 A2 9C 16 12 14 Bus SMB_ICH SMB_ICH SMB_ICH SMB_THRM SMB_SB SMB_SB SMB_SB Page
Net Name Suffix

# = Active Low signal
Ref
Primary IDE.................................24.................................DS27 Secondary IDE...............................24.................................DS24 SMC/KBC NUMLOCK.............................29.................................DS2 SMC/KBC SCROLL LOCK.........................29.................................DS1 SMC/KBC CAPS LOCK...........................29.................................DS3 SMC/KBC INIT CLOCK..........................24.................................DS26
SW
Page
Ref
3
ON/OFF......................................40.................................SW5 LID.........................................29.................................SW3 DIP SWITCH..................................36.................................SW4 RESET.......................................40.................................SW6 VIRTUAL BATTERY.............................29.................................SW2
PCI Devices
Device Slot 1 Slot 2 Slot 3 Docking AGP LAN USB Hub to PCI LPC bridge/IDE/AC97/SMBus IDSEL # AD25 AD26 AD27 AD28 (AD17 internal) (AD24 internal) AD29 AD30 AD31 REQ/GNT # 1 1 2 2 3 3 4 Interrupts A, B, C, D B, C, D, A C, D, A, B E, F, G, H B, C, D, A A, B PC/PCI A A A
Default Jumper Settings

B
Page
DDR Termination:
Address/Command DATA Control MA, BS#, RAS#, CAS#, WE# DQS, DATA, CB CKE, CS# 1 Series and 1 Parallel 1 Series and 1 Parallel 1 Series and 1 Parallel
J2 J8 J11 J12 J21 J22 J27 J38 J49 J51 J75 J81
1-X 1-X 1-2 1-2 2-3 1-X 1-X 2-3 1-2 1-2 1-X 2-3
KBC 60/64 DECODE DISABLE INIT CLK DISABLE KSC DISABLE LAN PHYCLK Disable WMT-N/Northwood Select KSC Programming KSC Programming WMT-N/Northwood Select SIO Disable CPU VR Phase num Select CMOS CLEAR AGP Reset Default
As seen from top
29 30 29 27 36 29 29 36 31 37 16 9
Power States
SIGNAL STATE Full ON S1 (Power On Suspend)
1
PCB Footprints SOT-23

SLP_S1# HIGH LOW LOW LOW LOW SLP_S3# HIGH HIGH LOW LOW LOW SLP_S5# +V3ALWAYS HIGH HIGH HIGH LOW LOW ON ON ON ON ON +V* ON ON ON OFF OFF +V*S ON ON OFF OFF OFF Clocks
SOT23-5 2 1 2 1 3 4
1
ON
3
LOW LOW OFF OFF
S3 (Suspend to RAM) S4 (Suspend To Disk) S5 / Soft OFF
Title
Notes and Annotations

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U18B H_A#16 H_A#15 H_A#14 H_A#13 H_A#12 H_A#11 H_A#10 H_A#9 H_A#8 H_A#7 H_A#6 H_A#5 H_A#4 H_A#3 H_REQ#4 H_REQ#3 H_REQ#2 H_REQ#1 H_REQ#0 N5 N4 N2 M1 N1 M4 M3 L2 M6 L3 K1 L6 K4 K2 L5 H3 J3 J4 K5 J1 AB1 Y1 W2 V3 U4 T5 W1 R6 V2 T4 U3 P6 U1 T2 R3 P4 P3 R2 T1 R5 A16# A15# A14# A13# A12# A11# A10# A9# A8# A7# A6# A5# A4# A3# ADSTB0# REQ4# REQ3# REQ2# REQ1# REQ0# A35# A34# A33# A32# A31# A30# A29# A28# A27# A26# A25# A24# A23# A22# A21# A20# A19# A18# A17# ADSTB1# ADS# AP0# AP1# BINIT# BNR# BPRI# DP3# DP2# DP1# DP0# DEFER# DRDY# DBSY# BR3# BR2# BR1# BR0# IERR# INIT# LOCK# MCERR# RESET# RS2# RS1# RS0# RSP# TRDY# HIT# HITM# G1 AC1 V5 AA3 G2 D2 L25 K26 K25 J26 E2 H2 H5 U6 W4 Y3 H6 AC3 W5 G4 V6 AB25 F4 G5 F1 AB2 J6 F3 E3 H_ADS# 7 7 H_D#[63:0] U18A H_BNR# 7 H_BPRI# 7 H_D#15 D25 H_D#14 J21 H_D#13 D23 H_D#12 C26 H_D#11 H21 H_D#10 G22 H_D#9 B25 H_D#8 C24 H_D#7 C23 H_D#6 B24 H_D#5 D22 H_D#4 C21 H_D#3 A25 H_D#2 A23 H_D#1 B22 H_D#0 B21 E21 E22 F21 H_D#31 H25 H_D#30 K23 H_D#29 J24 H_D#28 L22 H_D#27 M21 H_D#26 H24 H_D#25 G26 H_D#24 L21 H_D#23 D26 H_D#22 F26 H_D#21 E25 H_D#20 F24 H_D#19 F23 H_D#18 G23 H_D#17 E24 H_D#16 H22 G25 H_DINV#1 K22 H_DSTBN#1 J23 H_DSTBP#1 D15# D14# D13# D12# D11# D10# D9# D8# D7# D6# D5# D4# D3# D2# D1# D0# DINV0# STBN0# STBP0# D31# D30# D29# D28# D27# D26# D25# D24# D23# D22# D21# D20# D19# D18# D17# D16# DINV1# STBN1# STBP1# D47# D46# D45# D44# D43# D42# D41# D40# D39# D38# D37# D36# D35# D34# D33# D32# DINV2# STBN2# STBP2# D63# D62# D61# D60# D59# D58# D57# D56# D55# D54# D53# D52# D51# D50# D49# D48# DINV3# STBN3# STBP3# T23 T22 T25 T26 R24 R25 P24 R21 N25 N26 M26 N23 M24 P21 N22 M23 P26 R22 P23 H_D#47 H_D#46 H_D#45 H_D#44 H_D#43 H_D#42 H_D#41 H_D#40 H_D#39 H_D#38 H_D#37 H_D#36 H_D#35 H_D#34 H_D#33 H_D#32 H_DINV#2 7 H_DSTBN#2 7 H_DSTBP#2 7
DATA GRP 2
ADDR GROUP 0
DATA GRP 0
7 7
H_A#[31:3] H_ADSTB#0
H_DEFER# 7 H_DRDY# 7 H_DBSY# 7 H_BR3# H_BR2# H_BR1# 2 4 3
4,5,7,15,17,36,37,38 +VCC_CORE +VCC_CORE_MCH 56 56 56 +VCC_CORE 8
7,8
7 RP14B 5 RP14D 6 RP14C
R361 220 H_BR0# 7 4,5,7,15,17,36,37,38
CONTROL
H_REQ#[4:0]
7 H_DINV#0 7 H_DSTBN#0 7 H_DSTBP#0
H_IERR_PU#
H_A#31 H_A#30 H_A#29 H_A#28 H_A#27 H_A#26 H_A#25 H_A#24 H_A#23 H_A#22 H_A#21 H_A#20 H_A#19 H_A#18 H_A#17 7 14 CLK_CPU_BCLK H_ADSTB#1
1 RP14A 56 15,34
H_INIT#
DATA GRP 3
H_LOCK# 7
H_RS#2 H_RS#1 H_RS#0
H_CPURST# 4,5,7
H_RS#[2:0] 7 H_TRDY# 7 H_HIT# 7 H_HITM# 7
7 7 7
AA24 H_D#63 AA22 H_D#62 AA25 H_D#61 Y21 H_D#60 Y24 H_D#59 Y23 H_D#58 W25 H_D#57 Y26 H_D#56 W26 H_D#55 V24 H_D#54 V22 H_D#53 U21 H_D#52 V25 H_D#51 U23 H_D#50 U24 H_D#49 U26 H_D#48 V21 H_DINV#3 7 W22 H_DSTBN#3 7 W23 H_DSTBP#3 7
ADDR GROUP 1
Northwood-Processor-MobilSkt_Rev1.02
DATA GRP 1
R444 54.9_1% 14 CLK_CPU_BCLK# R445 54.9_1% 14 CLK_ITP_CPU NO_STUFF_54.9_1% R446 14 CLK_ITP_CPU# NO_STUFF_54.9_1% R447 15,34 H_A20M# 15 H_FERR_S# 15,34 H_IGNNE# H_INTR H_NMI H_SMI# H_STPCLK# H_VID4 H_VID3 H_VID2 H_VID1 H_VID0 U18C AF22 AF23 AC26 AD26 C6 B6 B2 D1 E5 B5 Y4 AE1 AE2 AE3 AE4 AE5 AF3 AD20 A5 AE23 AD22 A4 AF4 AD3 AF25 B3 C4 A2 AD2 AF24 AE21 A22 A7 BCLK0 BCLK1 ITP_CLK0 ITP_CLK1 A20M# FERR# IGNNE# LINT0 LINT1 SMI# STPCLK# VID4 VID3 VID2 VID1 VID0 RSVD3 VCCA VCCSENSE VCCIOPLL VSSA VSSSENSE VCCVID RSVD2 RSVD5 THRMDA THRMDC THRMTRIP# RSVD1 RSVD4 RSVD_PID RSVD0 RSVD_SMI2#
FSBSEL0 FSBSEL1 GHI# COMP0 COMP1
AD6 AD5 A6 L24 H_COMP0 P1 H_COMP1 AB4 AA5 Y6 AC4 AB5 AC6
H_BSEL0 14 H_BSEL1 14 PM_CPUPERF# 16,34 R356 R101 51.1_1% 51.1_1%
HOST CLK LEGACY CPU
5,36 +VCC_VID L2 1 4.7UH
36
15,34 15,34 15,34 15,34 H_VID[4:0]
BPM5# BPM4# BPM3# BPM2# BPM1# BPM0# BYPASSEN# DBRESET DPSLP# GTLREF3 GTLREF2 GTLREF1 GTLREF0 ODT MCLK0 MCLK1 MCLK2 MCLK3 MCLKIO0 MCLKIO1 PWRGOOD PROCHOT# SLP# TCK TDI TDO TMS TRST#
H_BPM5_PREQ# 5 H_BPM4_PRDY# 5 H_BPM1_ITP# 5 H_BPM0_ITP# 5 +VCC_CORE 4,5,7,15,17,36,37,38
56 4,5,7,15,17,36,37,38 +VCC_CORE RP11A AD24H_BYPASSEN# 1 8 AE25 MASTER_RESET# 5,36,40 AD25 H_DPSLP# 15,34 AA6 F6 AA21 F20 H_ODT AA2 AC21 H_MCLK0 AC20 H_MCLK1 AC24 H_MCLK2 AC23 H_MCLK3 AA20 H_MCLKIO0 AB22 H_MCLKIO1 AB23 C3 AB26 D4 C1 D5 F7 E6 R21 680 2 3 4 1 2
R359 49.9_1% +VCC_CORE 1 R355 100_1% 2 C444 1UF C451 220PF C476 200 R334 200 R335 200 R115 200 R106 200 R107 200 R112 200 R109 220PF 200 R118 R98 R94 1 1 1 1 1 1 1 1 1 1 4,5,7,15,17,36,37,38
H_GTLREF_1
2 C78 33uF H_VCCA L4 C99 33uF 5,36
4,5,7,15,17,36,37,38 7 6 5 8 7 RP11B RP11C RP11D RP10A RP10B R478 R479 56 56 56 56 56 1K 1K
+VCC_CORE
1 4.7UH
H_VCCIOPLL TP1 H_VSSA +VCC_VID TP2
MISC
200
R337 300 H_PWRGD 15,34
5 H_THERMDA 5 H_THERMDC 5 H_THRMTRIP_S#

1
H_PROCHOT_S# 5 H_CPUSLP# 15,34 H_TCK H_TDI H_TDO H_TMS H_TRST# 5 5 5 5 5
16,34 PM_CPUPERF# 15,34 H_A20M# 15,34 H_IGNNE# 15,34 H_INTR 15,34 H_NMI 15,34 H_SMI# 15,34 H_STPCLK# 15,34 H_DPSLP# 15,34 H_CPUSLP# 15,34 H_INIT#
200 2
Title
CPU 1 of 2
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Design Guide
213
A B
3,5,7,15,17,36,37,38 +VCC_CORE VCC85 AF2
A B
VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58 VCC59 VCC60 VCC61 VCC62 VCC63 VCC64 VCC65 VCC66 VCC67 VCC68 VCC69 VCC70 VCC71 VCC72 VCC73 VCC74 VCC75 VCC76 VCC77 VCC78 VCC79 VCC80 VCC81 VCC82 VCC83 VCC84
A10 A12 A14 A16 A18 A20 A8 AA10 AA12 AA14 AA16 AA18 AA8 AB11 AB13 AB15 AB17 AB19 AB7 AB9 AC10 AC12 AC14 AC16 AC18 AC8 AD11 AD13 AD15 AD17 AD19 AD7 AD9 AE10 AE12 AE14 AE16 AE18 AE20 AE6 AE8 AF11 AF13 AF15 AF17 AF19 AF21 AF5 AF7 AF9 B11 B13 B15 B17 B19 B7 B9 C10 C12 C14 C16 C18 C20 C8 D11 D13 D15 D17 D19 D7 D9 E10 E12 E14 E16 E18 E20 E8 F11 F13 F15 F17 F19 F9
Design Guide
Title Project:
CPU 1 of 2 / MCH POWER ON CONFIGURATION
845MP/MZ Platform m Sheet 4

E
of 4 2
H1 VSS1 H4 VSS2 H23 VSS3 H26 VSS4 A11 VSS5 A13 VSS6 A15 VSS7 A17 VSS8 A19 VSS9 A21 VSS10 A24 VSS11 A26 VSS12 A3 VSS13 A9 VSS14 AA1 VSS15 AA11 VSS16 AA13 VSS17 AA15 VSS18 AA17 VSS19 AA19 VSS20 AA23 VSS21 AA26 VSS22 AA4 VSS23 AA7 VSS24 AA9 VSS25 AB10 VSS26 AB12 VSS27 AB14 VSS28 AB16 VSS29 AB18 VSS30 AB20 VSS31 AB21 VSS32 AB24 VSS33 AB3 VSS34 AB6 VSS35 AB8 VSS36 AC11 VSS37 AC13 VSS38 AC15 VSS39 AC17 VSS40 AC19 VSS41 AC2 VSS42 AC22 VSS43 AC25 VSS44 AC5 VSS45 AC7 VSS46 AC9 VSS47 AD1 VSS48 AD10 VSS49 AD12 VSS50 AD14 VSS51 AD16 VSS52 AD18 VSS53 AD21 VSS54 AD23 VSS55 AD4 VSS56 AD8 VSS57 AE11 VSS58 AE13 VSS59 AE15 VSS60 AE17 VSS61 AE19 VSS62 AE22 VSS63 AE24 VSS64 AE26 VSS65 AE7 VSS66 AE9 VSS67 AF1 VSS68 AF10 VSS69 AF12 VSS70 AF14 VSS71 AF16 VSS72 AF18 VSS73 AF20 VSS74 AF26 VSS75 AF6 VSS76 AF8 VSS77 B10 VSS78 B12 VSS79 B14 VSS80 B16 VSS81 B18 VSS82 B20 VSS83 B23 VSS84 B26 VSS85 B4 VSS86 B8 VSS87 C11 VSS88 C13 VSS89 C15 VSS90 C17 VSS91 C19 VSS92 C2 VSS93 C22 VSS94 C25 VSS95 C5 VSS96 C7 VSS97 C9 VSS98 D10 VSS99 D12 VSS100 D14 VSS101 D16 VSS102 D18 VSS103 D20 VSS104 D21 VSS105 D24 VSS106 D3 VSS107 D6 VSS108 D8 VSS109 E1 VSS110 E11 VSS111 E13 VSS112 E15 VSS113 E17 VSS114 E19 VSS115 E23 VSS116 E26 VSS117 E4 VSS118 E7 VSS119 E9 VSS120 F10 VSS121 F12 VSS122 F14 VSS123 F16 VSS124 F18 VSS125 F2 VSS126 F22 VSS127 F25 VSS128 F5 VSS129 F8 VSS130 G21 VSS131 G24 VSS132 G3 VSS133 G6 VSS134 J2 VSS135 J22 VSS136 J25 VSS137 J5 VSS138 K21 VSS139 K24 VSS140 K3 VSS141 K6 VSS142 L1 VSS143 L23 VSS144 L26 VSS145 L4 VSS146 M2 VSS147 M22 VSS148 M25 VSS149 M5 VSS150 N21 VSS151 N24 VSS152 N3 VSS153 N6 VSS154 P2 VSS155 P22 VSS156 P25 VSS157 P5 VSS158 R1 VSS159 R23 VSS160 R26 VSS161 R4 VSS162 T21 VSS163 T24 VSS164 T3 VSS165 T6 VSS166 U2 VSS167 U22 VSS168 U25 VSS169 U5 VSS170 V1 VSS171 V23 VSS172 V26 VSS173 V4 VSS174 W21 VSS175 W24 VSS176 W3 VSS177 W6 VSS178 Y2 VSS179 Y22 VSS180 Y25 VSS181 Y5 VSS182 U18D
214
CPU Thermal Sensor

4,6,9,10,14,17,19,23,28,29,30,31,32,33,36,37,40 +V3.3S 4,6,9,10,14,17,19,23,28,29,30,31,32,33,36,37,40 C56 0.1UF
4
+V3.3S
R46 1K
R60 1K U12 R246
R463 1K NO_STUFF_1K 2 3 4 10 6 VCC DXP DXN ADD0 ADD1 STBY# SMBDATA SMBCLK ALERT# NC1 NC2 NC3 NC4 NC5 15 12 14 11 1 5 9 13 16 R464
H_THERMDA C425 2200PF
Address Select Straps Current Address: 1001 110x
RP5A 10K
RP5B 10K
RP5C 10K
THRM_ALERT# 15,16,17,18,19,20,22,34 +V3.3S_ICH R61 3,4,7,15,17,36,37,38 R273 +VCC_CORE NO_STUFF_470 3 R66 56 5 6 R274 2 NO_STUFF_470 CR10A NO_STUFF_3904 36 VCC_VIDPWRGD
SMB_THRM_DATA 29,34 SMB_THRM_CLK 29,34
H_THERMDC R192 0 7 8 R91 NO_STUFF_0 J3 NO_STUFF_3Pin_Recepticle 2 THERMDP 1 THERMDN R155 NO_STUFF_0 GND1 GND2 ADM1023
PM_THRM# 16,29,34 R261 NO_STUFF_1K H_PROCHOT# 0 R262 NO_STUFF_0 Note: Stuff resistors for SMB_THRM_DATA and SMB_THRM_CLK as default for normal operation.
Layout Note: Route H_THERMDA and H_THERMDC on same layer. 10 mil trace 5 mill between on a 12 mil spacing
3 H_PROCHOT_S#
4 CR10B NO_STUFF_3904 1
4,6,9,10,14,17,19,23,28,29,30,31,32,33,36,37,40 +V3.3S
3
GND0 GND2 3 4 5 6 GND1 GND3 R71 10K R74 10K R473 10K U44 3,36 +VCC_VID R469 56 3 3 H_THRMTRIP_S# 1 Q42 2N3904 2 R73 10K 4 3 2 1 10 11 12 13 1PRE_L 1CLK 1D 1CLR 2PRE_L 2CLK 2D 2CLR 74HC74A 7 14
C648 0.1UF
R99 10K
Note: Stuff R463, R246, and R192 as Default Stuff R464, R91, and R155 and disable the KSC to use Tj Pro Connector
VCC5
Tj Pro Connector
1Q 1Q_L
5 6 9 8
H_THRMTRIP# 36
GND
2Q 2Q_L
3,4,7,15,17,36,37,38
+VCC_CORE
Place close to ITP
In-Target Probe
+V3.3S 4,6,9,10,14,17,19,23,28,29,30,31,32,33,36,37,40
Place close to CPU
R318 R319 R320 R321 51 51 51 51
R339 R340 R341 R342 51 51 51 51
R18 75
R35 51
R22 1.5K_1% J15 23 13 11 9 7 5 3
C65 10UF C62 0.1UF C58 0.1UF R20 10K R30 10K R23 39 R343 150
3 H_BPM5_PREQ# 3 H_BPM4_PRDY# 3 H_BPM1_ITP# 3 H_BPM0_ITP#
BPM5DR# BPM5# BPM4# BPM3# BPM2# BPM1# BPM0# STTDO STPWR BCK BCK# FBO FBI RST#
TCK TDI TMS TRST
16 10 12 14
H_TCK 3 H_TDI 3 H_TMS 3 H_TRST# 3
Place 54.9 Ohm 1% Resistors near ITP
R442 54.9_1% 14 CLK_ITP 14 CLK_ITP# R443 54.9_1%
3 H_TDO
24 22 19 21
DBR DBA
6 4 1
H_DBA#
R29
MASTER_RESET# 3,36,40 AGP_BUSY# 9,16

1
NO_STUFF_33 R36 27.4_1%
H_TCK
17 18 15
3,4,7 H_CPURST#
GND1 GND2 GND3 GND4 GND5
1 2 8 20 25
Title
CPU Thermal Sensor & ITP

E
2x13-HDR
A B C D
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Design Guide
215
M_A_FR_[12:0]
9 AGP_AD[31:0] 9 AGP_CBE#[3:0] 10,11
M_A_FR_12 M_A_FR_11 M_A_FR_10 M_A_FR_9 M_A_FR_8 M_A_FR_7 M_A_FR_6 M_A_FR_5 M_A_FR_4 M_A_FR_3 M_A_FR_2 M_A_FR_1 M_A_FR_0
Correct BD IPN is: A56859-008
Correct BD (MZ) IPN is: A83134-001
845MP/MZ 1 of 3
SMA0/CS#11 SMA1/CS#10 SMA2/CS#6 SMA3/CS#9 SMA4/CS#5 SMA5/CS#8 SMA6/CS#7 SMA7/CS#4 SMA8/CS#3 SMA9/CS#0 SMA10 SMA11/CS#2 SMA12/CS#1 E12 F17 E16 G18 G19 E18 F19 G21 G20 F21 F13 E20 G22 9 9 9 9 9 9 9 9 For GRCOMP resistor value: 2/3 of board impedance. 40.2 ohm for 60 board impedance. 36.5 ohm for 55 board impedance. AGP_FRAME# AGP_DEVSEL# AGP_IRDY# AGP_TRDY# AGP_STOP# AGP_PAR AGP_REQ# AGP_GNT# 9 14 9 9 9 9 9 9 9 9 9 9 9 9 9 AGP AGP_AD0 AGP_AD1 AGP_AD2 AGP_AD3 AGP_AD4 AGP_AD5 AGP_AD6 AGP_AD7 AGP_AD8 AGP_AD9 AGP_AD10 AGP_AD11 AGP_AD12 AGP_AD13 AGP_AD14 AGP_AD15 AGP_AD16 AGP_AD17 AGP_AD18 AGP_AD19 AGP_AD20 AGP_AD21 AGP_AD22 AGP_AD23 AGP_AD24 AGP_AD25 AGP_AD26 AGP_AD27 AGP_AD28 AGP_AD29 AGP_AD30 AGP_AD31 AGP_CBE#0 AGP_CBE#1 AGP_CBE#2 AGP_CBE#3 V25 GCBE0# V23 GCBE1# Y25 GCBE2# AA23 GCBE3# U20A Brookdale-Chipset_Rev1.2 R27 GAD0 R28 GAD1 T25 GAD2 R25 GAD3 T26 GAD4 T27 GAD5 U27 GAD6 U28 GAD7 V26 GAD8 V27 GAD9 T23 GAD10 U23 GAD11 T24 GAD12 U24 GAD13 U25 GAD14 V24 GAD15 Y27 GAD16 Y26 GAD17 AA28 GAD18 AB25 GAD19 AB27 GAD20 AA27 GAD21 AB26 GAD22 Y23 GAD23 AB23 GAD24 AA24 GAD25 AA25 GAD26 AB24 GAD27 AC25 GAD28 AC24 GAD29 AC22 GAD30 AD24GAD31 AGP_VREF CLK_MCH66 AGP_ADSTB0 AGP_ADSTB0# AGP_ADSTB1 AGP_ADSTB1# AGP_SBA[7:0] AGP_SBSTB AGP_SBSTB# AGP_RBF# AGP_WBF# AGP_PIPE# AGP_ST0 AGP_ST1 AGP_ST2 R102 40.2_1% GRCOMP Y24 GFRAME# W28 GDEVSEL# W27 GIRDY# W24 GTRDY W23 GSTOP# W25 GPAR AG24GREQ# AH25GGNT# AD25PRCOMP AA21 AGPREF P22 GCLKIN R24 AD_STB0 R23 AD_STB#0 AC27 AD_STB1 AC28AD_STB#1 MEMORY 11 11 AGP_SBA0 AGP_SBA1 AGP_SBA2 AGP_SBA3 AGP_SBA4 AGP_SBA5 AGP_SBA6 AGP_SBA7 AH28SBA0 AH27SBA1 AG28SBA2 AG27SBA3 AE28 SBA4 AE27 SBA5 AE24 SBA6 AE25 SBA7 AF27 SB_STB AF26 SB_STB# AE22 RBF# AE23 WBF# AF22 PIPE# AG25ST0 AF24 ST1 AG26ST2 M_DQS[8:0] M_CB[7:0]
A B C
11 M_DATA[63:0]
B C
Design Guide
Title
D
HUB
HUB_PD0 HUB_PD1 HUB_PD2 HUB_PD3 HUB_PD4 HUB_PD5 HUB_PD6 HUB_PD7 HUB_PD8 HUB_PD9 HUB_PD10 R362 36.5_1% HUB_RCOMP
P25 P24 N27 P23 M26 M25 L28 L27 M27 N28 M24 N25 N24 P27 P26 7,8 +V1.8S_MCH
PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 RQM RQI PSTOP PSTRB PSTRB# HLRCOMP PREF
SDQ0 SDQ1 SDQ2 SDQ3 SDQ4 SDQ5 SDQ6 SDQ7 SDQ8 SDQ9 SDQ10 SDQ11 SDQ12 SDQ13 SDQ14 SDQ15 SDQ16 SDQ17 SDQ18 SDQ19 SDQ20 SDQ21 SDQ22 SDQ23 SDQ24 SDQ25 SDQ26 SDQ27 SDQ28 SDQ29 SDQ30 SDQ31 SDQ32 SDQ33 SDQ34 SDQ35 SDQ36 SDQ37 SDQ38 SDQ39 SDQ40 SDQ41 SDQ42 SDQ43 SDQ44 SDQ45 SDQ46 SDQ47 SDQ48 SDQ49 SDQ50 SDQ51 SDQ52 SDQ53 SDQ54 SDQ55 SDQ56 SDQ57 SDQ58 SDQ59 SDQ60 SDQ61 SDQ62 SDQ63 SDQ64/CB0 SDQ65/CB1 SDQ66/CB2 SDQ67/CB3 SDQ68/CB4 SDQ69/CB5 SDQ70/CB6 SDQ71/CB7
G28 F27 C28 E28 H25 G27 F25 B28 E27 C27 B25 C25 B27 D27 D26 E25 D24 E23 C22 E21 C24 B23 D22 B21 C21 D20 C19 D18 C20 E19 C18 E17 E13 C12 B11 C10 B13 C13 C11 D10 E10 C9 D8 E8 E11 B9 B7 C7 C6 D6 D4 B3 E6 B5 C4 E5 C3 D3 F4 F3 B2 C2 E2 G5 C16 D16 B15 C14 B17 C17 C15 D14
M_DATA0 M_DATA1 M_DATA2 M_DATA3 M_DATA4 M_DATA5 M_DATA6 M_DATA7 M_DATA8 M_DATA9 M_DATA10 M_DATA11 M_DATA12 M_DATA13 M_DATA14 M_DATA15 M_DATA16 M_DATA17 M_DATA18 M_DATA19 M_DATA20 M_DATA21 M_DATA22 M_DATA23 M_DATA24 M_DATA25 M_DATA26 M_DATA27 M_DATA28 M_DATA29 M_DATA30 M_DATA31 M_DATA32 M_DATA33 M_DATA34 M_DATA35 M_DATA36 M_DATA37 M_DATA38 M_DATA39 M_DATA40 M_DATA41 M_DATA42 M_DATA43 M_DATA44 M_DATA45 M_DATA46 M_DATA47 M_DATA48 M_DATA49 M_DATA50 M_DATA51 M_DATA52 M_DATA53 M_DATA54 M_DATA55 M_DATA56 M_DATA57 M_DATA58 M_DATA59 M_DATA60 M_DATA61 M_DATA62 M_DATA63 M_CB0 M_CB1 M_CB2 M_CB3 M_CB4 M_CB5 M_CB6 M_CB7
J27 RSTIN# H27 SSI_ST H26 TESTIN#
SDQS0 SDQS1 SDQS2 SDQS3 SDQS4 SDQS5 SDQS6 SDQS7 SDQS8
F26 C26 C23 B19 D12 C8 C5 E3 E15
M_DQS0 M_DQS1 M_DQS2 M_DQS3 M_DQS4 M_DQS5 M_DQS6 M_DQS7 M_DQS8
Project: 845MP/MZ Platform m Sheet

E
SWE# SCAS# SRAS# MEMORY
MCH-M (1 of 3)
M_RCOMP Make 1" long M_RCVIN# M_CS3_R# M_CS2_R# M_CS1_R# M_CS0_R# HUB_PD[10:0] 8,15 R370 30.1_1% 10,12 10,12 10,12 10,12 M_BS1_FR# 10,11 M_BS0_FR# 10,11 M_CKE3_R# 10,12 M_CKE2_R# 10,12 M_CKE1_R# 10,12 M_CKE0_R# 10,12 MCH_TEST# 8 SSI_ST 4 HUB_VREF_MCH 8 HUB_PSTRB# 8,15 HUB_PSTRB 8,15 +V1.25 12,13,39 R433 56 C192 0.1UF C634 100PF 4,5,9,10,14,17,19,23,28,29,30,31,32,33,36,37,40 +V3.3S
G23 E22 H23 F23 J23 K23 G12 G13 E9 F7 F9 E7 G9 G10 J28 G3 H3
SCKE0 SCKE1 SCKE2 SCKE3 SCKE4 SCKE5 SBS0 SBS1 SCS#0 SCS#1 SCS#2 SCS#3 SCS#4 SCS#5 SMRCOMP RCVENIN# RCVENOUT#
G11 G8 F11 SCK0/CLK0 SCK#0/CLK1 SCK1/CLK2 SCK#1/CLK3 SCK2/CLK4 SCK#2/CLK5 SCK3 SCK#3 SCK4 SCK#4 SCK5 SCK#5 SCK6/CLK6 SCK#6/CLK7 SCK7/CLK10 SCK#7/CLK11 SCK8/CLK9 SCK#8/CLK8 SDREF0 SDREF1 E14 F15 J24 G25 G6 G7 G15 G14 E24 G24 H5 F5 K25 J25 G17 G16 H7 H6 J21 J9
M_CLK_DDR0 M_CLK_DDR0# M_CLK_DDR1 M_CLK_DDR1# M_CLK_DDR2 M_CLK_DDR2#
M_WE_FR# 10,11 M_CAS_FR# 10,11 M_RAS_FR# 10,11
M_CLK_DDR3 10 M_CLK_DDR3# 10 M_CLK_DDR4 10 M_CLK_DDR4# 10 M_CLK_DDR5 10 M_CLK_DDR5# 10
6 of 4 2
1
10 10 10 10 10 10
AD26NC0 AD27 NC1
C483 0.1UF
R363 0
PCI_RST_MCH# 15
SM_VREF 10,39
216
+V1.5S 8
9,36,40 H_D#[63:0] 3 R113 2 1 R22 R29 U22 U26 W22 W29 AA22 AA26 AB21 AC29 AD21 AD23 AE26 AF23 AG29 AJ25 N14 N16 P13 P15 P17 R14 R16 T15 U14 U16 L29 N26 L25 M22 N23 +V1.5S_MCH U20B VCCAGP0 VCCAGP1 VCCAGP2 VCCAGP3 VCCAGP4 VCCAGP5 VCCAGP6 VCCAGP7 VCCAGP8 VCCAGP9 VCCAGP10 VCCAGP11 VCCAGP12 VCCAGP13 VCCAGP14 VCCAGP15 VCCCORE0 VCCCORE1 VCCCORE2 VCCCORE3 VCCCORE4 VCCCORE5 VCCCORE6 VCCCORE7 VCCCORE8 VCCCORE9 VCCHL1 VCCHL2 VCCHL3 VCCHL4 VCCHL5 Brookdale-Chipset_Rev1.2 ADS# V3 HTRDY# U7 DRDY# V4 DEFER# Y4 HITM# Y3 HIT# Y5 HLOCK# W5 BREQ#0 V7 BNR# W3 BPRI# Y7 DBSY# V5 RS#0 W2 RS#1 W7 RS#2 W6 VTTFSB1 VTTFSB2 VTTFSB3 VTTFSB4 VTTFSB5 VTTFSB6 VTTFSB7 VTTFSB8 VTTFSB9 VTTFSB10 VTTFSB11 VTTFSB12 VTTFSB13 VTTFSB14 VTTFSB15 VTTFSB16 VTTFSB17 VTTFSB18 VTTFSB19 VCCSM1 VCCSM2 VCCSM3 VCCSM4 VCCSM5 VCCSM6 VCCSM7 VCCSM8 VCCSM9 VCCSM10 VCCSM11 VCCSM12 VCCSM13 VCCSM14 VCCSM15 VCCSM16 VCCSM17 VCCSM18 VCCSM19 VCCSM20 VCCSM21 VCCSM22 VCCSM23 VCCSM24 VCCSM25 VCCSM26 VCCSM27 VCCSM28 VCCSM29 VCCSM30 VCCSM31 VCCSM32 VCCSM33 VCCSM34 VCCSM35 VCCSM36 VCCSM37 VCCSM38 M8 U8 AA9 AB8 AB18 AB20 AC19 AD18 AD20 AE19 AE21 AF18 AF20 AG19 AG21 AG23 AJ19 AJ21 AJ23 A5 A9 A13 A17 A21 A25 C1 C29 D7 D11 D15 D19 D23 D25 F6 F10 F14 F18 F22 G1 G4 G29 H8 H10 H12 H14 H16 H18 H20 H22 H24 K22 K24 K26 L23 K6 J5 J7 3 H_A#[31:3] H_ADS# 3 H_TRDY# 3 H_DRDY# 3 H_DEFER# 3 H_HITM# 3 H_HIT# 3 H_LOCK# 3 H_BR0# 3 H_BNR# 3 H_BPRI# 3 H_DBSY# 3 H_RS#0 H_RS#1 H_RS#2 H_RS#[2:0] 3 U20C H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 3 3 H_ADSTB#0 H_ADSTB#1 T4 T5 T3 U3 R3 P7 R2 P4 R6 P5 P3 N2 N7 N3 K4 M4 M3 L3 L5 K3 J2 M5 J3 L2 H4 N5 G2 M6 L7 U6 T7 R7 U5 U2 R5 N6 K8 J8 AC13 AD13 AC2 AA7 3 3 3 3 3 3 3 3 3 3 3 3 H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 AD4 AE6 AE11 AC15 AD3 AE7 AD11 AC16 AD5 AG4 AH9 AD15 AE17 M7 R8 Y8 AB11 AB17 HA#3 HA#4 HA#5 HA#6 HA#7 HA#8 HA#9 HA#10 HA#11 HA#12 HA#13 HA#14 HA#15 HA#16 HA#17 HA#18 HA#19 HA#20 HA#21 HA#22 HA#23 HA#24 HA#25 HA#26 HA#27 HA#28 HA#29 HA#30 HA#31 HREQ#0 HREQ#1 HREQ#2 HREQ#3 HREQ#4 HADSTB#0 HADSTB#1 HCLKINN HCLKINP HYRCOMP HYSWNG HXRCOMP HXSWNG HDSTBN#0 HDSTBN#1 HDSTBN#2 HDSTBN#3 HDSTBP#0 HDSTBP#1 HDSTBP#2 HDSTBP#3 DINV#0 DINV#1 DINV#2 DINV#3 CPURST# HVREF0 HVREF1 HVREF2 HVREF3 HVREF4 Brookdale-Chipset_Rev1.2 HD#0 AA2 HD#1 AB5 HD#2 AA5 HD#3 AB3 HD#4 AB4 HD#5 AC5 HD#6 AA3 HD#7 AA6 HD#8 AE3 HD#9 AB7 HD#10 AD7 HD#11 AC7 HD#12 AC6 HD#13 AC3 HD#14 AC8 HD#15 AE2 HD#16 AG5 HD#17 AG2 HD#18 AE8 HD#19 AF6 HD#20 AH2 HD#21 AF3 HD#22 AG3 HD#23 AE5 HD#24 AH7 HD#25 AH3 HD#26 AF4 HD#27 AG8 HD#28 AG7 HD#29 AG6 HD#30 AF8 HD#31 AH5 HD#32 AC11 HD#33 AC12 HD#34 AE9 HD#35 AC9 HD#36 AE10 HD#37 AD9 HD#38 AG9 HD#39 AC10 HD#40 AE12 HD#41 AF10 HD#42 AG11 HD#43 AG10 HD#44 AH11 HD#45 AG12 HD#46 AE13 HD#47 AF12 HD#48 AG13 HD#49 AH13 HD#50 AC14 HD#51 AF14 HD#52 AG14 HD#53 AE14 HD#54 AG15 HD#55 AG16 HD#56 AG17 HD#57 AH15 HD#58 AC17 HD#59 AF16 HD#60 AE15 HD#61 AH17 HD#62 AD17 HD#63 AE16 H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63
NO_STUFF_0.01_1%
4
HOST
+VCC_CORE_MCH R434 2
3,8 +VCC_CORE 1 3,4,5,15,17,36,37,38
NO_STUFF_0.01_1% R435 2 1 Place 54.9 Ohm 1% Resistors near Brookdale
HOST
+V1.8S 6,8
3
R117 2
+V1.8S_MCH 1
NO_STUFF_0.01_1%
3 H_REQ#[4:0]
NO_STUFF_0.01_1%
8,13,39,40 +V2.5
+VCC_CORE_MCH
3,8
R440 54.9_1% C440 14 CLK_MCH_BCLK# 0.01UF 14 CLK_MCH_BCLK HYRCOMP HYSWING HXRCOMP R441 54.9_1%
R346 301_1%
R347 150_1% R344 24.9_1%
R103 24.9_1%
+VCC_CORE_MCH R351 301_1%
3,8 C445 0.01UF HXSWING
+V1.5S_MCH 1 1
R349 150_1%
3,4,5 H_CPURST#
L6 4.7UH
L5 4.7UH
+VCC_CORE_MCH
3,8
HYSWING, HXSWING 12 mil trace, 10 mil space
R357 49.9_1% MCH_GTLREF C473 C462 1 R358 100_1% 1UF 2 220PF

1
T17 T13 1 + C122 - 33UF 2

1
VCCGA1 VCCHA1 VSSGA2 VSSHA2
+ C121 - 33UF U17 U13
845MP/MZ
A B
2 OF 3
C
Title
MCH-M (2 of 3)
D
7
E
of
42
Design Guide
217
14,15 CLK_ICH66
Layout:Place 0 Ohm close to "T"
J80 R142 NO_STUFF_0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 HUB_VREF_MCH 6 C20 TP_18pf1 18pF C16 TP_22pf1 TP_22pf2 22PF C18 TP_27pf2 2 27PF C19 TP_47pf1 47pF C17 TP_220pf1 TP_220pf2 220PF C14 TP_2700pf2 2700pF C15 TP_.033uf2 0.033uF C13 TP_.082uf2 0.082uF TP_47pf2 TP_18pf2
4
Test CAP's
U20D N22 K27 K5 L24 M23 K7 J26 A3 A7 A11 A15 A19 A23 A27 D5 D9 D13 D17 D21 E1 E4 E26 E29 F8 F12 F16 F20 F24 G26 H9 H11 H13 H15 H17 H19 H21 J1 J4 J6 J22 J29 L1 L4 L6 L8 L22 L26 N1 N4 N8 N13 N15 N17 N29 P6 P8 P14 P16 R1 R4 R13 R15 R17 R26 T6 T8 T14 T16 T22 U1 U4 VSS0 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70
HUB_PD0 Brookdale-Chipset_Rev1.2 HUB_PD1 U15 VSS71 VSS72 U29 HUB_PD2 V6 VSS73 VSS74 V8 HUB_PD3 V22 VSS75 VSS76 W1 HUB_PD9 W4 VSS77 VSS78 W8 W26 6,15 HUB_PSTRB VSS79 6,15 HUB_PSTRB# VSS80 Y6 VSS81 Y22 HUB_PD10 VSS82 AA1 VSS83 AA4 HUB_PD8 VSS84 AA8 VSS85 AA29 HUB_PD4 VSS86 AB6 VSS87 AB9 HUB_PD5 VSS88 AB10 HUB_PD6 VSS89 AB12 VSS90 AB13 HUB_PD7 AB14 VSS91 VSS92 AB15 AB16 VSS93 6,15 HUB_PD[10:0] VSS94 AB19 VSS95 AB22 NO_STUFF_50Pin_SKT VSS96 AC1 VSS97 AC4 VSS98 AC18 +V2.5 7,13,39,40 VSS99 AC20 VSS100 AC21 AC23 VSS101 VSS102 AC26 VSS103 AD6 C218 C191 C246 C243 C247 C209 C493 VSS104 AD8 22UF 22UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF VSS105 AD10 VSS106 AD12 AD14 VSS107 C487 C486 C198 C245 C248 C485 C484 VSS108 AD16 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF VSS109 AD19 VSS110 AD22 AE1 VSS111 C489 C488 C244 C270 C277 C260 VSS112 AE4 0.1UF 0.1UF 0.1UF 150uF 150uF 150uF VSS113 AE18 VSS114 AE20 AE29 VSS115 +VCC_CORE_MCH 3,7 VSS116 AF5 VSS117 AF7 C130 C132 C131 VSS118 AF9 C442 C441 C467 C460 VSS119 AF11 0.1UF 0.1UF 0.1UF 0.1UF 10UF 10UF 10UF VSS120 AF13 AF15 VSS121 VSS122 AF17 C458 C456 C457 C459 C474 C443 VSS123 AF19 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF VSS124 AF21 AF25 VSS125 VSS126 AG1 VSS127 AG18 +V1.5S_MCH 7 VSS128 AG20 VSS129 AG22 VSS130 AH19 + C127 C147 +V1.8S_MCH VSS131 AH21 C148 C477 VSS132 AH23 0.1UF 10UF 10UF 100uF AJ3 VSS133 VSS134 AJ5 C179 VSS135 AJ7 VSS136 AJ9 10UF C471 C481 C468 C475 C461 AJ11 VSS137 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF VSS138 AJ13 AJ15 VSS139 VSS140 AJ17 VSS141 AJ27
Test CAP's Backside

TP_BS_330pf1 +V1.8S_ICH 15,17 TP_BS_47pf1 330PF C418 TP_BS_47pf2 47pF C417 TP_BS_0.01uf2 0.01UF C421 TP_BS_0.1uf2 0.1UF C419 TP_BS_220pF2 220PF C420 TP_BS_330pf2
TP_27pf1
TP_BS_0.01uf1
TP_2700pf1
TP_BS_0.1uf1
TP_.033uf1
LAI HUBLINK
TP_BS_220pF1
TP_.082uf1
HUB INTERFACE REFERENCE

(1/2) 1.8V
+V1.8S 7,17,40 +V1.8S_MCH 6,7
2
R364 NO_STUFF_4.7K
MCH_TEST# 6
R372 301_1%
C490 NO_STUFF_470PF R371 NO_STUFF_56.2_1%
Measurement Point 2
HUB_VREF_MCH 6
J40 6,7 1 R373 301_1%
R365 0
C482 0.1UF
C478 0.1UF
C479 0.1UF
C492 0.01UF
range for R372, R373: 100 ohm - 1K
845MP/MZ
A B
3 OF 3
C
Title Project:
MCH-M (3 of 3)
845MP/MZ Platform m Sheet
D
8
E
of
42
Design Guide
218
+V1.5S_AGP
ST1
6 AGP_AD[31:0] J46 AGP_AD0 AGP_AD1 AGP_AD2 AGP_AD3 AGP_AD4 AGP_AD5 AGP_AD6 AGP_AD7 AGP_AD8 AGP_AD9 AGP_AD10 AGP_AD11 AGP_AD12 AGP_AD13 AGP_AD14 AGP_AD15 AGP_AD16 AGP_AD17 AGP_AD18 AGP_AD19 AGP_AD20 AGP_AD21 AGP_AD22 AGP_AD23 AGP_AD24 AGP_AD25 AGP_AD26 AGP_AD27 AGP_AD28 AGP_AD29 AGP_AD30 AGP_AD31 A65 B65 A63 B63 A62 B62 A60 B60 B57 A56 B56 A54 B54 A53 B53 A51 A39 B38 A38 B36 A36 B35 A35 B33 A30 B30 A29 B29 A27 B27 A26 B26 A32 B32 A59 B59 A18 B18 B7 B48 B50 B46 B8 A41 A8 B41 AGP_RST# 6 6 6 AGP_TRDY# AGP_RBF# AGP_WBF# A7 A46 B12 A14 A2 6 AGP_STOP# A47 B6 A6 B1 6 6 6 6 6 AGP_PAR AGP_ST0 AGP_ST1 AGP_ST2 AGP_PIPE# A50 B10 A10 B11 A12 A48 A4 B4 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 AD_STB1# AD_STB1 AD_STB0# AD_STB0 SB_STB# SB_STB CLK PERR# SERR# DEVSEL# REQ# FRAME# GNT# IRDY# RST# TRDY# RBF# WBF# TYPEDET# STOP# INTB# INTA# OVRCNT# PAR ST0 ST1 ST2 PIPE# PME# USBUSB+ GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10 GND11 GND12 GND13 GND14 GND15 GND16 GND17 GND18 RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 B14 B22 A3 A11 A22 A24 B5 B13 B19 B23 B31 B37 B49 B55 B61 A5 A13 A19 A23 A31 A37 A49 A55 A61 +V1.5S_AGP C632 C633 + C139 100uF C197 22UF C269 0.1UF C276 0.1UF C261 0.1UF C193 0.1UF 15,18,19 PCI_RST_SLOTS# 18,19,29,34 PCI_GATED_RST# 3 1 CON3_HDR +V1.5S 7,36,40 R480 0 124Pin_AGP-Rev2.0 3.3Vaux 5.0V2 5.0V1 12V VCC3.3_1 VCC3.3_2 VCC3.3_3 VCC3.3_4 VCC3.3_5 VCC3.3_6 VCC3.3_7 VCC3.3_8 VDDQ1 VDDQ2 VDDQ1.5_1 VDDQ1.5_2 VDDQ1.5_3 VDDQ1.5_4 VDDQ1.5_5 VDDQ1.5_6 VDDQ1.5_7 VDDQ1.5_8 VDDQ1.5_9 Vrefcg Vrefgc SBA0 SBA1 SBA2 SBA3 SBA4 SBA5 SBA6 SBA7 C/BE0# C/BE1# C/BE2# C/BE3#
ST0 0 1 X X
MCH STRAP DDR SDR 533 Mhz 400 Mhz

AGP_SBSTB AGP_ADSTB1 AGP_ADSTB0 AGP_SBSTB# R108 R116 R135 NO_STUFF_8.2K NO_STUFF_8.2K NO_STUFF_8.2K
4
+V3.3ALWAYS
B24 B3 B2 A1 B9 B16 B25 B28 A9 A16 A25 A28 B52 A52 B34 B40 B47 B58 B64 A34 A40 A58 A64 B66 A66 B15 A15 B17 A17 B20 A20 B21 A21 A57 B51 B39 A33 AGP_SBA0 AGP_SBA1 AGP_SBA2 AGP_SBA3 AGP_SBA4 AGP_SBA5 AGP_SBA6 AGP_SBA7 AGP_CBE#0 AGP_CBE#1 AGP_CBE#2 AGP_CBE#3
16,17,18,19,24,25,26,29,32,33,34,39,40 +V12S 19,22,34,35,40
+V5S_AGP
X X 0 1
C141 0.1UF AGP_ADSTB1# R367 NO_STUFF_8.2K R360 NO_STUFF_8.2K
+V1.5S_AGP +V3.3S_AGP +V1.5S_AGP

R352 8.2K AGP_ST2 AGP_ST1 AGP_ST0 R345 1K R154 1K_1% AGP_VREF 6 2 Measurement Point R350 NO_STUFF_1K R353 8.2K
AGP_ADSTB0# R374 NO_STUFF_8.2K
Stub should be< 0.1"
+V1.5S_AGP
+V1.5S_AGP AGP_FRAME# 2 RP20B AGP_TRDY# 4 RP22D AGP_STOP# 3 RP22C AGP_DEVSEL# 1 RP20A AGP_PIPE# AGP_IRDY# AGP_RBF# J44 R104 7 NO_STUFF_8.2K 5 NO_STUFF_8.2K 6 NO_STUFF_8.2K 8 NO_STUFF_8.2K NO_STUFF_8.2K
3
+V1.5S_AGP
R156 1K_1%
C480 0.1UF
C499 0.1UF
J41 1
6 AGP_ADSTB1# 6 AGP_ADSTB1 R126 R123 6 AGP_ADSTB0# 8.2K 8.2K 6 AGP_ADSTB0 6 AGP_SBSTB# 6 AGP_SBSTB 14 CLK_AGP_SLOT AGP_PERR# AGP_SERR# 6 AGP_DEVSEL# 6 6 6
2
Mobile AGP Sideband Header

5,16 AGP_BUSY# 1 2 3 4 5 6 6Pin_HDR
AGP_REQ# AGP_GNT# AGP_WBF#
AGP_SBA[7:0] 6
Place near MCH
Place near AGP
16,34 AGP_SUSPEND# 16,34 PM_C3_STAT# 16,29,31,34 PM_SUS_STAT#
3 RP20C 3 RP19C 4 RP18D 3 RP18C 2 RP19B
6 NO_STUFF_8.2K 6 NO_STUFF_8.2K 5 NO_STUFF_8.2K 6 NO_STUFF_8.2K 7 NO_STUFF_8.2K
AGP_CBE#[3:0] 6 J81 2 AGP_RST# +V1.5ALWAYS R481 NO_STUFF_0 40
AGP_REQ# AGP_FRAME# AGP_GNT# AGP_IRDY#
D3
Core Power R468/463 (V3S) R467/482 (V3A) IO Rail R480 (V1.5S) R481 (V1.5A) RESET J81 3-2 1-2 (Gated)
+V3.3ALWAYS
Cold
DEFAULT
Hot
On
STUFF NO_STUFF NO_STUFF NO_STUFF STUFF STUFF STUFF NO_STUFF STUFF NO_STUFF NO_STUFF STUFF NO_STUFF NO_STUFF STUFF STUFF NO_STUFF STUFF
C171 0.1UF
C268 0.1UF
C278 0.1UF
NO_STUFF_150uF NO_STUFF_150uF
16,17,18,19,24,25,26,29,32,33,34,39,40 4,17,19,20,24,31,32,33,35,36,37,40 R97 +V5S_AGP 2 1 +V3.3S_AGP +V5S
15,18,19,20,22 INT_PIRQB# 15,18,19,20,22 INT_PIRQA#
4,5,6,10,14,17,19,23,28,29,30,31,32,33,36,37,40 +V3.3S R482 R483 NO_STUFF_0 0 R467 NO_STUFF_0 R468 0
NO_STUFF_0.01_1% C133 22UF C145 0.1UF C144 0.1UF C181 22UF C170 22UF + C160 100uF C156 0.1UF C184 0.1UF C163 0.1UF
1
15,18,19,22,34 PCI_PME#
Title
AGP CONN
C
AGP 1.5V Connector

E
of
42
Design Guide
219
13,39 +V2.5_DDR 11,12 M_DATA_R_[63:0] 6,11 M_A_FR_[12:0] J43A M_A_FR_0 M_A_FR_1 M_A_FR_2 M_A_FR_3 M_A_FR_4 M_A_FR_5 M_A_FR_6 M_A_FR_7 M_A_FR_8 M_A_FR_9 M_A_FR_10 M_A_FR_11 M_A_FR_12 112 111 110 109 108 107 106 105 102 101 115 100 99 97 117 116 98 71 73 79 83 72 74 80 84 35 37 158 160 89 91 96 95 120 118 119 121 122 194 196 198 195 193 86 12 26 48 62 134 148 170 184 78 11,12 M_DQS_R[8:0] M_DQS_R0 M_DQS_R1 M_DQS_R2 M_DQS_R3 M_DQS_R4 M_DQS_R5 M_DQS_R6 M_DQS_R7 M_DQS_R8 11 25 47 61 133 147 169 183 77 CON200_DDR-SODIMM DQ0 5 A0 DQ1 7 A1 DQ2 13 A2 DQ3 17 A3 DQ4 6 A4 DQ5 8 A5 DQ6 14 A6 DQ7 18 A7 DQ8 19 A8 DQ9 23 A9 DQ10 29 A10/AP DQ11 31 A11 DQ12 20 A12 DQ13 24 A13(DU) DQ14 30 DQ15 32 BA0 DQ16 41 BA1 DQ17 43 BA2(DU) DQ18 49 CB0 DQ19 53 CB1 DQ20 42 CB2 DQ21 44 CB3 DQ22 50 CB4 DQ23 54 CB5 DQ24 55 CB6 DQ25 59 CB7 DQ26 65 CK0 DQ27 67 CK0# DQ28 56 CK1# DQ29 60 CK1 DQ30 66 CK2 DQ31 68 CK2# DQ32 127 CKE0 DQ33 129 CKE1 DQ34 135 CAS# DQ35 139 RAS# DQ36 128 WE# DQ37 130 S0# DQ38 136 S1# DQ39 140 SA0 DQ40 141 SA1 DQ41 145 SA2 DQ42 151 SCL DQ43 153 SDA DQ44 142 RESET(DU) DQ45 146 DQ46 152 DM0 DQ47 154 DM1 DQ48 163 DM2 DQ49 165 DM3 DQ50 171 DM4 DQ51 175 DM5 DQ52 164 DM6 DQ53 166 DM7 DQ54 172 DM8 DQ55 176 DQ56 177 DQS0 DQ57 181 DQS1 DQ58 187 DQS2 DQ59 189 DQS3 DQ60 178 DQS4 DQ61 182 DQS5 DQ62 188 DQS6 DQ63 190 DQS7 DQS8 11,12 M_A_SR_[12:0] M_DATA_R_0 M_A_SR_0 M_DATA_R_1 M_A_SR_1 M_DATA_R_2 M_A_SR_2 M_DATA_R_3 M_A_SR_3 M_A_SR_4 M_DATA_R_4 M_A_SR_5 M_DATA_R_5 M_DATA_R_6 M_A_SR_6 M_DATA_R_7 M_A_SR_7 M_A_SR_8 M_DATA_R_8 M_DATA_R_9 M_A_SR_9 M_A_SR_10 M_DATA_R_10 M_A_SR_11 M_DATA_R_11 M_A_SR_12 M_DATA_R_12 M_DATA_R_13 M_DATA_R_14 M_DATA_R_15 11,12 M_BS0_SR# M_DATA_R_16 11,12 M_BS1_SR# M_DATA_R_17 11,12 M_CB_R[7:0] M_CB_R0 M_DATA_R_18 M_DATA_R_19 M_CB_R1 M_CB_R2 M_DATA_R_20 M_DATA_R_21 M_CB_R3 M_CB_R4 M_DATA_R_22 M_DATA_R_23 M_CB_R5 M_DATA_R_24 M_CB_R6 M_DATA_R_25 M_CB_R7 M_DATA_R_26 6 M_CLK_DDR4 M_DATA_R_27 6 M_CLK_DDR4# M_DATA_R_28 6 M_CLK_DDR5# M_DATA_R_29 6 M_CLK_DDR5 M_DATA_R_30 6 M_CLK_DDR3 M_DATA_R_31 6 M_CLK_DDR3# M_DATA_R_32 6,12 M_CKE2_R# M_DATA_R_33 6,12 M_CKE3_R# M_DATA_R_34 11,12 M_CAS_SR# M_DATA_R_35 11,12 M_RAS_SR# M_DATA_R_36 11,12 M_WE_SR# M_DATA_R_37 6,12 M_CS2_R# M_DATA_R_38 +V3.3S 6,12 M_CS3_R# M_DATA_R_39 M_DATA_R_40 M_DATA_R_41 M_DATA_R_42 M_DATA_R_43 M_DATA_R_44 14,15,20,22 SMB_CLK M_DATA_R_45 14,15,20,22 SMB_DATA M_DATA_R_46 M_DATA_R_47 M_DATA_R_48 M_DATA_R_49 M_DATA_R_50 M_DATA_R_51 M_DATA_R_52 M_DATA_R_53 M_DATA_R_54 M_DATA_R_55 11,12 M_DQS_R[8:0] M_DQS_R0 M_DATA_R_56 M_DQS_R1 M_DATA_R_57 M_DQS_R2 M_DATA_R_58 M_DQS_R3 M_DATA_R_59 M_DQS_R4 M_DATA_R_60 M_DATA_R_61 M_DQS_R5 M_DATA_R_62 M_DQS_R6 M_DQS_R7 M_DATA_R_63 M_DQS_R8 4,5,6,9,14,17,19,23,28,29,30,31,32,33,36,37,40 112 111 110 109 108 107 106 105 102 101 115 100 99 97 117 116 98 71 73 79 83 72 74 80 84 35 37 158 160 89 91 96 95 120 118 119 121 122 194 196 198 195 193 86 12 26 48 62 134 148 170 184 78 11 25 47 61 133 147 169 183 77 J50A CON200_DDR-SODIMM_REV M_DATA_R_0 DQ0 5 M_DATA_R_1 DQ1 7 13 M_DATA_R_2 DQ2 M_DATA_R_3 DQ3 17 M_DATA_R_4 DQ4 6 M_DATA_R_5 DQ5 8 M_DATA_R_6 DQ6 14 M_DATA_R_7 DQ7 18 M_DATA_R_8 19 DQ8 M_DATA_R_9 DQ9 23 M_DATA_R_10 DQ10 29 M_DATA_R_11 DQ11 31 M_DATA_R_12 DQ12 20 M_DATA_R_13 DQ13 24 M_DATA_R_14 DQ14 30 M_DATA_R_15 BA0 DQ15 32 M_DATA_R_16 BA1 DQ16 41 M_DATA_R_17 BA2(DU) DQ17 43 M_DATA_R_18 CB0 DQ18 49 M_DATA_R_19 CB1 DQ19 53 M_DATA_R_20 CB2 DQ20 42 M_DATA_R_21 CB3 DQ21 44 M_DATA_R_22 CB4 DQ22 50 M_DATA_R_23 CB5 DQ23 54 M_DATA_R_24 CB6 DQ24 55 M_DATA_R_25 CB7 DQ25 59 M_DATA_R_26 CK0 DQ26 65 M_DATA_R_27 CK0# DQ27 67 M_DATA_R_28 CK1# DQ28 56 M_DATA_R_29 CK1 DQ29 60 M_DATA_R_30 CK2 DQ30 66 M_DATA_R_31 CK2# DQ31 68 M_DATA_R_32 CKE0 DQ32 127 M_DATA_R_33 CKE1 DQ33 129 M_DATA_R_34 CAS# DQ34 135 M_DATA_R_35 RAS# DQ35 139 M_DATA_R_36 WE# DQ36 128 M_DATA_R_37 S0# DQ37 130 M_DATA_R_38 S1# DQ38 136 M_DATA_R_39 SA0 DQ39 140 M_DATA_R_40 SA1 DQ40 141 M_DATA_R_41 SA2 DQ41 145 M_DATA_R_42 SCL DQ42 151 M_DATA_R_43 SDA DQ43 153 M_DATA_R_44 RESET(DU) DQ44 142 M_DATA_R_45 DQ45 146 M_DATA_R_46 DM0 DQ46 152 M_DATA_R_47 DM1 DQ47 154 M_DATA_R_48 DM2 DQ48 163 M_DATA_R_49 DM3 DQ49 165 M_DATA_R_50 DM4 DQ50 171 M_DATA_R_51 DM5 DQ51 175 M_DATA_R_52 DM6 DQ52 164 M_DATA_R_53 DM7 DQ53 166 M_DATA_R_54 DM8 DQ54 172 M_DATA_R_55 DQ55 176 M_DATA_R_56 DQS0 DQ56 177 M_DATA_R_57 DQS1 DQ57 181 M_DATA_R_58 DQS2 DQ58 187 M_DATA_R_59 DQS3 DQ59 189 M_DATA_R_60 DQS4 DQ60 178 M_DATA_R_61 DQS5 DQ61 182 M_DATA_R_62 DQS6 DQ62 188 M_DATA_R_63 DQS7 DQ63 190 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13(DU) DQS8 9 21 33 45 57 69 81 93 113 131 143 155 157 167 179 191 10 22 34 36 46 58 70 82 92 94 114 132 144 156 168 180 192 199 197 1 2
J43B
6,11 M_BS0_FR# 6,11 M_BS1_FR# 11,12 M_CB_R[7:0] M_CB_R0 M_CB_R1 M_CB_R2 M_CB_R3 M_CB_R4 M_CB_R5 M_CB_R6 M_CB_R7 6 6 6 6 6 6 6,12 6,12 6,11 6,11 6,11 M_CLK_DDR1 M_CLK_DDR1# M_CLK_DDR2# M_CLK_DDR2 M_CLK_DDR0 M_CLK_DDR0# M_CKE0_R# M_CKE1_R# M_CAS_FR# M_RAS_FR# M_WE_FR# 6,12 M_CS0_R# 6,12 M_CS1_R#
+V3.3S
CON200_DDR-SODIMM VSS1 3 VDD1 VSS2 15 VDD2 VSS3 27 VDD3 VSS4 39 VDD4 VSS5 51 VDD5 VSS6 63 VDD6 VSS7 75 VDD7 VSS8 87 VDD8 VSS9 103 VDD9 VSS10 125 VDD10 VSS11 137 VDD11 VSS12 149 VDD12 VSS13 159 VDD13 VSS14 161 VDD14 VSS15 173 VDD15 VSS16 185 VDD16 VSS17 4 VDD17 VSS18 16 VDD18 VSS19 28 VDD19 VSS20 38 VDD20 VSS21 40 VDD21 VSS22 52 VDD22 VSS23 64 VDD23 VSS24 76 VDD24 VSS25 88 VDD25 VSS26 90 VDD26 VSS27 104 VDD27 VSS28 126 VDD28 VSS29 138 VDD29 VSS30 150 VDD30 VSS31 162 VDD31 VSS32 174 VDD32 VSS33 186 VDD33 VDDID VDDSPD VREF1 VREF2 DU1 DU2 DU3 DU4 85 123 124 200
4,5,6,9,14,17,19,23,28,29,30,31,32,33,36,37,40
C513 0.1UF +V2.5_DDR 13,39 9 21 33 45 57 69 81 93 113 131 143 155 157 167 179 191 10 22 34 36 46 58 70 82 92 94 114 132 144 156 168 180 192 199 197 1 2 C535 0.1UF
J50B
14,15,20,22 SMB_CLK 14,15,20,22 SMB_DATA
SO DIMM 0
1
SO DIMM 1
6,39 SM_VREF R222 0
+V3.3S
VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18 VDD19 VDD20 VDD21 VDD22 VDD23 VDD24 VDD25 VDD26 VDD27 VDD28 VDD29 VDD30 VDD31 VDD32 VDD33
CON200_DDR-SODIMM_REV VSS1 3 VSS2 15 VSS3 27 VSS4 39 VSS5 51 VSS6 63 VSS7 75 VSS8 87 VSS9 103 VSS10 125 VSS11 137 VSS12 149 VSS13 159 VSS14 161 VSS15 173 VSS16 185 VSS17 4 VSS18 16 VSS19 28 VSS20 38 VSS21 40 VSS22 52 VSS23 64 VSS24 76 VSS25 88 VSS26 90 VSS27 104 VSS28 126 VSS29 138 VSS30 150 VSS31 162 VSS32 174 VSS33 186 DU1 DU2 DU3 DU4 85 123 124 200
4,5,6,9,14,17,19,23,28,29,30,31,32,33,36,37,40
VDDID VDDSPD VREF1 VREF2
Title
DDR SO-DIMM
E
of
42
Design Guide
220
10,12 M_DQS_R[8:0]
M_DQS_R8 M_DQS_R7 M_DQS_R6 M_DQS_R5 M_DQS_R4
R377 22 R381 22 R384 22 R380 22 R383 22 R378 22 R382 22 R379 22 R376 22
M_DQS8 M_DQS7 M_DQS6 M_DQS5 M_DQS4 M_DQS3 M_DQS2 M_DQS1 M_DQS0
M_DQS[8:0] 6
M_DQS_R3 M_DQS_R2 M_DQS_R1 M_DATA_R_[63:0] 10,12 M_DATA0 M_DATA1 M_DATA2 M_DATA3 M_DATA4 M_DATA5 M_DATA6 M_DATA7 M_DATA8 M_DATA9 4RP46D 22 5 M_DATA_R_0 RP46C 22 6 M_DATA_R_1 3 2RP46B 22 7 M_DATA_R_2 1RP46A 22 8 M_DATA_R_3 4RP28D 22 5 M_DATA_R_4 RP28C 22 6 M_DATA_R_5 3 2RP28B 22 7 M_DATA_R_6 1RP28A 22 8 M_DATA_R_7 4RP47D 22 5 M_DATA_R_8 RP47C 22 6 M_DATA_R_9 3 2RP47B 22 7 M_DATA_R_10 1RP47A 22 8 M_DATA_R_11 4RP29D 22 5 M_DATA_R_12 RP29C 22 6 M_DATA_R_13 3 2RP29B 22 7 M_DATA_R_14 1RP29A 22 8 M_DATA_R_15 4RP48D 22 5 M_DATA_R_16 RP48C 22 6 M_DATA_R_17 3 2RP48B 22 7 M_DATA_R_18 1RP48A 22 8 M_DATA_R_19 4RP30D 22 5 M_DATA_R_20 RP30C 22 6 M_DATA_R_21 3 2RP30B 22 7 M_DATA_R_22 1RP30A 22 8 M_DATA_R_23 4RP49D 22 5 M_DATA_R_24 RP49C 22 6 M_DATA_R_25 3 2RP49B 22 7 M_DATA_R_26 1RP49A 22 8 M_DATA_R_27 4RP31D 22 5 M_DATA_R_28 RP31C 22 6 M_DATA_R_29 3 2RP31B 22 7 M_DATA_R_30 1RP31A 22 8 M_DATA_R_31 M_DATA32 M_DATA33 M_DATA34 M_DATA35 M_DATA36 M_DATA37 M_DATA38 M_DATA39 M_DATA40 M_DATA41 M_DATA42 M_DATA43 M_DATA44 M_DATA45 M_DATA46 M_DATA47 M_DATA48 M_DATA49 M_DATA50 M_DATA51 M_DATA52 M_DATA53 M_DATA54 M_DATA55 M_DATA56 M_DATA57 M_DATA58 M_DATA59 M_DATA60 M_DATA61 M_DATA62 M_DATA63 4RP50D 22 5 M_DATA_R_32 RP50C 22 6 M_DATA_R_33 3 2RP50B 22 7 M_DATA_R_34 1RP50A 22 8 M_DATA_R_35 4RP32D 22 5 M_DATA_R_36 3RP32C 22 6 M_DATA_R_37 2RP32B 22 7 M_DATA_R_38 1RP32A 22 8 M_DATA_R_39 4RP51D 22 5 M_DATA_R_40 RP51C 22 6 M_DATA_R_41 3 2RP51B 22 7 M_DATA_R_42 1RP51A 22 8 M_DATA_R_43 4RP33D 22 5 M_DATA_R_44 3RP33C 22 6 M_DATA_R_45 2RP33B 22 7 M_DATA_R_46 1RP33A 22 8 M_DATA_R_47 4RP52D 22 5 M_DATA_R_48 3RP52C 22 6 M_DATA_R_49 2RP52B 22 7 M_DATA_R_50 1RP52A 22 8 M_DATA_R_51 4RP34D 22 5 M_DATA_R_52 3RP34C 22 6 M_DATA_R_53 2RP34B 22 7 M_DATA_R_54 1RP34A 22 8 M_DATA_R_55 4RP53D 22 5 M_DATA_R_56 3RP53C 22 6 M_DATA_R_57 2RP53B 22 7 M_DATA_R_58 1RP53A 22 8 M_DATA_R_59 4RP35D 22 5 M_DATA_R_60 3RP35C 22 6 M_DATA_R_61 2RP35B 22 7 M_DATA_R_62 1RP35A 22 8 M_DATA_R_63 6,10 M_BS0_FR# 6,10 M_BS1_FR# 6,10 M_CAS_FR# 6 M_DATA[63:0] 6,10 M_RAS_FR# 6,10 M_WE_FR# 6,10 M_A_FR_[12:0] 10,12 M_CB_R[7:0] M_CB_R7 M_CB_R6 M_CB_R5 M_CB_R4 M_CB_R3 M_CB_R2 M_CB_R1 M_CB_R0 4 3 2 1 4 3 2 1 M_DQS_R0
RP25D 22 RP25C 22 RP25B 22 RP25A 22 RP43D 22 RP43C 22 RP43B 22 RP43A 22
5 6 7 8 5 6 7 8
M_CB7 M_CB6 M_CB5 M_CB4 M_CB3 M_CB2
M_CB[7:0] 6
M_DATA10 M_DATA11 M_DATA12 M_DATA13 M_DATA14 M_DATA15 M_DATA16 M_DATA17 M_DATA18 M_DATA19 M_DATA20 M_DATA21 M_DATA22
2
M_CB1 M_CB0
M_DATA23 M_DATA24 M_DATA25 M_DATA26 M_DATA27 M_DATA28 M_DATA29 M_DATA30 M_DATA31
RP60D 10 M_A_FR_12 4 5 RP70D 10 M_A_FR_11 4 5 RP61C 10 M_A_FR_10 3 6 RP60C 10 M_A_FR_9 3 6 RP70C 10 M_A_FR_8 3 6 RP60B 10 M_A_FR_7 2 7 RP70B 10 M_A_FR_6 2 7 RP60A 10 M_A_FR_5 1 8 RP70A 10 M_A_FR_4 1 8 RP71D 10 M_A_FR_3 4 5 RP71C 10 M_A_FR_2 3 6 RP61D 10 M_A_FR_1 4 5 RP71B 10 M_A_FR_0 2 7
M_A_SR_12 M_A_SR_11 M_A_SR_10 M_A_SR_9 M_A_SR_8 M_A_SR_7 M_A_SR_6 M_A_SR_5 M_A_SR_4 M_A_SR_3 M_A_SR_2 M_A_SR_1 M_A_SR_0
M_A_SR_[12:0] 10,12
RP61A 1 RP61B 2 RP62B 2 RP62C 3 RP62D 4
10 8 10 7 10 7 10 6 10 5
M_BS0_SR# 10,12 M_BS1_SR# 10,12 M_CAS_SR# 10,12 M_RAS_SR# 10,12 M_WE_SR# 10,12
Title
DDR SERIES TERMINATION

E
of
42
Design Guide
221
+V1.25
6,13,39
M_CB_R[7:0] 10,11
RP92B
56
M_DQS_R[8:0]
M_DQS_R0 R412 R411 M_CS2_R# M_CS3_R# 10,11 M_BS0_SR# 10,11 M_BS1_SR# R410 R406 R409 6,10 6,10 RP78B M_A_SR_7 M_A_SR_8 M_A_SR_9 M_A_SR_10 M_A_SR_11 M_A_SR_12 RP90C RP78A RP90D RP77A RP89A RP77B 7 2 56 4 5 8 1 56 RP89D 56 4 5 8 1 56 RP77D 56 2 7 5 4 56 RP90B 56 3 6 1 8 56 RP89C 56 3 6 6 3 56 RP77C 56 2 7 2 7 56 RP89B 56 6,10 6,10 56 56 R405 56 M_DQS_R8 56 R404 56 M_DQS_R7 M_CKE3_R# M_CKE2_R# 56 R407 56 M_DQS_R6 56 R408 56 M_DQS_R5 M_DQS_R1 M_DQS_R2 M_DQS_R3 M_DQS_R4 M_A_SR_0 M_A_SR_1
M_CKE0_R# M_CKE1_R#
M_CS0_R# M_CS1_R#
6,10 6,10
6,10 6,10
M_A_SR_[12:0]
M_A_SR_2 M_A_SR_3 M_A_SR_4 M_A_SR_5 M_A_SR_6
Title
Project:
10,11 M_DATA_R_[63:0]
M_DATA_R_[63:0]
M_DATA_R_31 RP68A 8
56
RP73D
56
M_DATA_R_30 RP68B 7
56
RP73C
56
M_DATA_R_29 RP68C 6
56
RP73B
56
M_DATA_R_28 RP68D 5
56
RP73A
56
M_DATA_R_27 RP80D 5
56
RP82A
56
M_DATA_R_59 M_DATA_R_60 M_DATA_R_61 M_DATA_R_62 M_DATA_R_63
M_DATA_R_26 RP80C 6
56
RP82B
56
M_DATA_R_25 RP80B 7
56
RP82C
56
M_DATA_R_24 RP80A 8
56
RP82D
56
M_DATA_R_23 RP64A 8
56
RP67D
56
M_DATA_R_22 RP64B 7
56
RP67C
56
M_DATA_R_21 RP64C 6
56
RP67B
56
M_DATA_R_20 RP64D 5
56
RP67A
56
M_DATA_R_19 RP79D 5
56
RP81A
56
M_DATA_R_18 RP79C 6
56
RP81B
56
M_DATA_R_17 RP79B 7
56
RP81C
56
M_DATA_R_16 RP79A 8
56
RP81D
56
M_DATA_R_15 RP63A 8
56
RP66D
56
M_DATA_R_14 RP63B 7
56
RP66C
56
M_DATA_R_46 M_DATA_R_47 M_DATA_R_48 M_DATA_R_49 M_DATA_R_50 M_DATA_R_51 M_DATA_R_52 M_DATA_R_53 M_DATA_R_54 M_DATA_R_55 M_DATA_R_56 M_DATA_R_57 M_DATA_R_58
M_DATA_R_13 RP63C 6
56
RP66B
56
M_DATA_R_12 RP63D M_DATA_R_44 M_DATA_R_45 5
56
RP66A
56
M_DATA_R_11 RP86D M_DATA_R_43 5
56
RP85A
56
M_DATA_R_10 RP86C M_DATA_R_42 6
56
RP85B
56
M_DATA_R_9 M_DATA_R_41
RP86B
56
RP85C
56
M_DATA_R_8
RP86A M_DATA_R_40
56
RP85D
56
M_DATA_R_7
RP65A M_DATA_R_39
56
RP72D
56
M_DATA_R_6
RP65B M_DATA_R_38
56
RP72C
56
M_DATA_R_5
RP65C M_DATA_R_37
56
RP72B
56
M_DATA_R_4
RP65D M_DATA_R_36
56
RP72A
56
M_DATA_R_3 M_DATA_R_35
RP76D
56
RP84A
56
10,11 M_A_SR_[12:0]
M_DATA_R_2
RP76C M_DATA_R_34
56
RP84B
56
10,11 M_DQS_R[8:0]
M_DATA_R_1
M_DATA_R_33
RP76B
56
RP84C
56
M_DATA_R_0
RP76A M_DATA_R_32
56
RP84D
56
Design Guide
RP91B
56
RP91A
56
845MP/MZ Platform m
RP92D
56
RP92C
56
10,11 M_WE_SR#
RP92A 6 8 1
56
DDR Parallel Termination
10,11 M_RAS_SR#
10,11 M_CAS_SR#
RP90A
56
RP78C
56
R385
R386
56
56
M_CB_R7 RP91D 56
Sheet
RP69A
56
M_CB_R6 RP78D 56
RP69B
56
M_CB_R5 RP91C 56
RP69C
56
12
M_CB_R4
E
RP69D
56
M_CB_R3
of
RP83D
56
M_CB_R2
RP83C
56
M_CB_R1
42
RP83B
56
M_CB_R0
RP83A
56
222
+V2.5_DDR
10,39 +V2.5 7,8,39,40

One 0.1uF cap per power pin. Place each cap close to pin. 2 R171 1
NO_STUFF_0.01_1% C540 0.1UF C538 0.1UF C547 0.1UF C548 0.1UF C537 0.1UF C545 0.1UF C539 0.1UF C546 0.1UF C536 0.1UF C511 0.1UF C509 0.1UF
C283 150uF
C341 150uF
C325 150uF
C306 150uF
C506 0.1UF
C504 0.1UF
C512 0.1UF
C510 0.1UF
C505 0.1UF
C503 0.1UF
Layout note: Place capacitors between and near DDR connector if possible.
+V1.25 6,12,39
Layout note: Place one cap close to every 2 pullup resistors terminated to +V1.25.
C523 0.1UF
C521 0.1UF
C524 0.1UF
C518 0.1UF
C519 0.1UF
C515 0.1UF
C529 0.1UF
C533 0.1UF
C564 0.1UF
C589 0.1UF
C556 0.1UF
C557 0.1UF
C583 0.1UF
C585 0.1UF
C584 0.1UF
C581 0.1UF
C528 0.1UF
C587 0.1UF
C566 0.1UF
C570 0.1UF
C576 0.1UF
C565 0.1UF
C568 0.1UF
C520 0.1UF
C563 0.1UF
C562 0.1UF
C582 0.1UF
C586 0.1UF
C572 0.1UF
C571 0.1UF
C573 0.1UF
C561 0.1UF
C560 0.1UF
C558 0.1UF
C555 0.1UF
C579 0.1UF
C580 0.1UF
C569 0.1UF
C567 0.1UF
C553 0.1UF
C517 0.1UF
C522 0.1UF
C577 0.1UF
C527 0.1UF
C532 0.1UF
C588 0.1UF
C574 0.1UF
C516 0.1UF
1
C526 0.1UF
C530 0.1UF
C559 0.1UF
C531 0.1UF
C554 0.1UF
C525 0.1UF
1
Title
DDR Decoupling
E
of
42
Design Guide
223
+V3.3 Only need the AND gate if S1M is supported 5 1
17,19,21,24,27,29,34,36,40 R470 NO_STUFF_0 4 CK408PWRDN# FB20 +VDD3S_CLK 1 2 300ohm@100MHz 2 C431 C115 22UF 1UF 2 1 C429 0.1UF C430 0.1UF C86 0.1UF C433 0.1UF C438 0.1UF C427 0.1UF C437 0.1UF C432 0.1UF 4,5,6,9,10,17,19,23,28,29,30,31,32,33,36,37,40 +V3.3S_CLKSRC R84 1
4
+V3.3S
16,24,34,40 PM_SLP_S1# 16,21,29,34,39,40 PM_SLP_S3# J19

4
2 74AHC1G08 U60 3
1 5 3 2 4 NO_STUFF_SMA CON Place 0ohm near crystal. NO_STUFF_0
Used for D3 Hot
NO_STUFF_0.01_1%
Place crystal within 500 mils of CK_TITAN
R39 14.318MHZ Y2 1 2
Note: 1) CPU[2:0] needs to be running in C3, C4 2) PCIF2 should be the free-running PCI clock U16 +V3.3S_CLKSRC FB21 1 2 300ohm@100MHz C435 0.1UF XTAL_IN 1 8 14 19 32 37 46 50 2 3 R332 1K CK408_SEL2 CK408_SEL1 CK408_SEL0 40 55 54 25 34 0 53 28 43 29 30 R389 C542 CK_IREF R331 475_1% 33 33 35 42 41 4 9 15 20 31 36 47 VDD0 VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 XTAL_IN XTAL_OUT SEL2 SEL1 66INPUT SEL0 PWRDWN# PCI_STOP# CPU_STOP# VTT_PWRGD# MULT0 SDATA SCLOCK 3V66_0 3V66_1/VCH IREF VSSIREF VSS0 VSS1 VSS6 VSS2 VSS3 VSS4 VSS5 PCI0 USB DOT REF CK-408 10 39 38 56 66BUF2 66BUF1 66BUF0 PCIF2 PCIF1 PCIF0 PCI6 PCI5 PCI4 PCI3 PCI2 PCI1 VDDA VSSA CPU2 CPU2# CPU1 CPU1# CPU0 CPU0# 26 27 45 44 49 48
FB22 +V3SA_CLK C439 0.1UF C128 22UF 1 2 300ohm@100MHz
C45
C46 NO_STUFF_10pF NO_STUFF_10pF
No stuff; caps are internal to CK-408.
R75 NO_STUFF_54.9_1% R72 R77 R64 R68 33 33 33 33 33 33 R59 NO_STUFF_54.9_1% 2 3 4 2 RP16B 33 RP16C33 RP16D33 RP7B 33 7 6 5 7 R55 NO_STUFF_54.9_1% R62 NO_STUFF_0 R63 NO_STUFF_0 CLK_ITP_CPU 3 CLK_CPU_BCLK 3 CLK_CPU_BCLK# 3 R78 NO_STUFF_54.9_1% R65 NO_STUFF_54.9_1% CLK_MCH_BCLK 7 CLK_MCH_BCLK# 7 R69 NO_STUFF_54.9_1% R51 CLK_ITP 0 R52 0
3
C113 22UF
VDD5_48Mhz
+V3.3S_CLKSRC
3
XTAL_OUT NO_STUFF_330 R44 R42 1K
52 R54 51 R58 24 23 22 21 7 6 5 18 17 16 13 12 11 3 2 3 4 1 2 3 4 1 R82
CLK_ITP_CPU# 3 C118
CLK_ITP# 5 NO_STUFF_10pF
CLK_AGP_SLOT 9 CLK_MCH66 6 CLK_ICH66 8,15 CLK_ICHPCI 15
NO_STUFF_0
R43 1K R37
CK408PWRDN# 16,34 PM_STPPCI# R328 16,34,36,37 PM_STPCPU# +V3.3S_CLKSRC 36VR_PWRGD_CK408# R330 10K R329 NO_STUFF_10K
C110 NO_STUFF_10pF C109 NO_STUFF_10pF C68 NO_STUFF_10pF
3 H_BSEL0 3 H_BSEL1
2
R49 R45
0 NO_STUFF_0 Q5
RP7C 33 RP9B 33 RP9C 33 RP9D 33 RP8A 33 RP8B 33 RP8C 33 RP8D 33 RP7A 33 33
6 7 6 5 8 7 6 5 8
CLK_PCI_PORT80 30 CLK_PCI_SLOT3 19 CLK_PCI_SLOT2 18 CLK_PCI_SLOT1 18 CLK_DOCKPCI 20 CLK_FWHPCI 28 CLK_SIOPCI 31 CLK_SMCPCI 29 CLK_LPCPCI 34 CLK_ICH48 16
C67 C101 C98 C91 C89 C81 C77 C75 C71 C105
NO_STUFF_10pF NO_STUFF_10pF NO_STUFF_10pF NO_STUFF_10pF NO_STUFF_10pF NO_STUFF_10pF NO_STUFF_10pF NO_STUFF_10pF NO_STUFF_10pF NO_STUFF_10pF
2
10,15,20,22 SMB_DATA Q7 10,15,20,22 SMB_CLK
4 CLK_PLD NO_STUFF_BAR43 NO_STUFF_BAR43 NO_STUFF_10pF J18 1 2 Measurement Point
No Stuff
SEL1 0 0 1 1 MULT 1 0 SEL0 0 1 0 1 R331 475 1% 221 1% FUNCTION 66Mhz Host CLK 100Mhz Host CLK 200Mhz Host CLK 133Mhz Host CLK CK408 CLOCK SWING CONFIG 0.7 VOLTS 1.0 VOLTS
CLK_REF0
R41 R40 R38
33 33 33
CLK_LPC14 34 CLK_SIO14 31 CLK_ICH14 16
C61 C60 C59
NO_STUFF_10pF NO_STUFF_10pF NO_STUFF_10pF

1
Correct CK408 IPN is: A62115-001
CK-408
Title
CK-408
E
of
42
Design Guide
224
5,16,17,18,19,20,22,34 U46A 18,19,20 PCI_AD[31:0] PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 PCI_C/BE0# PCI_C/BE1# PCI_C/BE2# PCI_C/BE3# PCI_GNT1# PCI_GNT2# PCI_GNT3# PCI_GNT4# PCI_REQ0# PCI_REQ1# PCI_REQ2# PCI_REQ3# PCI_REQ4# CLK_ICHPCI PCI_DEVSEL# PCI_FRAME# PCI_REQA# PCI_REQB# PCI_GNTA# PCI_GNTB# PCI_IRDY# PCI_PAR PCI_PERR# PCI_LOCK# PCI_PME# J2 K1 J4 K3 H5 K4 H3 L1 L2 G2 L4 H4 M4 J3 M5 J1 F5 N2 G4 P2 G1 P1 F2 P3 F3 R1 E2 N4 D1 P4 E1 P5 K2 K5 N1 R2 A4 E3 D2 D5 B4 D3 F4 A3 R4 E4 T5 M3 F1 C4 D4 B6 B3 N3 G5 M2 M1 W1 Y1 L5 H2 H1 PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 PCI_C/BE0# PCI_C/BE1# PCI_C/BE2# PCI_C/BE3# PCI_GNT0# PCI_GNT1# PCI_GNT2# PCI_GNT3# PCI_GNT4# PCI_REQ0# PCI_REQ1# PCI_REQ2# PCI_REQ3# PCI_REQ4# PCI_CLK PCI_DEVSEL# PCI_FRAME# PCI_GPIO0/REQA# PCI_GPIO1/REQB_L/REQ5# PCI_GPIO16/GNTA# PCI_GPIO17/GNTB_L/GNT5# PCI_IRDY# PCI_PAR PCI_PERR# PCI_LOCK# PCI_PME# PCI_RST# PCI_SERR# PCI_STOP# PCI_TRDY# SM_INTRUDER# SMLINK0 System SMLINK1 Management SMB_CLK I/F SMB_DATA SMB_ALERT#/GPIO11 CPU_A20GATE CPU_A20M# CPU_DPSLP# CPU_FERR# CPU_IGNNE# CPU_INIT# CPU_INTR CPU I/F CPU_NMI CPU_PWRGOOD CPU_RCIN# CPU_SLP# CPU_SMI# CPU_STPCLK# HUB_PD0 HUB_PD1 HUB_PD2 HUB_PD3 HUB_PD4 HUB_PD5 HUB_PD6 HUB_PD7 HUB_PD8 HUB_PD9 HUB_PD10 HUB_CLK HUB_PAR HUB_PSTRB HUB_PSTRB# HUB_RCOMP HUB_VREF HUB_VSWING INT_APICCLK INT_APICD0 INT_APICD1 INT_PIRQA# Interrupt INT_PIRQB# I/F INT_PIRQC# INT_PIRQD# INT_PIRQE#/GPIO2 INT_PIRQF#/GPIO3 INT_PIRQG#/GPIO4 INT_PIRQH#/GPIO5 INT_IRQ14 INT_IRQ15 INT_SERIRQ EEPROM I/F EEP_CS EEP_DIN EEP_DOUT EEP_SHCLK LAN_RXD0 LAN_RXD1 LAN_RXD2 LAN_TXD0 LAN_TXD1 LAN_TXD2 LAN_JCLK LAN_RSTSYNC Y6 AC3 AB2 AC4 AB5 AC5 Y22 V23 AB22 J22 AA21 AB23 AA23 Y21 W23 U22 W21 Y23 U23 L22 M21 M23 N20 P21 R22 R20 T23 M19 P19 N19 T19 R19 N22 P23 K19 L20 L19 J19 J20 J21 B1 C1 B2 A2 A6 B5 C5 A5 AB14 W19 H22 E9 D8 E8 D10 C8 A8 A9 B9 C10 A10 C9 D7 HUB_PD0 HUB_PD1 HUB_PD2 HUB_PD3 HUB_PD4 HUB_PD5 HUB_PD6 HUB_PD7 HUB_PD8 HUB_PD9 HUB_PD10 SM_INTRUDER# 22,34 SMLINK0 19,22 SMLINK1 19,22 SMB_CLK 10,14,20,22 SMB_DATA 10,14,20,22 SMB_ALERT# 22,34 H_A20GATE 33 H_A20M# 3,34 H_DPSLP# 3,34 H_IGNNE# 3,34 H_INTR 3,34 H_INIT# 3,34 H_NMI 3,34 H_PWRGD 3,34 H_RCIN# 29,34 H_CPUSLP# 3,34 H_SMI# 3,34 H_STPCLK# 3,34 HUB_PD[10:0] 6,8 R244 300 6
+V3.3S_ICH 28 +V3.3S_FWH 3,4,5,7,17,36,37,38 R247 470 3 5 R369 470 +VCC_CORE R368 56 2 H_FERR_S# 3 3 5 CR11A 3904 4 R276 470 R251 300 6 CR11B 3904 1 FWH_INIT# 28
4
ICH3-M
PART A
2 CR9B 1 3904 H_FERR#
CR9A 4 3904 R283 470
8,17
+V1.8S_ICH
PLACE RCOMP resistor within 0.5" of ICH pad using a thick trace RCOMP R should be 2/3 board impedance
10 mil trace, 7 mil space

HUB_VREF_ICH C591 0.01UF
R416 301_1% 2 R417 301_1% 1
C578 NO_STUFF_0.01UF J63 Measurement Point

3
Hublink I/F PCI I/F
18,19,20 18,19,20 18,19,20 18,19,20 18 18 19 20 22 18,22 18,22 19,22 20,22 14 18,19,20,22 18,19,20,22 18 20 16,18 20 18,19,20,22 18,19,20 18,19,22 18,19,20,22 9,18,19,22,34
CLK_ICH66 8,14 TP_HUBPAR 34 HUB_PSTRB 6,8 HUB_PSTRB# 6,8
R227 36.5_1% HUB_RCOMP_ICH +V1.8S_ICH 8,17
C364 10K R418 INT_PIRQA# 9,18,19,20,22 INT_PIRQB# 9,18,19,20,22 INT_PIRQC# 18,19,20,22 INT_PIRQD# 18,19,20,22 INT_PIRQE# 19,22 INT_PIRQF# 19,22 INT_PIRQG# 19,22 INT_PIRQH# 19,22,34 INT_IRQ14 22,23,34 INT_IRQ15 22,23,34 INT_SERIRQ 18,19,20,29,31,34 EEP_CS EEP_SK EEP_DOUT EEP_DIN LAN_RXD0 27 LAN_RXD1 27 LAN_RXD2 27 LAN_TXD0 27 LAN_TXD1 27 LAN_TXD2 27 LAN_JCLK 27 LAN_RST 27 1 2 3 4 R234 301_1%
HUB INTERFACE VSWING VOLTAGE
NO_STUFF_470PF HUB INTERFACE LAYOUT: R233 Route signals with 5/20 trace/space routing. Signals NO_STUFF_56.2_1% must match +/- 0.1" of HUB_STB/STB# signals
(1/2) 1.8V
C368 17 U31 8 7 6 5 +V3.3_ICHLAN 0.1UF R242 301_1% R243 0
2
CS VCC SK DC DI ORG DO GND AT88SC153
C373 0.1UF
range for R234, R242: 100 ohm - 1K
18,19,20,22 PCI_SERR# 18,19,20,22 PCI_STOP# 18,19,20,22 PCI_TRDY#
LAN I/F
EEPROM for ICH3-M LAN (Atmel AT93C66-10PC-2.7)
LAN_EEP_DOUT 16
ICH3-M R17 PCIRSTR# C629 NO_STUFF_22PF

1
22 PCI_RST_MCH# 6
Correct ICH3 IPN is: A42352-007

PCI_RST_ONBD# 4,20,28,29,30,31,34
1
R27
22 C630 NO_STUFF_22PF
R24
22 PCI_RST_SLOTS# 9,18,19 C631 NO_STUFF_22PF
Title
ICH3-M (1 of 3)
E
of
42
Design Guide
225
U46B 5,9 27,29 29,33,34 9,34 22,29,31,34 34,36,37 29,34 21,29,34,36 21,22,32,34 29,34 14,24,34,40 14,21,29,34,39,40 29,34,40 BIOS Note: 14,34,36,37 BIOS should disable 14,34 PM_STPCPU# on CK-Titan. 34 9,29,31,34 (use H_DPSLP# instead) 5,29,34 AGP_BUSY# PM_LANPWROK PM_BATLOW# PM_C3_STAT# PM_CLKRUN# PM_DPRSLPVR PM_PWRBTN# PM_PWROK PM_RI# PM_RSMRST# PM_SLP_S1# PM_SLP_S3# PM_SLP_S5# PM_STPCPU# PM_STPPCI# PM_SUS_CLK PM_SUS_STAT# PM_THRM# V4 Y5 AB3 V5 AC2 AB21 AB1 AA6 AA1 AA7 W20 AA5 AA2 V21 U21 AA4 AB4 U5 U20 Y20 V19 B7 D11 B11 C11 C7 A7 V1 U3 T3 U2 T2 U4 U1 D19 A19 E17 B17 D15 A15 D18 A18 E16 B16 D14 A14 E12 D12 C12 B12 A12 A11 H20 G22 F21 G19 E22 E21 H21 G23 F23 G21 D23 E23 PM_AGPBUSY#/GPIO6 PM_AUXPWROK PM_BATLOW# PM_C3_STAT#/GPIO21 PM_CLKRUN#/GPIO24 PM_DPRSLPVR PM_PWRBTN# PM_PWROK PM_RI# PM_RSMRST# PM_SLP_S1#/GPIO19 PM_SLP_S3# PM_SLP_S5# PM_STPCPU#/GPIO20 PM_STPPCI#/GPIO18 PM_SUS_CLK PM_SUS_STAT# PM_THRM# Unmuxed GPIO_7 GPIO GPIO_8 GPIO_12 Power GPIO_13 Management GPIO_25 GPIO_27 GPIO_28 IDE_PDCS1# IDE_PDCS3# IDE_SDCS1# IDE_SDCS3# IDE_PDA0 IDE_PDA1 IDE_PDA2 IDE_SDA0 IDE_SDA1 IDE_SDA2 IDE_PDD0 IDE_PDD1 IDE_PDD2 IDE_PDD3 IDE_PDD4 IDE_PDD5 IDE_PDD6 IDE_PDD7 IDE_PDD8 IDE_PDD9 IDE_PDD10 IDE_PDD11 IDE_PDD12 IDE_PDD13 IDE_PDD14 IDE_PDD15 IDE_SDD0 IDE_SDD1 IDE_SDD2 IDE_SDD3 IDE_SDD4 IDE_SDD5 IDE_SDD6 IDE_SDD7 IDE_SDD8 IDE_SDD9 IDE_SDD10 IDE_SDD11 IDE_SDD12 IDE_SDD13 IDE_SDD14 IDE_SDD15 V2 W2 Y4 Y2 W3 W4 Y3 AC15 AB15 AC21 AC22 AA14 AC14 AA15 AC20 AA19 AB20 W12 AB11 AA10 AC10 W11 Y9 AB9 AA9 AC9 Y10 W9 Y11 AB10 AC11 AA11 AC12 Y17 W17 AC17 AB16 W16 Y14 AA13 W15 W13 Y16 Y15 AC16 AB17 AA17 Y18 AC18 Y13 Y19 AB12 AB18 AC13 AC19 Y12 AA18 AB13 AB19 J23 F20 Y7 AC7 AC6 AB7 H23 IDE_PDD0 IDE_PDD1 IDE_PDD2 IDE_PDD3 IDE_PDD4 IDE_PDD5 IDE_PDD6 IDE_PDD7 IDE_PDD8 IDE_PDD9 IDE_PDD10 IDE_PDD11 IDE_PDD12 IDE_PDD13 IDE_PDD14 IDE_PDD15 IDE_SDD0 IDE_SDD1 IDE_SDD2 IDE_SDD3 IDE_SDD4 IDE_SDD5 IDE_SDD6 IDE_SDD7 IDE_SDD8 IDE_SDD9 IDE_SDD10 IDE_SDD11 IDE_SDD12 IDE_SDD13 IDE_SDD14 IDE_SDD15 ICH_GPIO7 34 SMC_EXTSMI# 29,31,33,34 SMC_RUNTIME_SCI# 29,33,34 SMC_WAKE_SCI# 29,33,34 AUDIO_PWRDN 24 ICH_MFG_MODE 34 TP_BT_RESET# N\C IDE_PDCS1# IDE_PDCS3# IDE_SDCS1# IDE_SDCS3# IDE_PDA0 IDE_PDA1 IDE_PDA2 IDE_SDA0 IDE_SDA1 IDE_SDA2 23 23 23 23
+V3.3S_ICH R228
4
5,15,17,18,19,20,22,34 NO_STUFF_1K NO_STUFF_10K AC_SPKR AC_SDATAOUT PCI_GNTA# 15,18
J69 1 2
4
R394
R395 NO_STUFF_1K R396 NO_STUFF_1K LAN_EEP_DOUT 15
ICH3-M
PART B
NO_STUFF_MFG-TEST-JUMPER
34,36 PM_GMUXSEL 3,34 PM_CPUPERF# 34,36 VR_PWRGD 24 AC_BITCLK 24 AC_RST# Note: value of R200 24 AC_SDATAIN0 depends on actual 24 AC_SDATAIN1 strength of buffer. 24 AC_SDATAOUT R393 24 AC_SYNC 33 28,29,30,31,34 28,29,30,31,34 28,29,30,31,34 28,29,30,31,34 22,31,34 22,34 28,29,30,31,34 LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 LPC_DRQ#0 LPC_DRQ#1 LPC_FRAME#
PM_GMUXSEL/GPIO23 Geyserville PM_CPUPERF#/GPIO22 PM_VGATE/VRMPWRGD AC_BITCLK AC_RST# AC_SDATAIN0 AC_SDATAIN1 AC_SDATAOUT AC_SYNC LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 LPC_DRQ0# LPC_DRQ1# LPC_FRAME# USB_PP0 USB_PP1 USB_PP2 USB_PP3 USB_PP4 USB_PP5 USB_PN0# USB_PN1# USB_PN2# USB_PN3# USB_PN4# USB_PN5# USB_OC0# USB_OC1# USB_OC2# USB_OC3# USB_OC4# USB_OC5# USB_LEDA0#/GPIO32 USB_LEDA1#/GPIO33 USB_LEDA2#/GPIO34 USB_LEDA3#/GPIO35 USB_LEDA4#/GPIO36 USB_LEDA5#/GPIO37 USB_LEDG0#/GPIO38 USB_LEDG1#/GPIO39 USB_LEDG2#/GPIO40 USB_LEDG3#/GPIO41 USB_LEDG4#/GPIO42 USB_LEDG5#/GPIO43 USB_RBIAS ICH3-M
23 23 23 23 23 23 IDE_PDD[15:0]
23
ICH3M Strapping Options

Function Board Default NO STUFF NO STUFF NO STUFF NO STUFF Optional Override STUFF for No Reboot STUFF for safe mode STUFF for A16 swap override STUFF
AC'97 I/F
IDE I/F
R196 R197 R198

3
No Reboot Safe Mode Boot A16 swap override Reserved
R199
LPC I/F
IDE_SDD[15:0]
23
9,17,18,19,24,25,26,29,32,33,34,39,40
+V3.3ALWAYS
RTC Circuitry
17,22 3 +V_RTC
TP_USB_PP3 N\C
25 USB_PP0 25 USB_PP1 26 USB_PP2 26 26 25 25 26 USB_PP4 USB_PP5 USB_PN0 USB_PN1 USB_PN2
BAT54 1 Q32
TP_USB_PN3 N\C 4 RP104D 1K C409 1UF 2 1
BAT54 1
2
RTC_RST# delay 10-20ms

RTC_RST#
26 USB_PN4 26 USB_PN5 25 25 26 26 26 26 9,34 30 32 28,34 28,34 22 22 22 22,23,34 22,23,34 34 34 USB_OC0# USB_OC1# USB_OC2# USB_OC3# USB_OC4# USB_OC5# AGP_SUSPEND# KSC_VPPEN# SER_EN FWH_WP# FWH_TBL# ICH_FAB_REV0 ICH_FAB_REV1 ICH_FAB_REV2 IDE_PATADET IDE_SATADET ICH_GPIO42 ICH_GPIO43
USB I/F
3 Q27
R298 15K C402 1UF 2
CMOS Settings Clear CMOS Keep CMOS
J75 SHUNT OPEN
J75
R302
IDE_PDDACK# IDE_SDDACK# IDE_PDDREQ IDE_SDDREQ IDE_PDIOR# IDE_SDIOR# IDE_PDIOW# IDE_SDIOW# IDE_PIORDY IDE_SIORDY CLK_14 CLK_48 CLK_RTEST# CLK_RTCX1 CLK_RTCX2 CLK_VBIAS Misc SPKR Clocks
IDE_PDDACK# 23 IDE_SDDACK# 23 IDE_PDDREQ 23 IDE_SDDREQ 23 IDE_PDIOR# 23 IDE_SDIOR# 23 IDE_PDIOW# 23 IDE_SDIOW# 23 IDE_PIORDY 23 IDE_SIORDY 23 CLK_ICH14 14 CLK_ICH48 14 RTC_X1 RTC_X2 RTC_VBIAS AC_SPKR 24
1K
C405 0.047UF
RTC_RST#
Battery IPN is: 202168-001
BH1 Battery_Holder
1 R303 10M
1 R209 2 B21 18.2_1%
C407 10PF Y4 32.768KHZ Value for C251,C252 depends on Xtal 2 1
2 1
RTC_X1
1
R295 10M 2
Title
ICH3-M (2 of 3)
E
C406 10PF
of
42
Design Guide
226
4,5,6,9,10,14,19,23,28,29,30,31,32,33,36,37,40 40 +V1.8ALWAYS R193 2 +V1.8A_ICH 1 C334 10UF +V1.8

4
E +V3.3S
1 R258 U46C C599 0.1UF C624 0.1UF C575 0.1UF E13 F14 K12 P10 V6 V7 F15 F16 F7 F8 K10 AB6 VCC5REF E6 W8 C13 W5 F9 F10 P14 U18 V22 C23 C615 0.1UF C384 0.1UF B23 E7 T21 D6 T1 C2 3 VCCSUS1.8_0 VCCSUS1.8_1 VCCSUS1.8_2 VCCSUS1.8_3 VCCSUS1.8_4 VCCSUS1.8_5 VCCSUS1.8_6 VCCSUS1.8_7 VCCLAN1.8_0 VCCLAN1.8_1 VCCLAN1.8_2 VCCRTC VCC5REF1 VCC5REF2 VCC3.3_0 VCC3.3_1 VCC3.3_2 VCC3.3_3 VCC3.3_4 VCC3.3_5 VCC3.3_6 VCC3.3_7 VCC3.3_8 VCC3.3_9 VCC3.3_10 VCC3.3_11 VCC3.3_12 VCC3.3_13 VCC3.3_14 VCC1.8_0 VCC1.8_1 VCC1.8_2 VCC1.8_3 VCC1.8_4 VCC1.8_5 VCC1.8_6 VCC1.8_7 VCC1.8_8 VCC1.8_9 VCC1.8_10 VCC1.8_11 VCCSUS3.3_0 VCCSUS3.3_1 VCCSUS3.3_2 VCCSUS3.3_3 VCCSUS3.3_4 VCCSUS3.3_5 F6 G6 H6 J6 M10 R6 T6 U6 G18 H18 P12 V15 V16 V17 V18 J18 M14 R18 T18 E11 K6 K18 P6 P18 V10 V14 U19 F17 F18 K14 E10 V8 V9 +V3.3S_ICH 5,15,16,18,19,20,22,34 C608 C607 C601 C399 C371 C614 C605 C400 C616 C610 C620 C375 C377 22UF C401 22UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
4
NO_STUFF_0.01_1%
NO_STUFF_0.01_1% 2 +V3.3S_ICH 5,15,16,18,19,20,22,34 C603 C609 C598 C592 C613 C600 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF +V1.8S 7,8,40 1 R190 NO_STUFF_0.01_1% +V1.8S_ICH 8,15 + C318 100uF C338 C335 22UF 0.1UF C619 0.1UF C606 0.1UF C611 0.1UF C604 0.1UF C552 0.1UF 2 C618 0.1UF 9,16,18,19,24,25,26,29,32,33,34,39,40 +V3.3ALWAYS 1
3
R189
+V1.8_ICHLAN 4,9,19,20,24,31,32,33,35,36,37,40 +V5S C328 5,15,16,18,19,20,22,34 22UF 0.1UF 0.1UF +V3.3S_ICH C595 C596 1 R179 1K Q20 BAT54 16,22 +V_RTC
2 1 NO_STUFF_0.01_1%
ICH3-M
POWER
VCC5REFSUS
C593 1UF
C315 0.1UF
C617 0.1UF
+V3.3 14,19,21,24,27,29,34,36,40 R194 C333 C594 NO_STUFF_0.01_1% 22UF 0.1UF

3
VCC5REFSUS1 VCC5REFSUS2 VCCLAN3.3_0 VCCLAN3.3_1 VCC_CPU_IO_0 VCC_CPU_IO_1 VCC_CPU_IO_2 VCCSUS1.8_8 VCCSUS1.8_9 N/C0 N/C1 N/C2 N/C3 N/C4
15 +V3.3_ICHLAN C549 0.1UF 1 2 C330
4.7UF 3,4,5,7,15,36,37,38 +VCC_CORE R267 2 1 NO_STUFF_0.01_1% C612 1UF
R181 NO_STUFF_0.01_1% +V3.3ALWAYS_ICH 22,34 2 C551 C625 C550 C597 C602 C340 C623 C339 C323 22UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
4,9,19,20,24,31,32,33,35,36,37,40 +V5ALWAYS_ICH 5,15,16,18,19,20,22,34 +V3.3ALWAYS_ICH 1 R180 1K Q21 BAT54 VCC5REFSUS 1 C594 1UF C316 0.1UF C621 0.1UF 3
ICH3-M
F22 G20 G3 H19 J5 K11 K13 K20 K21 K22 K23 L10 L11 L12 L13 L14 L21 L23 L3 M11 M12 M13 M20 M22 N10 N11 N12 N13 N14 N21 N23 N5 P11 P13 P20 P22 R21 R23 R3 R5 T20 T22 T4 V20 V3 W10 W14 W18 W22 W6 W7 Y8
VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103
U46D ICH3-M
ICH3-M
A1 VSS0 A13 VSS1 A16 VSS2 A17 VSS3 A20 VSS4 A21 VSS5 A22 VSS6 A23 VSS7 AA12 VSS8 AA16 VSS9 AA20 VSS10 AA22 VSS11 AA3 VSS12 AA8 VSS13 AB8 VSS14 AC1 VSS15 AC23VSS16 AC8 VSS17 B10 VSS18 B13 VSS19 B14 VSS20 B15 VSS21 B18 VSS22 B19 VSS23 B20 VSS24 B22 VSS25 B8 VSS26 C14 VSS27 C15 VSS28 C16 VSS29 C17 VSS30 C18 VSS31 C19 VSS32 C20 VSS33 C21 VSS34 C22 VSS35 C3 VSS36 C6 VSS37 D13 VSS38 D16 VSS39 D17 VSS40 D20 VSS41 D21 VSS42 D22 VSS43 D9 VSS44 E14 VSS45 E15 VSS46 E18 VSS47 E19 VSS48 E20 VSS49 E5 VSS50 F19 VSS51
VSS
Note: Some of the decoupling Caps may be extra and shall be removed after the first build.
Title
ICH3-M (3 of 3)
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Design Guide
227
+V12S_PCI 19,40 -V12S 19 +V5S_PCI 19

4
19 9,16,17,19,24,25,26,29,32,33,34,39,40
19,40 -V12S +V12S_PCI 19 9,16,17,19,24,25,26,29,32,33,34,39,40 +V3.3ALWAYS B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 TRST# -12V +12V TCK TMS GND1 TDI TDO +5V (7) +5V (1) INTA# +5V (2) INTC# INTB# +5V (8) INTD# RSV3 PRSNT1# +5V (9) RSV1 RSV4 PRSNT2# GND14 GND2 GND15 GND3 RSV5 RSV2 RST# GND4 +5V (10) CLK GNT# GND5 GND16 REQ# PME# +5V (3) AD30 AD31 +3.3V (7) AD29 AD28 GND6 AD26 AD27 GND17 AD25 AD24 +3.3V (1) IDSEL C/BE3# +3.3V (8) AD23 AD22 GND8 AD20 AD21 GND18 AD19 AD18 +3.3V (2) AD16 AD17 +3.3V (9) C/BE2# FRAME# GND9 GND19 IRDY# TRDY# +3.3V (3) GND20 DEVSEL# STOP# GND10 +3.3V (10) LOCK# SDONE PERR# SBO# +3.3V (4) GND21 SERR# PAR +3.3V (5) AD15 C/BE1# +3.3V (11) AD14 AD13 GND11 AD11 AD12 GND22 AD10 AD09 GND12 KEY C/BE0# AD08 +3.3V (12) AD07 AD06 +3.3V (6) AD04 AD05 GND23 AD03 AD02 GND13 AD00 AD01 +5V (11) +5V (4) REQ64# ACK64# +5V (12) +5V (5) +5V (13) +5V (6) J32 10K CON120_PCI 10K
+V3.3ALWAYS
19 +V3.3S_PCI +V5_PCI 9,15,19,20,22 INT_PIRQB# INT_PIRQD# 15,19,20,22 C103 0.01UF SLT1_PRSNT1# C116 SLT1_PRSNT2#
0.01UF 15,19,20,29,31,34 INT_SERIRQ 14 CLK_PCI_SLOT1 15,22 PCI_REQ1# 15,19,20 PCI_AD31 15,19,20 PCI_AD29 15,19,20 PCI_AD27 15,19,20 PCI_AD25 15,19,20 PCI_C/BE3# 15,19,20 PCI_AD23 15,19,20 PCI_AD21 15,19,20 PCI_AD19 15,19,20 PCI_AD17 15,19,20 PCI_C/BE2# 15,19,20,22 PCI_IRDY# 15,19,20,22 PCI_DEVSEL# 15,19,20,22 PCI_LOCK# 15,19,22 PCI_PERR# 15,19,20,22 PCI_SERR# 15,19,20 PCI_C/BE1# 15,19,20 PCI_AD14 15,19,20 PCI_AD12 15,19,20 PCI_AD10
2
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62
TRST# -12V +12V TCK TMS GND1 TDI TDO +5V (7) +5V (1) INTA# +5V (2) INTC# INTB# +5V (8) INTD# RSV3 PRSNT1# +5V (9) RSV1 RSV4 PRSNT2# GND14 GND2 GND15 GND3 RSV5 RSV2 RST# GND4 +5V (10) CLK GNT# GND5 GND16 REQ# PME# +5V (3) AD30 AD31 +3.3V (7) AD29 AD28 GND6 AD26 AD27 GND17 AD25 AD24 +3.3V (1) IDSEL C/BE3# +3.3V (8) AD23 AD22 GND8 AD20 AD21 GND18 AD19 AD18 +3.3V (2) AD16 AD17 +3.3V (9) C/BE2# FRAME# GND9 GND19 IRDY# TRDY# +3.3V (3) GND20 DEVSEL# STOP# GND10 +3.3V (10) LOCK# SDONE PERR# SBO# +3.3V (4) GND21 SERR# PAR +3.3V (5) AD15 C/BE1# +3.3V (11) AD14 AD13 GND11 AD11 AD12 GND22 AD10 AD09 GND12 KEY C/BE0# AD08 +3.3V (12) AD07 AD06 +3.3V (6) AD04 AD05 GND23 AD03 AD02 GND13 AD00 AD01 +5V (11) +5V (4) REQ64# ACK64# +5V (12) +5V (5) +5V (13) +5V (6) J33 CON120_PCI
19 +V5_PCI +V5S_PCI 19 19 +V5S_PCI A1 +V3.3S_PCI 19 A2 19 +V3.3S_PCI A3 A4 15,19,20,22 INT_PIRQC# A5 A6 INT_PIRQA# 9,15,19,20,22 INT_PIRQA# 9,15,19,20,22 A7 INT_PIRQC# 15,19,20,22 A8 SLT2_PRSNT1# C434 A9 PCI_CLKRUN# 19,20 A10 0.01UF C114 SLT2_PRSNT2# A11 PCI_GATED_RST# 9,19,29,34 A12 0.01UF A13 A14 15,19,20,29,31,34 INT_SERIRQ A15 PCI_RST_SLOTS# 9,15,19 A16 14 CLK_PCI_SLOT2 A17 PCI_GNT1# 15 A18 15,22 PCI_REQ2# A19 PCI_PME# 9,15,19,22,34 A20 PCI_AD30 15,19,20 15,19,20 PCI_AD31 A21 15,19,20 PCI_AD29 A22 PCI_AD28 15,19,20 A23 PCI_AD26 15,19,20 15,19,20 PCI_AD27 A24 15,19,20 PCI_AD25 A25 PCI_AD24 15,19,20 A26 SLT1_IDSEL PCI_AD25 15,19,20 15,19,20 PCI_C/BE3# R96 100 A27 15,19,20 PCI_AD23 A28 PCI_AD22 15,19,20 A29 PCI_AD20 15,19,20 15,19,20 PCI_AD21 A30 15,19,20 PCI_AD19 A31 PCI_AD18 15,19,20 A32 PCI_AD16 15,19,20 15,19,20 PCI_AD17 A33 15,19,20 PCI_C/BE2# A34 PCI_FRAME# 15,19,20,22 A35 15,19,20,22 PCI_IRDY# A36 PCI_TRDY# 15,19,20,22 A37 15,19,20,22 PCI_DEVSEL# A38 PCI_STOP# 15,19,20,22 A39 15,19,20,22 PCI_LOCK# A40 15,19,22 PCI_PERR# A41 A42 15,19,20,22 PCI_SERR# A43 PCI_PAR 15,19,20 A44 PCI_AD15 15,19,20 15,19,20 PCI_C/BE1# A45 15,19,20 PCI_AD14 A46 PCI_AD13 15,19,20 A47 PCI_AD11 15,19,20 15,19,20 PCI_AD12 A48 15,19,20 PCI_AD10 A49 PCI_AD9 15,19,20 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 PCI_C/BE0# 15,19,20 PCI_AD6 15,19,20 PCI_AD4 15,19,20 PCI_AD2 15,19,20 PCI_AD0 15,19,20 PCI_REQ64# 22 15,19,20 PCI_AD8 15,19,20 PCI_AD7 15,19,20 PCI_AD5 15,19,20 PCI_AD3 15,19,20 PCI_AD1 5,15,16,17,19,20,22,34 +V3.3S_ICH R458
+V5S_PCI 19 A1 A2 +V3.3S_PCI 19 A3 A4 A5 A6 INT_PIRQB# 9,15,19,20,22 A7 INT_PIRQD# 15,19,20,22 A8 A9 PCI_CLKRUN# 19,20 A10 A11 PCI_GATED_RST# 9,19,29,34 A12 A13 A14 A15 PCI_RST_SLOTS# 9,15,19 A16 A17 PCI_GNT2# 15 A18 A19 PCI_PME# 9,15,19,22,34 A20 PCI_AD30 15,19,20 A21 A22 PCI_AD28 15,19,20 A23 PCI_AD26 15,19,20 A24 A25 PCI_AD24 15,19,20 A26 SLT2_IDSEL R95 100 A27 A28 PCI_AD22 15,19,20 A29 PCI_AD20 15,19,20 A30 A31 PCI_AD18 15,19,20 A32 PCI_AD16 15,19,20 A33 A34 PCI_FRAME# 15,19,20,22 A35 A36 PCI_TRDY# 15,19,20,22 A37 A38 PCI_STOP# 15,19,20,22 A39 A40 A41 A42 A43 PCI_PAR 15,19,20 A44 PCI_AD15 15,19,20 A45 A46 PCI_AD13 15,19,20 A47 PCI_AD11 15,19,20 A48 A49 PCI_AD9 15,19,20 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 PCI_C/BE0# 15,19,20 PCI_AD6 15,19,20 PCI_AD4 15,19,20 PCI_AD2 15,19,20 PCI_AD0 15,19,20 5,15,16,17,19,20,22,34 +V3.3S_ICH
15,19,20 PCI_AD8 15,19,20 PCI_AD7 15,19,20 PCI_AD5 15,19,20 PCI_AD3 15,19,20 PCI_AD1 22 PCI_ACK64#
R459
SLOT1
5,15,16,17,19,20,22,34 +V3.3S_ICH R178 8.2K 2 4 6 R177 8.2K +V3.3S_ICH 5,15,16,17,19,20,22,34 PCI_REQA# 15 INT_SERIRQ 15,19,20,29,31,34 19,24,25,26,34,39,40 +V5 R333 NO_STUFF_0 +V5_PCI 19
SLOT2
J48 15,16 PCI_GNTA#

1
1 5
LEGACY HEADER FOR ADD-IN AUDIO CARD TESTING VIA SLOT1 ONLY
5Pin_Keyed-HDR
Title
PCI Slot 1 & 2

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Design Guide
228
18,40 +V3.3S_PCI R93 0 14,17,21,24,27,29,34,36,40

4
-V12S +V5PCISLT3 +V3.3ALWAYS +V12S_PCI 18 +V3.3PCISLT3 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 TRST# -12V +12V TCK TMS GND1 TDI TDO +5V (7) +5V (1) INTA# +5V (2) INTC# INTB# +5V (8) INTD# RSV3 PRSNT1# +5V (9) RSV1 RSV4 PRSNT2# GND14 GND2 GND15 GND3 RSV5 RSV2 RST# GND4 +5V (10) CLK GNT# GND5 GND16 REQ# PME# +5V (3) AD30 AD31 +3.3V (7) AD29 AD28 GND6 AD26 AD27 GND17 AD25 AD24 +3.3V (1) IDSEL C/BE3# +3.3V (8) AD23 AD22 GND8 AD20 AD21 GND18 AD19 AD18 +3.3V (2) AD16 AD17 +3.3V (9) C/BE2# FRAME# GND9 GND19 IRDY# TRDY# +3.3V (3) GND20 DEVSEL# STOP# GND10 +3.3V (10) LOCK# SDONE PERR# SBO# +3.3V (4) GND21 SERR# PAR +3.3V (5) AD15 C/BE1# +3.3V (11) AD14 AD13 GND11 AD11 AD12 GND22 AD10 AD09 GND12 KEY C/BE0# AD08 +3.3V (12) AD07 AD06 +3.3V (6) AD04 AD05 GND23 AD03 AD02 GND13 AD00 AD01 +5V (11) +5V (4) REQ64# ACK64# +5V (12) +5V (5) +5V (13) +5V (6) J31 CON120_PCI 10K A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 SLT3_IDSEL A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 2 RP15B 7 INT_PIRQA# 9,15,18,20,22 0 2 RP54B 7 INT_PIRQG# 15,22 NO_STUFF_0 4,5,6,9,10,14,17,23,28,29,30,31,32,33,36,37,40 +V3.3S C626 100PF
4
18
+V5_PCI 18
+V3.3PCISLT3 9,16,17,18,24,25,26,29,32,33,34,39,40 +V5PCISLT3
1 RP15A 8 0 1 RP54A 8 NO_STUFF_0
INT_PIRQC# 15,18,20,22 INT_PIRQE# 15,22
+V3.3 R89 NO_STUFF_0
15,18,20,22
INT_PIRQD#
15,22 INT_PIRQF# 9,15,18,20,22 INT_PIRQB# 15,22,34 INT_PIRQH#
6 0 6 RP54C NO_STUFF_0 4 5 RP15D 0 4 5 RP54D NO_STUFF_0 18 +V5S_PCI R85 0 RP15C 3 +V5 R70 NO_STUFF_0
PCI_SLT3INTB# PCI_SLT3INTD# C436 0.01UF SLT3_PRSNT1# C120 SLT3_PRSNT2# 0.01UF 15,18,20,29,31,34 INT_SERIRQ 14 CLK_PCI_SLOT3 15,22 PCI_REQ3# 15,18,20 PCI_AD31 15,18,20 PCI_AD29
PCI_SLT3INTA# PCI_SLT3INTC# PCI_CLKRUN# 18,20 PCI_GATED_RST# 9,18,29,34
R425 56
18,24,25,26,34,39,40
PCI_RST_SLOTS# 9,15,18 PCI_GNT3# 15 PCI_PME# 9,15,18,22,34 PCI_AD30 15,18,20 PCI_AD28 15,18,20 PCI_AD26 15,18,20
Place AC termination VERY close to J31 PIN A15
15,18,20 PCI_AD27 15,18,20 PCI_AD25 +V5PCISLT3 Place close to slot 3 C124 22UF +V3.3PCISLT3 Place close to slot 3 C196 22UF C180 22UF C140 0.1UF C233 0.1UF C151 0.1UF C228 0.1UF C188 0.1UF C256 0.1UF C90 0.1UF C264 0.1UF C94 0.1UF 15,18,20 PCI_C/BE3# 15,18,20 PCI_AD23 15,18,20 PCI_AD21 15,18,20 PCI_AD19 15,18,20 PCI_AD17 15,18,20 PCI_C/BE2# 15,18,20,22 PCI_IRDY# 15,18,20,22 PCI_DEVSEL# 15,18,20,22 PCI_LOCK# 15,18,22 PCI_PERR# 15,18,20,22 PCI_SERR# +V5S 1 4,9,17,20,24,31,32,33,35,36,37,40 Layout Note: Place half of these caps by PCI slot 1, the other half by PCI slot2 +V5S_PCI 18 15,18,20 PCI_C/BE1# 15,18,20 PCI_AD14 15,18,20 PCI_AD12 15,18,20 PCI_AD10
R100
PCI_AD24 15,18,20 PCI_AD27 15,18,20 100 PCI_AD22 15,18,20 PCI_AD20 15,18,20 PCI_AD18 15,18,20 PCI_AD16 15,18,20 PCI_FRAME# 15,18,20,22 PCI_TRDY# 15,18,20,22 PCI_STOP# 15,18,20,22 SMLINK0 15,22 SMLINK1 15,22 PCI_PAR 15,18,20 PCI_AD15 15,18,20 PCI_AD13 15,18,20 PCI_AD11 15,18,20 PCI_AD9 15,18,20 PCI_C/BE0# 15,18,20 PCI_AD6 15,18,20 PCI_AD4 15,18,20 PCI_AD2 15,18,20 PCI_AD0 15,18,20 +V3.3S_ICH 5,15,16,17,18,20,22,34
2
R127 NO_STUFF_0.01_1% 2
15,18,20 PCI_AD8 15,18,20 PCI_AD7 C262 0.1UF C125 0.1UF C134 0.1UF C126 0.1UF 15,18,20 PCI_AD5 15,18,20 PCI_AD3 15,18,20 PCI_AD1 5,15,16,17,18,20,22,34 +V3.3S_ICH R456
C259 22UF
C111 22UF
C85 22UF
C258 22UF
C70 0.1UF
C82 0.1UF
C83 0.1UF
C257 0.1UF
C112 0.1UF
C137 0.1UF
C100 0.1UF
C255 0.1UF
C249 0.1UF
C92 0.1UF
R457
10K +V3.3S 4,5,6,9,10,14,17,23,28,29,30,31,32,33,36,37,40 1 9,22,34,35,40 +V12S +V12S_PCI
SLOT3
18
R122 NO_STUFF_0.01_1% +V3.3S_PCI 2 C231 22UF C232 22UF C177 0.1UF 18 C189 0.1UF C165 0.1UF C182 0.1UF C176 0.1UF C168 0.1UF C142 0.1UF C143 0.1UF C169 0.1UF C230 0.1UF
R47
2 1 NO_STUFF_0.01_1% C219 0.1UF C229 0.1UF C79 C74 10UF 0.1UF 0.1UF C72
Title
PCI Slot 3 & Decoupling

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Design Guide
229
Qbuffers used for isolation during suspend as well as 5V->3.3V translation 1 15,18,19 PCI_AD[31:0] PCI_AD22 PCI_AD23 PCI_AD26 PCI_AD27 PCI_AD30 PCI_AD31 PCI_AD29 PCI_AD28 PCI_AD25 PCI_AD24 PCI_AD12 PCI_AD14 PCI_AD15 PCI_AD18 PCI_AD19 PCI_AD21 PCI_AD20 PCI_AD17 PCI_AD16 PCI_AD13 2 3 4 5 6 7 9 10 11 12 13 14 16 18 19 20 21 22 23 24 48 47
U19 NC 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 1A9 1A10 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 2A9 2A10 1OE# 2OE# VCC 1B1 1B2 1B3 1B4 1B5 1B6 1B7 1B8 1B9 1B10 2B1 2B2 2B3 2B4 2B5 2B6 2B7 2B8 2B9 2B10 GND1 GND2 GND3 GND4 15 46 45 44 43 42 40 39 38 37 36 35 34 33 31 30 29 28 27 26 25 8 17 32 41 DOCK_AD22 DOCK_AD23 DOCK_AD26 DOCK_AD27 DOCK_AD30 DOCK_AD31 DOCK_AD29 DOCK_AD28 DOCK_AD25 DOCK_AD24 DOCK_AD12 DOCK_AD14 DOCK_AD15 DOCK_AD18 DOCK_AD19 DOCK_AD21 DOCK_AD20 DOCK_AD17 DOCK_AD16 DOCK_AD13
+V5S_QSPWR
+V5S 4,9,17,19,24,31,32,33,35,36,37,40 R121 100K DOCK_QDEN# 21 Q12 2
C466 C123 22UF 0.1UF
BSS84 1
+V3.3S_ICH R180 8.2K
5,15,16,17,18,19,22,34 +V5S_QSPWR U17 1 NC 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 1A9 1A10 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 2A9 2A10 1OE# 2OE# VCC 1B1 1B2 1B3 1B4 1B5 1B6 1B7 1B8 1B9 1B10 2B1 2B2 2B3 2B4 2B5 2B6 2B7 2B8 2B9 2B10 GND1 GND2 GND3 GND4 15 46 45 44 43 42 40 39 38 37 36 35 34 33 31 30 29 28 27 26 25 8 17 32 41 C129 DOCK_GNTB# 21 DOCK_REQB# 21 DOCK_SERIRQ 21 DOCK_PIRQA# 21 DOCK_PIRQB# 21 DOCK_PIRQC# 21 DOCK_PIRQD# 21 DOCK_SERR# 21 DOCK_PAR 21 DOCK_IRDY# 21 DOCK_DEVSEL# 21 DOCK_STOP# 21 DOCK_TRDY# 21 DOCK_LOCK# 21 DOCK_FRAME# 21 DOCK_C/BE3# 21 DOCK_C/BE2# 21 DOCK_C/BE1# 21 DOCK_C/BE0# 21 0.1UF
4
21 DOCK_QPCIEN#
74CBTD16210
3
DOCK_AD[31:0] 21
15 PCI_GNTB# 15 PCI_REQB# 15,18,19,29,31,34 INT_SERIRQ 9,15,18,19,22 INT_PIRQA# 9,15,18,19,22 INT_PIRQB# 15,18,19,22 INT_PIRQC# 15,18,19,22 INT_PIRQD# 15,18,19,22 PCI_SERR# 15,18,19 PCI_PAR 15,18,19,22 PCI_IRDY# 15,18,19,22 PCI_DEVSEL# 15,18,19,22 PCI_STOP# 15,18,19,22 PCI_TRDY# 15,18,19,22 PCI_LOCK# 15,18,19,22 PCI_FRAME# 15,18,19 PCI_C/BE3# 15,18,19 PCI_C/BE2# 15,18,19 PCI_C/BE1# 15,18,19 PCI_C/BE0# DOCK_QPCIEN#
2 3 4 5 6 7 9 10 11 12 13 14 16 18 19 20 21 22 23 24 48 47
+V5S_QSPWR U21 1 PCI_AD2 PCI_AD3 PCI_AD6 PCI_AD7 PCI_AD10 PCI_AD11 PCI_AD9 PCI_AD8 PCI_AD5 PCI_AD4 10,14,15,22 SMB_DATA PCI_AD1 PCI_AD0 10,14,15,22 SMB_CLK 2 3 4 5 6 7 9 10 11 12 13 14 16 18 19 20 21 22 23 24 48 47 NC 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 1A9 1A10 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 2A9 2A10 1OE# 2OE# VCC 1B1 1B2 1B3 1B4 1B5 1B6 1B7 1B8 1B9 1B10 2B1 2B2 2B3 2B4 2B5 2B6 2B7 2B8 2B9 2B10 GND1 GND2 GND3 GND4 15 46 45 44 43 42 40 39 38 37 36 35 34 33 31 30 29 28 27 26 25 8 17 32 41 DOCK_AD2 DOCK_AD3 DOCK_AD6 DOCK_AD7 DOCK_AD10 DOCK_AD11 DOCK_AD9 DOCK_AD8 DOCK_AD5 DOCK_AD4 DOCK_AD1 DOCK_AD0 C494 0.1UF
74CBTD16210
+V5S_QSPWR U61 1 DOCK_SMBDATA 21 2 3 4 5 6 7 9 10 11 12 13 14 16 18 19 20 21 22 23 24 48 47 NC 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 1A9 1A10 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 2A9 2A10 1OE# 2OE# VCC 1B1 1B2 1B3 1B4 1B5 1B6 1B7 1B8 1B9 1B10 2B1 2B2 2B3 2B4 2B5 2B6 2B7 2B8 2B9 2B10 GND1 GND2 GND3 GND4 15 46 45 44 43 42 40 39 38 37 36 35 34 33 31 30 29 28 27 26 25 8 17 32 41 C646 0.1UF DOCK_KBDCLK 21 DOCK_KBDDATA 21
2
DOCK_SMBCLK 21 33 KBD_CLK 33 KBD_DATA 33 MOUSE_DATA 33 MOUSE_CLK 31,32 31,32 31,32 31,32 31,32 31,32 31,32 31,32 SER_RIA# SER_SOUTA SER_SINA SER_RTSA# SER_DSRA# SER_CTSA# SER_DTRA# SER_DCDA#
DOCK_MOUSEDATA 21 DOCK_MOUSECLK 21
DOCK_QPCIEN#
74CBTD16210
QUIET DOCK QSWITCH

U22 4,15,28,29,30,31,34 PCI_RST_ONBD# 3 4 7 8 11 14 17 18 21 22 1 13 1A1 1A2 1A3 1A4 1A5 2A1 2A2 2A3 2A4 2A5 1OE# 2OE# VCC 1B1 1B2 1B3 1B4 1B5 2B1 2B2 2B3 2B4 2B5 GND 24 2 5 6 9 10 15 16 19 20 23 12
+V5S_QSPWR
DOCK_SERRIA# 21 DOCK_SOUTA 21 DOCK_SINA 21 DOCK_RTSA# 21 DOCK_DSRA# 21 DOCK_CTSA# 21 DOCK_DTRA# 21 DOCK_DCDA# 21
C495 DOCK_RESET# 21 DOCK_CLKRUN# 21 0.1UF Local Mouse and Keyboard cannot be used if the Docking Keyboard and Mouse are used. BIOS will disable local Serial port via SER_EN if Docking board is used.
18,19 PCI_CLKRUN#
74CBTD16210
15 PCI_GNT4# 15,22 PCI_REQ4# 14 CLK_DOCKPCI 29,33,34 DOCK_INTR#
DOCK_GNT4# 21 DOCK_REQ4# 21 CLK_DOCKCONNPCI 21 DOCK_DOCKINTR# 21
Title
Bus-Switch-74CBT3384 R124 100
Docking Q-Switches
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Design Guide
230
A
200 199 150 149
J35A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 GND0 V_DC0 V_DC1 GND1 GND2 RED_RTN RED VSYNC HSYNC GND3 GND4 NC0 SM_DATA SYSACT# CLKRUN# PC_REQ# GND5 CD2 NC1 NC2 CD3#/GND INTD# INTC# GND6 GNT# REQ# GND7 PERR# SERR# GND8 STOP# TRDY# GND9 LOCK# FRAME# GND10 C/BE1# C/BE0# GND11 AD29 AD28 GND12 AD25 AD24 GND13 AD21 AD20 GND14 V_ACDC0 V_ACDC1 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 DOCK_REQ4# 20 DOCK_SERR# 20 DOCK_STOP# 20 DOCK_TRDY# 20 DOCK_LOCK# 20 DOCK_FRAME# 20 DOCK_C/BE1# 20 DOCK_C/BE0# 20 DOCK_AD29 DOCK_AD28 DOCK_AD25 DOCK_AD24 DOCK_AD21 DOCK_AD20 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125
J35C 3V GND30 NC7 GND31 AD17 AD16 GND32 AD13 AD12 GND33 AD9 AD8 GND34 AD5 AD4 GND35 AD1 AD0 GND36 PCI_CLK GND37 SLCTIN# PLT_AFD# PLT_PE GND38 LPT_BUSY LPT_D5 LPT_D4 GND39 ERROR# LPT_D1 LPT_D0 GND40 SER_OUT SER_RTS SER_CTS SER_DTR MS_DATA MS_CLK GND41 L_LININ LIN_GND R_LININ NC8 MIDI_SRX MIDI_STX USB+ USBGND42 DCKINTR# 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150
151 102
100
152
5049
101
DOCK_AD17 DOCK_AD16 DOCK_AD13 DOCK_AD12 DOCK_AD9 DOCK_AD8 DOCK_AD5 DOCK_AD4 DOCK_AD1 DOCK_AD0 20 CLK_DOCKCONNPCI
52 2 1 51
20 DOCK_SMBDATA 20 DOCK_CLKRUN# 20 DOCK_REQB#
DOCK_SOUTA 20 DOCK_RTSA# 20 DOCK_CTSA# 20 DOCK_DTRA# 20 DOCK_MOUSEDATA 20 DOCK_MOUSECLK 20
20 DOCK_PIRQC# 20 DOCK_PIRQB# 20 DOCK_GNT4#
DOCK_USBP5P 26 DOCK_USBP5N 26 DOCK_DOCKINTR# 20
200Pin_Docking-Plug
3
200Pin_Docking-Plug
3
J35D 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 5V0 5V1 NC9 GND43 AD15 AD14 GND44 AD11 AD10 GND45 AD7 AD6 GND46 AD3 AD2 GND47 SRBTN# QDEN# QPCIEN# NBPWROK DPWRSW NC10 LPT_SLCT LPT_STB# CD4#/GND LPT_ACK# LPT_D7 LPT_D6 GND48 LPT_INIT# LPT_D3 LPT_D2 GND49 SER_RD SER_DSR SER_RI SER_DCD KB_DATA KB_CLK NC11 L_INOUT L_O_GND R_INOUT NC12 MICIN MIC_GND 5V_USB GND_USB SUSTAT# CD1# 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200
20 DOCK_AD[31:0] J35B 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 V_DC2 V_DC3 GND15 GND16 GRN_RTN GREEN BLU_RTN BLUE DDC_DAT DDC_CLK GND17 GND18 SM_CLK SERINT NC3 PC_GNT# GND19 NC4 NC5 NC6 GND20 INTB# INTA# GND21 UNDKRQ# UNDKGT# GND22 PAR PCI_RST# GND23 IRDY# DEVSEL# GND24 C/BE3# C/BE2# GND25 AD31 AD30 GND26 AD27 AD26 GND27 AD23 AD22 GND28 AD19 AD18 GND29 V_ACDC2 V_ACDC3 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 DOCK_AD15 DOCK_AD14 DOCK_PAR 20 DOCK_RESET# 20 DOCK_IRDY# 20 DOCK_DEVSEL# 20 DOCK_C/BE3# 20 DOCK_C/BE2# 20 DOCK_AD31 DOCK_AD30 DOCK_AD27 DOCK_AD26 DOCK_AD23 DOCK_AD22 DOCK_AD19 DOCK_AD18 20 DOCK_QDEN# 20 DOCK_QPCIEN# DOCK_AD11 DOCK_AD10 DOCK_AD7 DOCK_AD6 DOCK_AD3 DOCK_AD2
DOCK_SINA 20 DOCK_DSRA# 20 DOCK_SERRIA# 20 DOCK_DCDA# 20 DOCK_KBDDATA 20 DOCK_KBDCLK 20
20 DOCK_SMBCLK 20 DOCK_SERIRQ
2
PM_RI# 16,22,32,34 Q43 BAR43 14,17,19,24,27,29,34,36,40 +V3.3 3

2
20 DOCK_GNTB#
20 DOCK_PIRQA# 20 DOCK_PIRQD#
200Pin_Docking-Plug Q13 14,16,29,34,39,40 PM_SLP_S3# BAR43 DOCK_SUSTAT# There is pull-up on docking station.
200Pin_Docking-Plug
1 Q44 BSS138 2 DOCK_SERRIA#
+V3.3ALWAYS_KBC
29,30 0.1UF
C422 14 16,29,34,36 PM_PWROK

1
U7C 8 SPWRGD Gate used to buffer PM_PWROK to docking 74HC08

1
9 10 7
Title
Docking Connector
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Design Guide
231
Layout Note: Signals on RPs shown below can be swapped to aid routing.
5,15,16,17,18,19,20,34
+V3.3S_ICH
15,18,19,20 15,18,19,20 15,18,19,20 15,18,19,20

4
PCI_FRAME# PCI_IRDY# PCI_TRDY# PCI_STOP# PCI_SERR# PCI_DEVSEL# PCI_PERR# PCI_LOCK# PCI_REQ0# PCI_REQ1# PCI_REQ2# PCI_REQ3# PCI_REQ4# INT_IRQ14
RP93A RP96B RP94D RP94C RP94B RP94A RP96C RP96D
1 2 4 3 2 1 3 4
8 7 5 6 7 8 6 5
8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K +V3.3ALWAYS_ICH 16,21,32,34 PM_RI# 15,34 SMB_ALERT# 9,15,18,19,34 PCI_PME# RP98C 3 RP101A 1 R419 10K 6 10K 8 10K 17,34
4
15,18,19,20 15,18,19,20 15,18,19 15,18,19,20 15
RP93D 4 RP93B RP75A RP96A RP93C 2 1 1 3
5 8.2K 7 8 8 6 8.2K 8.2K 8.2K 8.2K
15,18 15,18 Pull-ups for PCI_GNT#0 15,19 and PCI_GNT#3 are by 15,20 PCI slots 15,23,34
+V_RTC 15,34 SM_INTRUDER# R307 100K
16,17
RP103D 4 RP103A 1 RP87B 2 RP87A 1 RP87C 3 RP87D 4 RP42A RP42B RP42C RP42D RP21A RP21B 1 2 3 4 1 2
5 8.2K 8 8.2K 7 8.2K 8 8.2K 6 8.2K 5 8.2K 8 7 6 5 8 7 8.2K 8.2K 8.2K 8.2K 10K 10K
15,23,34 INT_IRQ15 9,15,18,19,20 INT_PIRQA# 9,15,18,19,20 INT_PIRQB# 15,18,19,20 INT_PIRQC# 15,18,19,20 INT_PIRQD# 15,19 15,19 15,19 15,19,34 18 18 INT_PIRQE# INT_PIRQF# INT_PIRQG# INT_PIRQH# PCI_REQ64# PCI_ACK64#
010 = 3 binary = Sheeks Fab 3
FAB REVISION 5,15,16,17,18,19,20,34

R400 NO_STUFF_10K R401 10K
+V3.3S_ICH
3
R413 10K
16,23,34 IDE_PATADET 16,23,34 IDE_SATADET 16,29,31,34 PM_CLKRUN# 16,31,34 LPC_DRQ#0 16,34 LPC_DRQ#1
1 2
RP105A RP105B
8 NO_STUFF_10K 7 NO_STUFF_10K
16 ICH_FAB_REV0 16 ICH_FAB_REV1 16 ICH_FAB_REV2 R414 1K R415 NO_STUFF_1K R399 NO_STUFF_1K
4 RP99D 5 10K R259 NO_STUFF_10K R260 NO_STUFF_10K DRQ0# & DRQ1# have weak internal pullups +V3.3ALWAYS_ICH 7 17,34
RP101B
AOL II LAN SUPPORT
R292 4.7K 2 3
10K
2
SMLINK0 15,19 BSS138 Q31
9,19,34,35,40
+V12S 1 2
17,34 +V3.3ALWAYS_ICH 6
SMB_CLK 10,14,15,20
R296 4.7K 3
RP101C 10K
Q1 and Q2 connect SMLINK and SMBUS in S0 for SMBus 2.0 compliance.
SMLINK1 15,19
9,19,34,35,40
+V12S 1 2
BSS138 Q29
1
SMB_DATA 10,14,15,20 +V3.3S_ICH
5,15,16,17,18,19,20,34 4 3 2 1
Title
J68
ICH3-M Pullups and Testpoints

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Design Guide
232
IDE_D_PRST#
24 IDE_PRI_RST#
R28947
IDE_PDD[15:0]
16
PRIMARY HDD CONN

J71 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 22 24 26 28 30 32 34 36 38 40 IDE_PDD8 IDE_PDD9 IDE_PDD10 IDE_PDD11 IDE_PDD12 IDE_PDD13 IDE_PDD14 IDE_PDD15
4
16 IDE_PDD[15:0]
4,5,6,9,10,14,17,19,28,29,30,31,32,33,36,37,40
+V3.3S 3 RP100C 6 4.7K 16 IDE_PDDREQ 16 IDE_PDIOW# 16 IDE_PDIOR# 16 IDE_PIORDY 16 IDE_PDDACK# 15,22,34 INT_IRQ14 16 IDE_PDA1 16 IDE_PDA0 16 IDE_PDCS1# 24,40 IDE_PDACTIVE#
IDE_PDD7 IDE_PDD6 IDE_PDD5 IDE_PDD4 IDE_PDD3 IDE_PDD2 IDE_PDD1 IDE_PDD0
IDE_PD_CSEL R286 470 IDE_PATADET 16,22,34 R420 0.047UF
20x2-HDR
3
16 IDE_PDCS3# 16 IDE_PDA2 IDE_D_SRST# 24 IDE_SEC_RST# R290 47
SECONDARY HDD CONN

J65 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 22 24 26 28 30 32 34 36 38 40 IDE_SDD8 IDE_SDD9 IDE_SDD10 IDE_SDD11 IDE_SDD12 IDE_SDD13 IDE_SDD14 IDE_SDD15 IDE_SDD[15:0] 16
16 IDE_SDD[15:0]
4,5,6,9,10,14,17,19,28,29,30,31,32,33,36,37,40
+V3.3S 4 RP100D 5 4.7K 16 IDE_SDDREQ 16 IDE_SDIOW# 16 IDE_SDIOR# 16 IDE_SIORDY 16 IDE_SDDACK# 15,22,34 INT_IRQ15 16 IDE_SDA1 16 IDE_SDA0 16 IDE_SDCS1# 24 IDE_SDACTIVE#
IDE_SDD7 IDE_SDD6 IDE_SDD5 IDE_SDD4 IDE_SDD3 IDE_SDD2 IDE_SDD1 IDE_SDD0
IDE_SD_CSEL IDE_SD_DIAG
R288 470 IDE_SATADET 16,22,34 R287 0.047UF
20x2-HDR
16 IDE_SDCS3# 16 IDE_SDA2
Title
IDE 1 of 2
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Design Guide
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Primary IDE Power

+V5S_IDE_P C366 Q21 1N4148 R221 100K 3 0.1UF 14 U40A 2 IDE_PRST 74HC14 7 3 U40B 4 74HC14 7 IDE_PRI_RST# 23 34,40 IDE_PPWR_EN 74HC14 7 4,9,17,19,20,31,32,33,35,36,37,40 R240 1M U40E 10 R239 100K IDE_PPWR2 14 14 C369 1000PF 2 1 4 3 U45B 11 U45A SI4925DY SI4925DY R232 NO_STUFF_0
4
+V5S 4,9,17,19,20,31,32,33,35,36,37,40 4,9,17,19,20,31,32,33,35,36,37,40 +V5S
IDE_PRST1# R223 1M
1 C357 0.1UF
IDE_PRST2#
SECONDARY IDE +V5S PWR ON DC-DC MODULE

14 U40F 12 74HC14
8 R245 2 1
5 6 +V5S_IDE_P 1 2 3 4
J67
+V5S
4,9,17,19,20,31,32,33,35,36,37,40 13
NO_STUFF_0.01_1%
C374 0.1UF
C398 C403 + C404 22UF 0.1UF 100uF
+V5S_IDE_S 1
C355 0.1UF 7
4Pin_PwrConn
14
14
Q22 1N4148
3
U40C 6 74HC14 IDE_SRST 9
U40D 8 74HC14 IDE_SEC_RST# 23
Mobile Drive Only
IDE_SRST2#
R231 100K
IDE_SRST1# R229 1M
5 C363 7 0.1UF
MDC INTERPOSER HEADER
IDE Reset Circuitry

+V5S_IDE_P +V3.3 14,17,19,21,27,29,34,36,40 R306 470 R299 470 DS26 2 GREEN 1 2 J73 PM_SUSLEDGND PM_SUSLED IDE_PLED 1 3 Q28 BSS138 DS27 GREEN 3 CON4_HDR 2 1 2 3 4
18,19,25,26,34,39,40
+V5 J45
+V3.3 14,17,19,21,27,29,34,36,40 +V3.3ALWAYS 2 4 6 8 10 12 14 16 20 9,16,17,18,19,25,26,29,32,33,34,39,40
IDE Activity LEDs

16 AUDIO_PWRDN 16 AC_SYNC 16 AC_SDATAIN1 16 AC_SDATAIN0 16 AC_BITCLK
1 3 5 7 9 11 13 15 17 19
AC_SPKR 16
AC_SDATAOUT 16
2
AC_RST# 16
R199 NO_STUFF_10K AC97_BITCLK has internal pulldown 20K resistor enabled when AC_SHUT bit is set to 1
2x10-SHD-HDR R300 10K
29,30 SMC_INITCLK
1 Q30 BSS138 1 2
PM_SLP_S1# 14,16,34,40
23,40 IDE_PDACTIVE#
+V5S_IDE_S
1
40
1
R238 470 23 IDE_SDACTIVE# 1 GREEN 2 DS24
Title
IDE 2 of 2 / MDC INTERPOSER

Project: 845MP/MZ Platform Sheet 24
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17,26,40
+V5ALWAYS +V5 18,19,24,26,34,39,40 R476 NO_STUFF_0 R477 0 +V5_USB1
+V3.3ALWAYS C76 1 2 0.1UF
9,16,17,18,19,24,26,29,32,33,34,39,40
RP12A 10K R81 R80 1K 1K 1 2 3 4 U14 8 GND IN EN1 EN2 TPS2052

3
RP12B 10K 7
USB_OC0# 16 FER,EMI,1206,3A,25%,50OHM100MHZ 1 2 FB17 50OHM C27 60OHM@100MHZ FB12D 4 5 L15 0.1UF NO_STUFF_ComModeChoke_90ohm@100MHz
OC1# OUT1 OUT2 OC2#
8 7 6 5
USBPWR_CONNC USBPWR_CONND USB_OC1# 16
FER,EMI,1206,3A,25%,50OHM100MHZ 1 2 FB16 50OHM USBD_VCC + C28 + C37 0.1UF 100uF C43 100uF
16 USB_PN0 16 USB_PP0
1 4
1 4
2 3
2 3 1 C32 47pF C33 47pF R312
USBC_VCC USBCUSBC+ 1 R313 2
FB12C 3 6 60OHM@100MHZ 60OHM@100MHZ FB12B 2 7 L16

2
NO_STUFF_Clamping-Diode NO_STUFF_Clamping-Diode NO_STUFF_ComModeChoke_90ohm@100MHz
J5 1 2 3 4 5 6 7 8 VCC1 TOP P#0 PORT P0 GND1 VCC2 BOTTOM P#1 PORT P1 GND2 USB-PORTS
1 4
1 4
2 3
2 3 1 C34 47pF 8 2 2 C31 47pF R314 1
USBUSB+ R315
GND3 GND4 GND5 GND6
9 10 11 12
FB12A 1
60OHM@100MHZ NO_STUFF_Clamping-Diode NO_STUFF_Clamping-Diode
Dual USB
Title
USB (1 of 2)
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+V5ALWAYS
17,25,40 +V5 18,19,24,25,34,39,40
R474 NO_STUFF_0
R475 0 3
+V3.3ALWAYS 1
9,16,17,18,19,24,25,29,32,33,34,39,40
RP12C 10K
RP97A 10K
U2 +V5_USB2 C9 0.1UF R8 R10 1K 1K 1 2 3 4 GND IN EN1 EN2 TPS2052 OC1# OUT1 OUT2 OC2# 8 7 6 5
USB_OC2# 16 1 FB19 50OHM 2 C416 0.1UF USBA_VCC C57 + 100uF
USBPWR_CONNA USBPWR_CONNB USB_OC4# 16
60OHM@100MHZ FB18D 4 5 L18

3
1 4
1 4 3
2 3
NO_STUFF_ComModeChoke_90ohm@100MHz 2 3 6 R325 C49 47pF C48 47pF 1 1
USBAUSBA+ 60OHM@100MHZ FB23C 3 J10B L12 16 USB_PN5 16 USB_PP5 1 4 1 4 2 3 1 2 3 4 1 FB15 50OHM 2 C25 C38 + 5 6 7 8 6 NO_STUFF_ComModeChoke_90ohm@100MHz 2 3 1 1
R323 NO_STUFF_Clamping-Diode 2 2 NO_STUFF_Clamping-Diode
FB18C 60OHM@100MHZ
VCC1 P#0 TOP P0 GND10 PORT VCC2 BOTTOM P#1 PORT P1 GND11 STACKED_RJ45_USB
DOCK_USBP5N 21 DOCK_USBP5P 21
C295 47pF
C304 47pFR176 2 2
R169
60OHM@100MHZ FB18B 2 7 L17 16 USB_PN4

2
0.1UF 100uF
FB23D 60OHM@100MHZ
NO_STUFF_Clamping-Diode NO_STUFF_Clamping-Diode
1 4
1 4
2 3
NO_STUFF_ComModeChoke_90ohm@100MHz 2 3 C50 47pF C51 47pF
USBBUSBB+ +V3.3ALWAYS 1 R324 1 R322 RP97B 2 2 9,16,17,18,19,24,25,29,32,33,34,39,40

2
16 USB_PP4
3 6
RP97C 10K
FB18A 60OHM@100MHZ
10K
NO_STUFF_Clamping-Diode NO_STUFF_Clamping-Diode
16 16
USB_OC5# USB_OC3#
Title
USB Connector (2 OF 2)
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Design Guide
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LAN_PHYCLK Enable Disable

4
J12 Shunt (Default) No Shunt
+V3.3 14,17,19,21,24,29,34,36,40 R2 2 1 Bulk caps should be 4.7uF or higher. L1 1 1 C8 4.7UF 2 2 4.7UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 2 4.7UF 1 C11 C39 C42 C40 C3 C4 1 4.7UH 2 +V3_L_LAN C12 Layout note: Place 100 Ohm resistor close to Kinnereth Optional cap: C652 value 6pF - 12pF if needed for magnetics +V3.3_LAN
4
NOTE: Disable LAN_PHYCLK when not using LAN Interface
NO_STUFF_0.01_1%
Layout note: Transmit/Receive pairs need to be 50 ohms

+V3.3_LAN J10A LAN_TDP LAN_TDN
1 25 36 40 2 7 9 12 14 17 19 23
U4 R7 TDP TDN RDP RDN 10 11 100_1% 15 16 5 LAN_RB100 4 LAN_RB10 32 31 27 47 46 LAN_RDP R4 R3 LAN_RDN 619_1% 549_1% NO_STUFF_603275-109 C1 10PF
J12 15 LAN_JCLK 1 2 15 15 15 15 15 15 15 LAN_CLK LAN_RST LAN_TXD2 LAN_TXD1 LAN_TXD0 LAN_RXD2 LAN_RXD1 LAN_RXD0 TP_LAN_ADV 39 42 45 44 43 37 35 34
VCC1 VCC2 VCCP_2 VCCP_1 VCCA_1 VCCA2 VCCT_1 VCCT_2 VCCT_3 VCCT_4 VCCR1 VCCR2
9 10 13 12
TDP TDN TDC1 TDC2 RDP RDN LED_PWR SPEED LED ACT_LED LINK_LED GRN YLW
RXC GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9
15 28 27 26 25 24 23 22 21 16
+V3.3_LAN If LAN is enabled, PM_LANPWROK waits for PM_PWROK to go high and stays high in S3. 3
R426 10K LAN_TCK Q2
JCLK JRSTSYNC JTXD2 JTXD1 JTXD0 JRXD2 JRXD1 JRXD0 ADV10 ISOL_TCK ISOL_TI ISOL_EX TOUT TESTEN
R6 120
11 14 17 18 19 20
Platform LAN Connect
RBIAS100 RBIAS10 ACTLED SPDLED LILED
16,29 PM_LANPWROK
1 2
BSS138
VSS2 VSS3 VSS4 VSS5 VSS1 VSSP_2 VSSP_1 VSSA_2 VSSA2 VSSR1 VSSR2
41 30 28 29 TP_LAN_TOUT 26 LAN_TESTEN 21 R316 100
LAN_ACTLED# LAN_SPDLED# LAN_LILED# LAN_X2
STACKED_RJ45_USB
X2 X1
Y1 1 C41 22PF 25MHZ 4 C23 22PF
J9 1 2
NO_STUFF
Kinnereth Testpoint Header

2 2
8 13 18 24 48 33 38 3 6 20 22
82562ET
Magnetics and LED resistors are integrated into RJ-45
Chassis GND (should cover part of magnetics)
Title
LAN Interface (Kinnereth)

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4,5,6,9,10,14,17,19,23,29,30,31,32,33,36,37,40
3
+V3.3S
R237
+V3.3S_FWH 15
3
U39 15 FWH_INIT# PCI_RST_ONBD# 14 CLK_FWHPCI 36,37 36,37 36,37 36,37 36,37 VR_VID4 VR_VID3 VR_VID2 VR_VID1 VR_VID0 R197 R210 R201 R204 R214 TP_FWH_ID3 TP_FWH_ID2 TP_FWH_ID1 TP_FWH_ID0 TP_FWH_RSVD2 TP_FWH_RSVD1 TP_FWH_RSVD5 TP_FWH_RSVD4 TP_FWH_RSVD3 100 100 100 100 100 37 R392 100 12 9 7 15 16 17 18 21 22 23 24 32 33 34 35 36 29 30 40 INIT# RST# CLK FGPI4 FGPI3 FGPI2 FGPI1 FGPI0 ID3 ID2 ID1 ID0 RSVD2 RSVD1 RSVD5 RSVD4 RSVD3 GND2 GND1 GNDA FWH VPP VCC2 VCC1 VCCA TBL# WP# FWH4 FWH3 FWH2 FWH1 FWH0 IC NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 11 10 31 39 20 19 38 28 27 26 25 2 1 3 4 5 6 8 13 14
2 1 NO_STUFF_0.01_1% C317 0.1UF R402 100 R403 100 C319 10UF C320 0.1UF C321 0.1UF C322 0.1UF
4,15,20,29,30,31,34
FWH_TBL# 16,34 FWH_WP# 16,34 LPC_FRAME# 16,29,30,31,34 LPC_AD3 16,29,30,31,34 LPC_AD2 16,29,30,31,34 LPC_AD1 16,29,30,31,34 LPC_AD0 16,29,30,31,34
RP6B 10K
FWH SKT
FWH sits in the FWH_TSOP_Socket
FWH IPN is: A60882-004
Title
FWH
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9,16,17,18,19,24,25,26,32,33,34,39,40 2 VR_SHUTDOWN_R
+V3.3ALWAYS +V3.3ALWAYS_KBC 21,30 2 1 NO_STUFF_0.01_1% R14 C6 22UF
J20
C424 0.1UF
C426 0.1UF
C428 0.1UF
C423 0.1UF
Boot Mode Programming Straps

P90-P92 needs to be at VCC for boot mode programming. They are already pulled up in the design. MD0, MD1 needs to be at Vss. Jumper for J22 needs to be populated. System needs to supply +V3ALWAYS to flash connector.
2
KSC Enable Disable Decode KBC Addresses Enable 60h & 64h Disable
21,30
J11 1-2 (Default) 2-3 J2 No Shunt (Default) Shunt

+V3.3ALWAYS_KBC
4
Measurement Point
1
KSC Testpoint Header

Y3 1 C104 18pF 10MHZ 2 3 C93 18pF 10K 6
+V3.3ALWAYS_KBC 21,30
Program
1
J22
RP6C
RP6D 10K
+V3.3ALWAYS_KBC 21,30 U10 59 9 4 36 37 VCC VCL VCCB AVREF AVCC MD1 MD0 XTAL EXTAL RES# STBY# NMI P51/RxD0 P50/TxD0 P52/SCK0/SCL0 P97/SDA0 P96/0/EXCL P92/IRQ0# P91/IRQ1# P90/IRQ2#/ADTRG# P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6/DA0 P77/AN7/DA1 PA1/CIN9/KIN9# PA0/CIN8/KIN8# P40/TMCI0 P41/TMO0 P43/TMCI1/HIRQ11 P44/TMO1/HIRQ1 P45/TMR11/HIRQ12 P46/PWX0 P47/PWX1 PB5/WUE5# PB4/WUE4# PA7/CIN15/KIN15#/PS2CD PA6/CIN14/KIN14/PS2CC PA3/CIN11/KIN11#/PS2AD PA2/CIN10/KIN10#/PS2AC PA5/CIN13/KIN13#/PS2BD PA4/CIN12/KIN12#/PS2BC P95/CS1# P94/IOW# P93/IOR# P60/FTCI/CIN0/KIN0# P61/FTOA/CIN1/KIN1# P62/FTIA/CIN2/KIN2#/TMIY P63/FTIB/CIN3/KIN3# P64/FTIC/CIN4/KIN4# P65/FTID/CIN5/KIN5# P66/FTOB/CIN6/KIN6#/IRQ6# P67/CIN7/KIN7#/IRQ7# P27/PW15 P26/PW14 P25/PW13 P24/PW12 P23/PW11 P22/PW10 P21/PW9 P20/PW8 P17/PW7 P16/PW6 P15/PW5 P14/PW4 P13/PW3 P12/PW2 P11/PW1 P10/PW0 P30/HDB0/LAD0 P31/HDB1/LAD1 P32/HDB2/LAD2 P33/HDB3/LAD3 P34/HDB4/LFRAME# P35/HDB5/LRESET# P36/HDB6/LCLK P37/HDB7/SERIRQ P82/CLKRUN# P83/LPCPD# P85/IRQ4# P86/IRQ5#/SCL1 P42/TMRI0/SDA1 VSS1 VSS2 VSS3 VSS4 AVSS 10 11 30 31 20 21 18 19 22 26 27 28 29 32 33 34 35 60 61 62 63 64 65 66 67 72 73 74 75 76 77 78 79 82 83 84 85 86 87 88 89 95 96 98 99 51 15 70 71 92 46 SCL1 SDA1 KBC_GP_DATA 33 KBC_GP_CLK 33 KBC_MOUSE_DATA 33 KBC_MOUSE_CLK 33 KBC_KB_DATA 33 KBC_KB_CLK 33 2
R33 240 2
R28 240 2 GREEN DS1 LED_SCROLL 1 LED_NUM
R16 240
GREEN DS3
GREEN DS2 1 3
+V3.3ALWAYS_KBC 21,30 14 U7D 11 13 74HC08 7 3 1 2 J11 SMC_MD SMC_MD SMC_XTAL SMC_EXTAL
30 SMC_RST# SMC_PROG_RST#
12
5 6 2 3 1 8 7 13 14 12 16 17 23 24 25
KBC_CAPSLOCK KBC_SCROLLOCK KBC_NUMLOCK KBC_SCANIN0 KBC_SCANIN1 KBC_SCANIN2 KBC_SCANIN3 KBC_SCANIN4 KBC_SCANIN5 KBC_SCANIN6 KBC_SCANIN7 KBC_SCANOUT15 KBC_SCANOUT14 KBC_SCANOUT13 KBC_SCANOUT12 KBC_SCANOUT11 KBC_SCANOUT10 KBC_SCANOUT9 KBC_SCANOUT8 KBC_SCANOUT7 KBC_SCANOUT6 KBC_SCANOUT5 KBC_SCANOUT4 KBC_SCANOUT3 KBC_SCANOUT2 KBC_SCANOUT1 KBC_SCANOUT0
9,16,17,18,19,24,25,26,32,33,34,39,40
3
36 VR_SHUT_DOWN#
SMC_RES# CON3_HDR SMC_STBY# +V3.3ALWAYS 24,30 SMC_INITCLK NO_STUFF_10K VR_SHUTDOWN_R R431 R48 0 N\C TP_NMI_GATE#
1 Q6
3 1 LED_CAPS BSS138 2
1 Q4 KBC_SCANIN[7:0] 33
9,16,17,18,19,24,25,26,32,33,34,39,40 +V3.3ALWAYS 1 8 RP2A 10K 2 7 RP2B 10K
LID SWITCH
36,40 PWR_PWROK 1 SW3 2
33,34,40 33,34,40 14,16,21,34,39,40 33,34,40
SMB_SB_CLK SMB_SB_DATA PM_SLP_S3# SMB_SB_ALRT#
1 Q3
34,40 SMC_ONOFF# SMC_LID VIRTUAL_BATTERY
38 3 39 40 16,34,40 PM_SLP_S5# SPDT_SLIDE 41 34,40 AC_PRESENT# 42 20,33,34 DOCK_INTR# 16,17,18,19,24,25,26,32,33,34,39,40 TP_BT_WAKE_UP 43 N\C +V3.3ALWAYS 44 VIRTUAL KBC_DISABLE# 45 1 SW2 BATTERY BT_ON# R1 10K 2 47 3 48 16,27 PM_LANPWROK 21,30 +V3.3ALWAYS_KBC 49 16,34 PM_PWRBTN# 50 34,36 VR_ON RP2D 52 34,35 FAN_ON 53 2 16,21,34,36 PM_PWROK 9,16,17,18,19,24,25,26,32,33,34,39,40 +V3.3ALWAYS 54 16,34 PM_RSMRST# 10K 55 5,16,34 PM_THRM# 56 34,40 SMC_SHUTDOWN 68 15,34 H_RCIN# RP97D 69 34 SMC_RSTGATE# 10K 80 5,34 SMB_THRM_CLK 81 5,34 SMB_THRM_DATA J2 90 16,33,34 SMC_RUNTIME_SCI# 91 16,31,33,34 SMC_EXTSMI# 93 16,33,34 SMC_WAKE_SCI# 94 33,34 KBC_A20GATE 4 5 5 2 4 1 +V3.3ALWAYS 1 RP17A 10K 28 9,16,17,18,19,24,25,26,32,33,34,39,40 +V3.3ALWAYS_KBC 21,30 34 BAT_SUSPEND 16,33,34 PM_BATLOW# BT_DETACH N\C 2 RP17B 10K J28 7 BT_DETACH 1 3 5 7 9 11 13 2 4 6 8 10 12 14 6 1 3 RP17C 10K 57 58 97 100
H8S/2149F-Z
KBC_SCANOUT[15:0] 33 LPC_AD0 16,28,30,31,34 LPC_AD1 16,28,30,31,34 LPC_AD2 16,28,30,31,34 LPC_AD3 16,28,30,31,34 LPC_FRAME# 16,28,30,31,34 CLK_SMCPCI 14 INT_SERIRQ 15,18,19,20,31,34 PM_CLKRUN# 16,22,31,34 PM_SUS_STAT# 9,16,31,34 SMB_SC_INT# 34 2
3 BSS138
BSS138
PB3/CS4#/WUE3# PB2/CS3#/WUE2# PB1/HIRQ4/WUE1#/LSCI PB0/HIRQ3/WUE0#/LSMI# P80/HA0/PME# P81/CS2#/GA20 PB7/WUE7# PB6/WUE6# P84/IRQ3# RESO#
4,5,6,9,10,14,17,19,23,28,30,31,32,33,36,37,40 +V3.3S C627 100PF R427 56
Measurement Point
J6 14,17,19,21,24,27,34,36,40 +V3.3
RP17D 10K
3 Q10
BSS138 2
Place AC termination close to U10

4,15,20,28,30,31,34
PCI_RST_ONBD#
GATE OFF PCIRST# during S3
SMC_PROG_RST# SMC_MD
CON14_RECEPT
A
Note: for flash progamming, must use TX1 and RX1, which are pin97 and pin98. Jumper J27 needs to be populated.
B
Correct KSC IPN is: A60844-003
Title
System Management and Keyboard Controller

E
J27
KSC Keyboard & System Management Controller
9,18,19,34 PCI_GATED_RST#
SMC_RSTGATE#
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Design Guide
239
Circuitry provides an interrupt to the SMC every 1s while in suspend (this allows the SMC to complete housekeeping functions while suspended)
R25 21,29 +V3.3ALWAYS_KBC 1M R13 0 21,29 +V3.3ALWAYS_KBC C35 Q1 R12 4.7K 14 2 1 0.1UF U8A 2 1 2 3 3 Q33 BSS138 3
+V3.3ALWAYS_KBC
21,29
14
U8B 4 5
14
U8C 6 9
14
U8D 8 SMC_INITCLK 24,29
74HC04 7
74HC04 7 1 7 C55 4.7uF 2 2
74HC04
R15 100K
NOTE: When flashing the KSC INSURE you short J8. Not doing so will permanently damage the KSC.
J8
VCC
GND
RST#
Low Power Mode J8 Normal Short L. PWR Open

3
MAX809 1
3
74HC04
Q34 BSS138 16 KSC_VPPEN# 1
SMC_RST# 29
21,29 +V3.3ALWAYS_KBC 14 U8E 11 10 74HC04 13
+V3.3ALWAYS_KBC 14 U8F 12 74HC04
21,29
SMC SUSPEND TIMER
PORT 80 DISPLAY
4,5,6,9,10,14,17,19,23,28,29,31,32,33,36,37,40 +V3.3S U23 9 17 29 41 VCC1 VCC2 VCC3 VCC4 IO32 IO31 IO30 IO29 IO28 IO27 IO26 IO25 IO24 IO23 IO22 IO21 IO20 IO19 IO18 IO17 IO16 IO15 IO14 IO13 IO12 IO11 IO10 IO9 IO8 IO7 IO6 IO5 IO4 IO3 IO2 IO1 44 43 42 35 34 33 32 31 30 28 27 26 25 23 22 21 20 19 18 15 14 13 12 11 10 8 7 6 5 3 2 1 LPC_FRAME# 16,28,29,31,34 LED1_INPUT1 LED1_INPUT2 LED1_INPUT3 LED1_INPUT4 LED1_INPUT5 LED1_INPUT6 LED1_INPUT7 RP37D RP37C RP37B RP36D RP36B RP36C RP36A 4 3 2 4 2 3 1 150 150 150 150 150 150 150 5 6 7 5 7 6 8
4,5,6,9,10,14,17,19,23,28,29,31,32,33,36,37,40 CR7 LED1_INPUT1_R LED1_INPUT2_R LED1_INPUT3_R LED1_INPUT4_R LED1_INPUT5_R LED1_INPUT6_R LED1_INPUT7_R 1 10 8 5 4 2 3 7 A B C D E F G DP
+V3.3S
AN1 AN2
6 9
2
7-SEG-LED-DISPLAY
14 CLK_PCI_PORT80 4,15,20,28,29,31,34 PCI_RST_ONBD#
37 39 38 40 R375 100
GCLK GCLR# OE#1 OE#2
LEFT
4,5,6,9,10,14,17,19,23,28,29,31,32,33,36,37,40 CR8 LED2_INPUT1 LED2_INPUT2 LED2_INPUT3 LED2_INPUT4 LED2_INPUT5 LED2_INPUT6 LED2_INPUT7 RP38D RP38C RP38A RP39C RP39B RP39D RP38B 4 3 1 3 2 4 2 150 150 150 150 150 150 150 5 6 8 6 7 5 7 LED2_INPUT1_R LED2_INPUT2_R LED2_INPUT3_R LED2_INPUT4_R LED2_INPUT5_R LED2_INPUT6_R LED2_INPUT7_R 1 10 8 5 4 2 3 7 A B C D E F G DP +V3.3S
AN1 AN2
6 9
4,5,6,9,10,14,17,19,23,28,29,31,32,33,36,37,40 +V3.3S
1
7-SEG-LED-DISPLAY LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0 16,28,29,31,34 16,28,29,31,34 16,28,29,31,34 16,28,29,31,34
C497 0.1UF
C496 0.1UF
C498 0.1UF
4 16 24 36
GND1 GND2 GND3 GND4 EPM7032AE
RIGHT
Title
SMC Suspend Timer and Port 80 LEDs

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Design Guide
240
J49 PCI_RST_ONBD# 4,15,20,28,29,30,34 1 3 CON3_HDR U30

4
2 SIO_RST#
SIO Enable Disable
J49 1-2 (Default) 2-3

+V3.3S_SIO RP74A 1
PPT_PNF# 32 +V3.3S_SIO 8 10K +V5S_DIODE VDD1 VDD2 VDD3 VDD4 VSS5 VSS6 VSS7 VSS8 SLIN#/ASTRB# INIT# ERR# AFD#/DSTRB# STB#/WRITE# PNF SLCT PE BUSY/WAIT# ACK# PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 DCD1# DSR1# SIN1 RTS1# SOUT1/XCNF0 CTS1# DTR1# RI1# XCNF1/XWR# XCNF2 GPIO20 GPIO21 GPIO22 GPIO23 GPIO24 GPIO26 GPIO27 GPIO30 GPIO31 GPIO32 GPIO33 GPIO34 NC 14 39 63 88 13 38 64 89 47 49 51 53 54 35 36 37 40 41 42 43 44 45 46 48 50 52 55 56 57 58 59 60 61 62 4 90 95 94 93 92 91 87 86 85 84 83 82 5 65 4,5,6,9,10,14,17,19,23,28,29,30,32,33,36,37,40 +V3.3S 6 RP74C 10K
+V5S
4,9,17,19,20,24,32,33,35,36,37,40 Q19
BAR43 RP58B RP58C RP58D RP55A RP55B RP55C RP55D RP58A

4
PWR & GND
16,28,29,30,34 LPC_AD0 16,28,29,30,34 LPC_AD1 16,28,29,30,34 LPC_AD2 16,28,29,30,34 LPC_AD3 14 CLK_SIOPCI 16,22,34 LPC_DRQ#0 16,28,29,30,34 LPC_FRAME#
15 16 17 18 8 11 12 9 10 19 7 6 20 69 68 67 71 66 70 21 22 23 24 25 26 27 28 29 30 31 32 33 34 72 73 3 2 1 100 99 98 97 96 81 80 79 78 77 76 75 74
LAD0 LAD1 LAD2 LAD3 LCLK LDRQ# LFRAME# LRESET# SERIRQ SMI# LPCPD# CLKRUN# CLKIN
7 6 5 8 R161 R160 33 33 PPT_SLIN#/ASTRB# 32 PPT_INIT# 32 PPT_ERR# 32 PPT_AFD#/DSTRB# 32 PPT_STB#/WRITE# 32 1K 1K 1K 1K C286 PPT_SLCT 32 330PF PPT_PE 32 PPT_BUSY/WAIT# 32 PPT_ACK# 32 RP57C RP57B RP57A RP56D 3 2 1 4 C285 330PF 33 33 33 33 33 33 33 33
15,18,19,20,29,34 INT_SERIRQ 16,29,33,34 SMC_EXTSMI# 9,16,29,34 PM_SUS_STAT# 16,22,29,34 PM_CLKRUN# 14 32 32 32 32 32

3
CLK_SIO14 IR_RXD IR_SEL IR_MD0 IR_MD1 IR_TXD
Clock IR
AFD#/DSTRB# STB#/WRITE#
Parallel Port
IRRX1 IRRX2_IRSL0 IRSL1 IRSL2A/DR1B/XIORDB IRSL3/PWUREQ IRTX DSKCHG# HDSEL# RDATA# WP# TRK0# WGATE# WDATA# STEP# DIR# DR0# MTR0# INDEX# DENSEL DRATE0 DR1# MTR1# GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 PC87393
Straps
Serial Port
32 FLP_DSKCHG# 32 FLP_HDSEL# 32 FLP_RDATA# 32 FLP_WP# 32 FLP_TRK0# 32 FLP_WGATE# 32 FLP_WDATA# 32 FLP_STEP# 32 FLP_DIR# 32 FLP_DR0# 32 FLP_MTR0# 32 FLP_INDEX# 32 FLP_DENSEL# 32 FLP_DRATE0
BUSY/WAIT# ACK# PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
R175 R173
100 100
1K 1K 1K 1K
7 6 5 8
Bus Interface FDC
5 RP59D
6 RP59C
5 RP41D
6 RP41C
7 RP59B
8 RP59A
8 RP41A
7 RP41B
R165
2 3 4 1
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
2 3 4 1
6 7 8 5 6 7 8
PPT_PD7 PPT_PD6 PPT_PD5 PPT_PD4 PPT_PD3 PPT_PD2 PPT_PD1 PPT_PD0
32 32 32 32 32 32 32 32
SER_DCDA# 20,32 SER_DSRA# 20,32 SER_SINA 20,32 SER_RTSA# 20,32 SER_SOUTA 20,32 C305 C303 C287 C500 C502 C501 C289 C301 C507 C302 SER_CTSA# 20,32 SER_DTRA# 20,32 680PF 680PF 330PF 330PF 330PF 330PF 330PF 330PF 330PF 330PF SER_RIA# 20,32
RP56C 3 RP56B 2 RP56A 1 R424
R159 10K
GPIOs
+V3.3S_SIO R182 2 1 C514 0.1UF C508 0.1UF C282 22UF
NO_STUFF_0.01_1%
Title
Super I/O Controller

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Design Guide
241
4,9,17,19,20,24,31,33,35,36,37,40
+V5S
31 PPT_PNF# 31 PPT_SLCT RP102C
60OHM@100MHZ 1 8 FB6A 2 7 FB6B 60OHM@100MHZ 3 6 FB6C 4 5 FB6D 1 8 FB11A 2 7 FB11B
PARALLEL PORT
PPT_L_PNF# PPT_L_SLCT J4 PPT_L_PE PPT_L_BUSY/WAIT# PPT_L_ACK# PPT_L_PD7 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1
RP104A 3
RP102B 1
FLOPPY CONNECTOR
8
4
RP104C 2
RP102A 3
J72 1 3 7 9 11 13 15 17 19 21 23 25 27 29 31 33 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34
1K 6
1K 7
1K 8
1K 6
1K FLP_DENSEL# 31 FLP_DRATE0 31 FLP_INDEX# 31 FLP_MTR0# 31 FLP_DR0# 31 FLP_DIR# 31 FLP_STEP# 31 FLP_WDATA# 31 FLP_WGATE# 31 FLP_TRK0# 31 FLP_WP# 31 FLP_RDATA# 31 FLP_HDSEL# 31 FLP_DSKCHG# 31
31 PPT_PE 31 PPT_BUSY/WAIT# 31 PPT_ACK# 31 PPT_PD7
PPT_L_PD6 60OHM@100MHZ 3 6 FB11C 4 5 FB11D 1 8 FB5A 2 7 FB5B PPT_L_PD5 PPT_L_PD4 PPT_L_PD3
31 31 31 31
PPT_PD6 PPT_PD5 PPT_PD4 PPT_PD3
17x2_HDR
31 PPT_SLIN#/ASTRB# 31 PPT_PD2 31 PPT_INIT# 31 PPT_PD1
60OHM@100MHZ 3 6 FB5C 4 5 FB5D 1 8 FB10A 2 7 FB10B
PPT_L_SLIN# PPT_L_PD2 PPT_L_INIT# PPT_L_PD1
26 GND0 27 GND1 28 GND2 PARALLEL

3
31 PPT_ERR# 31 PPT_PD0 31 PPT_AFD#/DSTRB# 31 PPT_STB#/WRITE#
60OHM@100MHZ 3 6 FB10C 4 5 FB10D 1 8 FB9A 2 7 FB9B
PPT_L_ERR# PPT_L_PD0 PPT_L_AFD#/DSTRB# PPT_L_STB#/WRITE#
INFRARED PORT
4,5,6,9,10,14,17,19,23,28,29,30,31,33,36,37,40 +V3.3ALWAYS 9,16,17,18,19,24,25,26,29,33,34,39,40 31 31 C5 22UF C2 0.1UF U3
2
+V3.3S R9 2.2
+V3.3S_IR U1 10 9 8 7 6 5 4 3 2 1 LEDA TXD RXD GND NC MOD1 MOD0 FIR_SEL AGND VDD MNT HSDL-3600#017
IR_TXD IR_RXD IR_MD1 IR_MD0 IR_SEL
31 31 31 V+ 27 SERBUF_V+ C22
PM_RI# 16,21,22,34
C21 0.1UF Q24 BSS138 C26 0.1UF
SERBUF_C1+ 28 SERBUF_C1- 24 SERBUF_C2+ 1 2 20 19 18 17 16 15 14 13 12 23 22 21
VCC
26
C1+ C1C2+ C2R2OUTB R1OUT R2OUT R3OUT R4OUT R5OUT T1IN T2IN T3IN
11
C10 0.1UF SERBUF_VC24 0.1UF SERBUF_CTSA SERBUF_RIA SERBUF_SINA# SERBUF_DSRA SERBUF_DCDA C7 0.1UF 10UF
1 2
V-
SERBUF_C2SER_RIA 20,31 SER_CTSA# 20,31 SER_RIA# 20,31 SER_SINA 20,31 SER_DSRA# 20,31 SER_DCDA# 20,31 SER_DTRA# 20,31 SER_SOUTA 20,31 SER_RTSA# 4,5,6,9,10,14,17,19,23,28,29,30,31,33,36,37,40 +V3.3S R5 1K SER_ON 16 SER_EN
SERIAL PORT
60OHM@100MHZ SERPRT_DCDA 3 6 FB9C SERPRT_DSRA 4 5 FB9D SERPRT_SINA# 3 6 FB7C SERPRT_RTSA 1 8 FB7A 60OHM@100MHZ 2 7 FB7B SERPRT_SOUTA# J1 1 6 2 7 3 8 4 9 5 SERIAL GND1 11 10
Caps must be placed as close as possible to pins 1,2
T1OUT T2OUT T3OUT
9 SERBUF_DTRA 10 SERBUF_SOUTA# 11 SERBUF_RTSA
FORCEON FORCEOFF# INVALID# MAX3243
GND
25
4 1 2
5 FB7D 8 FB8A 7 FB8B
SERPRT_CTSA SERPRT_DTRA SERPRT_RIA
R423 1K Note: FORCEOFF# overrides FORCEON.

A B
R2OUTB is enabled even in suspend. SER_RIA# is routed to allow the system to wake up in Suspend To RAM.
Title
Floppy, Parallel, Serial, and IR Ports

E
Design Guide
GND0
1
R1IN R2IN R3IN R4IN R5IN
4 5 6 7 8
of
42
242
+V5S 4,9,17,19,20,24,31,32,35,36,37,40 KBC_SCANOUT[15:0] 29 CBTD has integrated diode for 5V to 3.3V voltage translation 2 4 6 8 10 12 14 16 18 20 22 24 KBC_SCANOUT1 KBC_SCANOUT3 KBC_SCANOUT5 KBC_SCANOUT7 KBC_SCANOUT9 KBC_SCANOUT11 KBC_SCANOUT13 KBC_SCANOUT15 KBC_SCANIN1 KBC_SCANIN3 KBC_SCANIN5 KBC_SCANIN7
J30 KBC_SCANOUT0 KBC_SCANOUT2 KBC_SCANOUT4 KBC_SCANOUT6 KBC_SCANOUT8 KBC_SCANOUT10 KBC_SCANOUT12 KBC_SCANOUT14 KBC_SCANIN0 KBC_SCANIN2 KBC_SCANIN4 KBC_SCANIN6 1 3 5 7 9 11 13 15 17 19 21 23 U9 29 29 29 29 29 KBC_GP_DATA KBC_GP_CLK KBC_MOUSE_DATA KBC_MOUSE_CLK KBC_KB_DATA 3 4 7 8 11 14 17 18 21 22 1 13 KBC_SCANIN[7:0] 29 R26 100 +V5S 4,9,17,19,20,24,31,32,35,36,37,40 +V5S
3
C36 0.1UF
4
1A1 1A2 1A3 1A4 1A5 2A1 2A2 2A3 2A4 2A5 1OE# 2OE#
VCC 1B1 1B2 1B3 1B4 1B5 2B1 2B2 2B3 2B4 2B5 GND
24 2 5 6 9 10 15 16 19 20 23 12 4,5,6,9,10,14,17,19,23,28,29,30,31,32,36,37,40 +V3.3S RP75C 8.2K 6 3 GP_DATA GP_CLK MOUSE_DATA MOUSE_CLK KBD_DATA KBD_CLK
29 KBC_KB_CLK 15 H_A20GATE
MOUSE_DATA 20 MOUSE_CLK 20 KBD_DATA 20 KBD_CLK 20 KBC_A20GATE
29,34
NO_STUFF_24Pin_ZIF-HDR
Scan Matrix Key Board
Bus-Switch-74CBT3384
4,9,17,19,20,24,31,32,35,36,37,40
RP4A 4.7K FB8C GP_CLK 8 3 6 60OHM@100MHZ 3 +1 2 RT1 1.1A
+V5S 2
4,9,17,19,20,24,31,32,35,36,37,40
RP3B 4.7K 7
+V5S 4,9,17,19,20,24,31,32,35,36,37,40
CP1C 47PF 6
FB3 FB4 31Ohm@100MHz L_GPDATA 1 2 60ohm@100MHz C52 C54 22UF 0.1UF
4,9,17,19,20,24,31,32,35,36,37,40
4,9,17,19,20,24,31,32,35,36,37,40 +V5S RP3C 4.7K FB1 1 2 C29 47pF +V3.3ALWAYS RP74D RP98A RP98B RP98D RP99A RP88B RP88C R422 60ohm@100MHz 9,16,17,18,19,24,25,26,29,32,34,39,40 6 C30 47pF 3
+V5S 4
RP3D 4.7K
2
2 J7 FB2 1 1 2 L_GPCLK 6 4 2 5 13 14 15 10 12 11 4,9,17,19,20,24,31,32,35,36,37,40 +V5S 1 RP3A 4.7K 8 FB13 1 2 CP1B 47PF 7 2 9 DUAL_PS2 8 7 1 3 16 17
KBD_CLK CP1A 47PF
60ohm@100MHz 8
+V5S 3
4,9,17,19,20,24,31,32,35,36,37,40
RP4C 4.7K
4 1 2 4 1 2 3
10K 10K 10K 10K 10K 10K 10K 10K
5 8 7 5 8 7 6
SMC_EXTSMI# 16,29,31,34 SMC_RUNTIME_SCI# 16,29,34 SMC_WAKE_SCI# 16,29,34 PM_BATLOW# 16,29,34 SMB_SB_DATA 29,34,40 SMB_SB_CLK 29,34,40 SMB_SB_ALRT# 29,34,40 DOCK_INTR# 20,29,34
FB14 1 2 4
MOUSE_CLK
If a PS/2 "breakout" connector is used,the keyboard PS/2 connector can be used for both a PS/2 keyboard and a second PS/2 mouse. Otherwise, the keyboard PS/2 connector will only support a PS/2 keyboard.
60ohm@100MHz
60ohm@100MHz
CP1D 47PF
Title
Keyboard and Mouse Connectors

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Design Guide
243
9,19,22,35,40
+V12S
LPC POWERED ON SUSPEND RAIL FOR ADD-IN H8 CARD

+V3.3_LPCSLOT 5,15,16,17,18,19,20,22 +V3.3S_ICH J57 16,29,33 9,15,18,19,22 15,22 16,21,22,32 PM_BATLOW# PCI_PME# SM_INTRUDER# PM_RI# 1 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16 PM_RSMRST# 16,29 H_INIT# 3,15 H_INTR 3,15 PCI_RST_ONBD# 4,15,20,28,29,30,31 PM_PWROK 16,21,29,36
+V3.3_LPCSLOT
LPC Debug Slot

1 2 J55 3 9,19,22,35,40 +V12S B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 RP106A RP106B RP106C 10K 10K 10K
16 PM_SUS_CLK
9,16,17,18,19,24,25,26,29,32,33,39,40
+V3.3ALWAYS
15,29 H_RCIN# 29,33 KBC_A20GATE 16,29,31,33 SMC_EXTSMI# +V5_LPCSLOT
12V1 SUSCLK GND1 LREQ VCC3_1 LCNTL0 GND3 LDC LD5 GND4 LD3 LD1 GND6 3V_STBY LPS KBRESTE# A20GATE# GND8 LSMI# KEY
12V2 NEG_12V GND2 BP_CLK VCC3_2 LCNTL1 GND5 LD6 LD4 GND7 LD2 LD0 VCC5_2 SCLK GND10 SERIRQ CLKRUN# GND12 LINK_ON
15,22 SMB_ALERT# 5,16,29 PM_THRM# 16,29 PM_PWRBTN#
J78 1 2 3 4 CON4_HDR 3,15 14,16 16,29,40 16,22,29,31 3,15 16,36,37 H_STPCLK# PM_STPPCI# PM_SLP_S5# PM_CLKRUN# H_DPSLP# PM_DPRSLPVR
2X8_HDR
16 16 16 +V5_LPCSLOT
ICH_GPIO7 ICH_GPIO42 ICH_GPIO43
J64 1 2 3 4 5 6 6Pin_HDR
SMBus Debug Header

INT_SERIRQ 15,18,19,20,29,31 PM_CLKRUN# 16,22,29,31
17,22 +V3.3ALWAYS_ICH R311 LPC_DRQ#0 16,22,31 LPC_AD3 16,28,29,30,31 LPC_AD1 16,28,29,30,31 CLK_LPCPCI 14 PM_SUS_STAT# 9,16,29,31 15 TP_HUBPAR 3,15 H_CPUSLP# 15,19,22 INT_PIRQH# 16 ICH_MFG_MODE 9,15,18,19,22 PCI_PME# 4.7K J76 1 3 5 7 9 2 4 6 8 10 IDE_PATADET 16,22,23 IDE_SATADET 16,22,23 ICH_GPIO42 16 ICH_GPIO43 16
3
16,22 LPC_DRQ#1 16,28,29,30,31 LPC_FRAME# 16,28,29,30,31 LPC_AD2 16,28,29,30,31 LPC_AD0
14 CLK_LPC14 PCI_RST_ONBD# PCI_GATED_RST# 9,18,19,29 R281 0 R269 NO_STUFF_0 LPC_RST# 4,15,20,28,29,30,31
B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30
VCC5_1 LDRQ1# LFRAME1# GND9 LAD2 LAD0 GND11 PCIRST# GND13 OSC VCC3_3 60Pin_CardCon
VCC5_3 LDRQ0# GND14 LAD3 LAD1 GND15 PCICLK LPCPD# GND16 PME# VCC3_4
A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30
2X5-Header
ICH3-M Testpoint Header
J36 PM_THRM# PM_PWRBTN# SMC_ONOFF# VR_ON PM_PWROK 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 SMC_RUNTIME_SCI# 16,29,33 SMC_WAKE_SCI# 16,29,33 FAN_ON 29,35 SMB_THRM_CLK 5,29 SMB_THRM_DATA 5,29 SMB_SB_CLK 29,33,40 SMB_SB_DATA 29,33,40 SMB_SB_ALRT# 29,33,40 PM_BATLOW# 16,29,33 J61 14,16,36,37 14,16,24,40 9,16 3,16 16,36 16,36 3,15 3,15 PM_STPCPU# PM_SLP_S1# PM_C3_STAT# PM_CPUPERF# VR_PWRGD PM_GMUXSEL H_CPUSLP# H_STPCLK# 1 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16 PM_STPPCI# 14,16 INT_IRQ14 15,22,23 INT_IRQ15 15,22,23 AGP_SUSPEND# 9,16 H_SMI# 3,15 H_NMI 3,15 PM_CLKRUN# 16,22,29,31
5,16,29 16,29 29,40 29,36 16,21,29,36 16,29 PM_RSMRST#

2
R317
29,40 AC_PRESENT# 14,16,24,40 PM_SLP_S1# 14,16,21,29,39,40 PM_SLP_S3# 10K 29,40 29 29 20,29,33 SMC_SHUTDOWN BAT_SUSPEND SMC_RSTGATE# DOCK_INTR#
2X8_HDR SMB_SC_INT# 29
15x2_HDR SMC Sidebands for LPC Power Management J66 24,40 IDE_PPWR_EN 1 3 5 7 2 4 6 8 FWH_WP# 16,28 FWH_TBL# 16,28 +V3.3 14,17,19,21,24,27,29,36,40 +V3.3_LPCSLOT R195 2 1 C352 C353 22UF 18,19,24,25,26,39,40 2 4 6 8 H_IGNNE# 3,15 PM_SUS_CLK 16 PM_GMUXSEL 16,36 +V5 R196 2 1 C347 C370 22UF 0.1UF +V5_LPCSLOT 0.1UF C351 0.1UF C343 0.1UF 1 1 J79 2 1 J39 2 1 J47 2 1 J74 2 1 J16 2
NO STUFF
GROUND HEADERS
8Pin HDR SIO Sidebands
NO_STUFF_0.01_1%
TEST HEADER
1
J59 2 1
J13 2 1
J37 2 1
J25 2
1
J62 16,29,31,33 16,36 3,15 3,15 SMC_EXTSMI# VR_PWRGD H_A20M# H_PWRGD 1 3 5 7
NO_STUFF_0.01_1%
8Pin HDR
Title
LPC Slot & Debug Headers

E
of
42
Design Guide
244
4,9,17,19,20,24,31,32,33,36,37,40 +V5S
Fan Power Control

4 R79 1M 6 5 2 1 U15 SI3457DV 3 +V5_FAN
+
C73 0.1UF C84 22UF 1 2 CON2_HDR J24 1 3 Q9 1N4148
C97 1000PF
R83 3
100K
Q8 BSS138 29,34 FAN_ON 1 2
9,19,22,34,40
+V12S J14 3 2 1 CON3_HDR
4,9,17,19,20,24,31,32,33,36,37,40 +V5S
2
C44 0.1UF
Desktop Fan Header

C47 0.1UF C64 22UF 1 2 CON2_HDR J17
Title
System Management and Keyboard Controller IC

E
of
42
Design Guide
245
VR PWRGD CIRCUIT
+V3.3S +V3.3S C359 0.1UF 37 ON_BOARD_VR_PWRGD
4
VR Interposer Headers
4,5,6,9,10,14,17,19,23,28,29,30,31,32,33,37,40 +V3.3S 14 R272 1M INTERPOSER_PRES# 29,34 VR_ON 12 11 13 74HC08 C53 10UF 7 6 7 4,5,6,9,10,14,17,19,23,28,29,30,31,32,33,37,40 U13 U11D 1 ON_BOARD_VCCVID_ON 8 VIN TPS62000 EN ILIM SYNC GND VR_PWRGD_CK408# 14 4,5,6,9,10,14,17,19,23,28,29,30,31,32,33,37,40 +V3.3S 3 FC 2 R50 0 C63 0.1UF 3 C647 0.1UF 14 1 CON3_HDR R326 100K_1% J38 CON3_HDR 2 2 FB PGND PG L 9 5 10 4 2 3 1 R57 9.76k_1% J21 1 1 C69 L3 10uH 2 1 47pF R327 165k_1% 2 1 R56 27.4K_1% + 2 NO_STUFF_0 C80 33UF
4
4,5,6,9,10,14,17,19,23,28,29,30,31,32,33,37,40 +V3.3 14 U50A 3 2 7 74HC00 4 5 7 74HC00 R291 10K 10K R285 1 3 Q26 2N3904 2
14,17,19,21,24,27,29,34,40 R270 100K 1 14 U50B 14,17,19,21,24,27,29,34,40 +V3.3
+VCC_VID
3,5
3,4,5,7,15,17,37,38 +VCC_CORE
R421
INTERPOSER_PRES#
4,5,6,9,10,14,17,19,23,28,29,30,31,32,33,37,40 +V3.3S 6
+V3.3 14 U50C 10
14,17,19,21,24,27,29,34,40
8 9 74HC00 7 OFF_BOARD_VR_PWRGD
14,17,19,21,24,27,29,34,40 +V3.3 14 U50D 13 11 12 R282 100K 7 74HC00
CPU
J21 J38
Willamette-N 1 - 2 1 - 2 Northwood 2 - 3 2 - 3
R34 May need a 0 ohm for Willamette-N
FF
1
14
CPU VOLTAGE REGULATOR MODULE (1/3)

Sheet 36 of 42
14
14
14
4,5,6,9,10,14,17,19,23,28,29,30,31,32,33,37,40 +V3.3S 14 U59C 4,5,6,9,10,14,17,19,23,28,29,30,31,32,33,37,40 VR_PWRGD 16,34 100K Y 3 Y 6 680K +V3.3S 1 A 4 A 10 B VCC GND GND VCC_VIDPWRGD 5 Y 8 3 74AHC132 74AHC132 9 A 3 H_VID[4:0] GND 7 7 4,5,6,9,10,14,17,19,23,28,29,30,31,32,33,37,40 R225 C326 4,5,6,9,10,14,17,19,23,28,29,30,31,32,33,37,40 0.1UF C66 4,5,6,9,10,14,17,19,23,28,29,30,31,32,33,37,40 74AHC132 +V3.3S 7 1K 100PF +V3.3S +V3.3S 4,5,6,9,10,14,17,19,23,28,29,30,31,32,33,37,40 +V3.3S U11A U38 U11B 1 U11C H_VID0 3 A0 4 3 VR_VID0 28,37 ON_BOARD_VR_ON 37 C0 2 R188 OFF_BOARD_VR_ON 2 H_VID1 7 A1 9 6 VR_VID1 28,37 5 H_THRMTRIP# C1 6 H_VID2 74HC08 8.2K 11 A2 8 5 VR_VID2 28,37 C2 10 H_VID3 4,5,6,9,10,14,17,19,23,28,29,30,31,32,33,37,40 17 A3 16 10 VR_VID3 28,37 29 VR_SHUT_DOWN# C3 H_VID4 74HC08 +V3.3S 21 A4 VR_VID4 28,37 C4 20 74HC08 STRAP_VID0 4 B0 14 D0 5 4,5,6,9,10,14,17,19,23,28,29,30,31,32,33,37,40 +V3.3S U59D STRAP_VID1 8 B1 D1 9 STRAP_VID2 14 B2 13 B VCC D2 15 +V5S 4,9,17,19,20,24,31,32,33,35,37,40 STRAP_VID3 18 B3 19 Y 11 D3 J53 STRAP_VID4 22 B4 12 A D4 23 GND 1 BE# 1 2 PM_GMUXSEL 16,34 VCC 24 74AHC132 TP_OFF_BOARD_VCC_VID_PWRGD 3 13 BX 4 R203 R212 R186 R226 R198 PM_DPRSLPVR 16,34,37 GND 12 7 C331 OFF_BOARD_VR_PWRGD 5 6 330 330 330 330 330 0.01UF Bus_Switch_74CBT3383 6Pos_DIP 7 8 4,5,6,9,10,14,17,19,23,28,29,30,31,32,33,37,40 +V3.3S +V3.3S 4,5,6,9,10,14,17,19,23,28,29,30,31,32,33,37,40 R187 9 10 1K VID4_LED VID2_LED VID0_LED 11 12 7,9,40 +V1.5S +V5S 4,9,17,19,20,24,31,32,33,35,37,40 VID3_LED VID1_LED INTERPOSER_PRES# 13 14 14,17,19,21,24,27,29,34,40 +V3.3 1 2 3 4 5 6 15 16 DS18 2 DS20 DS21 17 18 GREEN GREEN U5B GREEN 19 20 21 22 4 DS19 DS22 +VCC_VID 3,5 J58 23 24 6 GREEN GREEN PM_DPRSLPVR 1 2 25 26 5 14,16,34,37 PM_STPCPU# VR_VID2 28,37 16,34,37 Note: With pin 13 high, B input goes to 3 4 27 28 28,37 VR_VID4 VR_VID1 28,37 74HC08 C output. With pin 13 low, A input 5 6 29 30 28,37 VR_VID3 VR_VID0 28,37 7 8 31 32 goes to C output. 14,17,19,21,24,27,29,34,40 +V3.3 9 10 33 34 11 12 35 36 4,5,6,9,10,14,17,19,23,28,29,30,31,32,33,37,40 +V3.3S +V3.3S 4,5,6,9,10,14,17,19,23,28,29,30,31,32,33,37,40 U5C 13 14 37 38 ON = Shunt jumper or set switch to ON 15 16 39 40 9 4,9,17,19,20,24,31,32,33,35,37,40 +V5S +V5S 4,9,17,19,20,24,31,32,33,35,37,40 37,38,40 +VDC JUMPER SETTINGS OFF= No Shunt in jumper or switch OFF 17 18 8 20x2_Header 19 20 10 21 22 74HC08 23 24 Willamette-N installed 25 26 Connector 1 - Install R257 14,17,19,21,24,27,29,34,40 +V3.3 27 28 (rows A,B) 14,17,19,21,24,27,29,34,40 +V3.3 - Switch 4 Positio n 6 = off 29 30 U5D 31 32 - +VCC_CORE = 1.7V U5A 33 34 12 - +VCC_CORE set by switch 4 35 36 1 11 29,40 PWR_PWROK 37 38 3 13 PM_PWROK 16,21,29,34 1 39 40 2 3,5,40 MASTER_RESET# 37,38,40 +VDC 74HC08 Northwood installed 74HC08 20x2_Header - Remove R257 V - Switch 4 Positio n 6 = on - +VCC_CORE = 1.0V Title Connector 2 - +VCC_CORE set by (rows C,D) switch 4 in deeper sleep Project: - +VCC_CORE set by CPU in Normal 845MP/MZ Platform m ( 1.3V Normal, 1.2V Geyserville ) R19 U59A 14 U59B 2 B VCC 5 B VCC 1K4 1K3 1K2 RP13D 5 RP13C 6 RP13B 7 RP13A 8 1K1 R257 NO_STUFF_8.2K 8.2K1 8.2K2 RP95C 8.2K 6 3 RP95A 8 RP95B 7 8.2K R249 14 14 12 11 10 9 8 SW4A SW4B SW4E 7 SW4C 1 2 3 4 SW4D 5 6 SW4F 2 2 2 2 2 7 7 7 14
Design Guide
246
+VDC
D
36,37,40
Decoupling
C263 10UF C280 10UF C284 10UF C288 10UF C309 10UF C308 10UF C312 10UF C311 10UF C316 10UF C310 10UF
VR Input Decoupling
C279 10UF
C307 10UF
Bulk decoupling values are tuned to Intels IMVP II 5Phase VR design. Circuits using other converter topologies may have different requirements.
+VCC_CORE
3,4,5,7,15,17,36,37
V_CORE Bulk Decoupling
C195 10UF
C206 10UF
C217 10UF
C201 10UF
C216 10UF
C227 10UF
C241 10UF
C239 10UF
C225 10UF
C224 10UF
C238 10UF
C223 10UF
C237 10UF
C236 10UF
C222 10UF
C194 10UF
C234 10UF
C220 10UF
C221 10UF
C235 10UF
C
+VCC_CORE
3,4,5,7,15,17,36,37
V_CORE Bulk Decoupling (Optional)
C203 10UF
C211 10UF
C208 10UF
C212 10UF
C240 10UF
C226 10UF
C205 10UF
C215 10UF
C204 10UF
C214 10UF
C213 10UF
C207 10UF
C210 10UF
C202 10UF
C253 + 150UF
C252 + 150UF
C251 + 150UF
C250 + 150UF
C267 + -
C265 + -
C266 + -
C254 + 150UF
NO_STUFF_150UF NO_STUFF_150UF NO_STUFF_150UF
High Frequency Decoupling (Place underneath Processor)
+VCC_CORE
3,4,5,7,15,17,36,37
C96 10UF
C102 10UF
C106 10UF
C135 10UF
C136 10UF
C150 10UF
C159 10UF
C164 10UF
C146 10UF
C138 10UF
C183 10UF
C178 10UF
C186 10UF
C185 10UF
C455 10UF
C454 10UF
C465 10UF
C446 10UF
C449 10UF
C452 10UF
C447 10UF
C450 10UF
C453 10UF
C469 10UF
C464 10UF
C470 10UF
C108 10UF
+VCC_CORE
3,4,5,7,15,17,36,37
+VCC_CORE
3,4,5,7,15,17,36,37
C88 10UF
C107 10UF
C190 10UF
C187 10UF
C153 10UF
C95 10UF
C87 10UF
C119 10UF
C175 10UF
C149 10UF
C174 0.47uF 2 2
C166 0.47uF 2
C162 0.47uF 2
C158 0.47uF 2
C155 0.47uF 2
C173 0.47uF 2
C161 0.47uF 2
C157 0.47uF 2
C154 0.47uF 2
Mid Frequency Decoupling (Place around Processor)
C167 0.47uF
Title
Decoupling
Project: 845MP/MZ Platform m Sheet 38 of 42
Design Guide
247
+V5
18,19,24,25,26,34,40
U43 C388 150uF C380 150uF C372 150uF C367 0.1UF VIN0 VIN1 VIN2 VIN3 VIN4 VSENSE
D
C362 47pF PG_EN C361 1 R217 2 1 2
NC/Comp PWRGD BOOT RT FSEL
PH0 PH1 PH2 PH3 PH4 PH5 PH6 PH7 PH8 PwrPad
+V2.5_DDR
Coilcraft DO5022P-103 10uH 10A sat. L13 1 10uH 2 R172 0.01_1%
10,13
Single point sense near load
+V2.5
7,8,13,40
C281 0.1UF
25.5k_1% R230
5600pF
AGND
NO_STUFF_10K_1%
PGND0 PGND1 SS/ENA PGND2 PGND3 VBAIS PGND4 Note for layout: This part has special pad on it's underside C628 0.01UF
+V3.3ALWAYS
R163 100_1% R162 100_1% R206
9,16,17,18,19,24,25,26,29,32,33,34,40
100K_1% U24 J42 OUT VCC RG2 SIGN 8 7 6 5 1 3 CON3_HDR Measurement Point 2 C365 0.1UF 1 2 3 4 SHDN NC RG1 GND MAX472
R205 10K_1% R215 221_1% 1 R216 5.49k_1% 2 1 R304 2 1 C345 2 C349 0.022uF
8200pF C336 0.1UF R166 4.99k_1%
10 mili ohm sense rstr and 100 ohm gain rstr. The full scale output is 2.5V at 0.5V per Amp.
NO_STUFF_0.01_1%
18,19,24,25,26,34,40
+V5
C387
+V2.5 7,8,13,40
C
18,19,24,25,26,34,40 18,19,24,25,26,34,40 +V5
+V5
10 VDD+ R256 10K NewPart
0.1UF
R265
9 6
8 NO_STUFF_1K_1%
R255 10K_1%
R266 EN_AMP 10K
+
GND 4
7 TLV2463 U47B R460 0 R254 10K_1% C378 0.01UF
R268
+V5
VDD+ 10
18,19,24,25,26,34,40
+V5
18,19,24,25,26,34,40
1 5 SM_VREF 6,10
3 NO_STUFF_0 R461 U51 VIN0 VIN1 VIN2 VIN3 VIN4 VSENSE C395 220PF R284 4.99k_1% C396 0.082uF R271 NO_STUFF_10K FSEL R462 0 NC/Comp STATUS BOOT RT 14,16,21,29,34,40 PM_SLP_S3# PM_SLP_S3# ENA PH0 PH1 PH2 PH3 PH4 PH5 PH6 PH7 PH8 PwrPad
+
GND 4
U47A TLV2463
C386 150uF
C393 150uF
C394 0.1UF
5 Amp 40 mOhms Coilcraft DT3316P-332 L14 1 NewPart 3.3uH 2
SM_VREF
Vtt Sense
B
+VDDR 9,16,17,18,19,24,25,26,29,32,33,34,40 +V3.3ALWAYS

R278
Single point sense near load +V1.25 6,12,13
AGND 0.01_1% C382 150uF R293 100_1% U53 1 2 3 4 SHDN NC RG1 GND MAX472 OUT VCC RG2 SIGN 8 7 6 5 Vddr_A 1 Vddr_A 3 CON3_HDR R294 100_1% R297 100K_1% J70 Measurement Point 2 C314 150uF C313 150uF C381 150uF C391 0.1UF
PGND0 PGND1 PGND2 PGND3 PGND4 VBAIS Note for layout: This part has special pad on it's underside REFIN C390 0.1UF
R280 3.92k_1% R279 267_1% C392 1 2 8200pF C397 0.022uF
C408 0.1UF
R301 4.99k_1%
R277 NO_STUFF_4.99k_1% Vtt Sense
10 mili ohm sense rstr and 100 ohm gain rstr. The full scale output is 2.5V at 0.5V per Amp.
DDR VR DDR VR
5 4 3 2
Title
DDR_VR
1
39
of
42
Design Guide
248
HDM Connector Assembly (base board)

J23 A1 A2 A3 A4
HDM conn. is a modulized conn. design in 2 parts. 3 9,16,17,18,19,24,25,26,29,32,33,34,39 pin power recepticle and a 72 pin recepticle. The 2 4,5,6,9,10,14,17,19,23,28,29,30,31,32,33,36,37 18,19 parts will be arranged as shown on this schematic +V3.3ALWAYS 14,17,19,21,24,27,29,34,36 +V3.3 +V3.3S -V12S page.
1 1 1 1 +VDC 36,37,38 R174 75 2 2 2 DS17 18,19 R53 2.2k -V12S C152 22UF 35V DS4 GREEN 18,19,24,25,26,34,39 +V5 C242 22UF +V5S 4,9,17,19,20,24,31,32,33,35,36,37 C199 22UF 1 +V12S 9,19,22,34,35 1 GREEN 1 2 DS15 GREEN 1 R168 75 2 2 DS7 GREEN 2 R134 75 1 2 DS9 GREEN R148 549_1%
9,19,22,34,35 +V12S 1 R157 549_1% 2 2 DS11 GREEN 1

D
CON3,RCPTL,TH,700000-667.Normal
D
D1 D2 D3 D4 F1 F2 F3 F4 3Pin_RECEPTICLE
C172 22UF 35V 9,16,17,18,19,24,25,26,29,32,33,34,39 +V3.3ALWAYS R128 56
7,8,17
+V1.8S J26 A1 A2 A3 A4 D1 D2 D3 D4 F1 F2 F3 F4 3Pin_RECEPTICLE J29 A1 F12 A2 F11 A3 F10 A4 F9 A5 F8 A6 F7 A7 F6 A8 F5 A9 F4 A10 F3 A11 F2 A12 F1 B1 E12 B2 E11 B3 E10 B4 E9 B5 E8 B6 E7 B7 E6 B8 E5 B9 E4 B10 E3 B11 E2 B12 E1 C1 D12 C2 D11 C3 D10 C4 D9 C5 D8 C6 D7 C7 D6 C8 D5 C9 D4 C10 D3 C11 D2 C12 D1 72Pin_RECEPTICLE(male) J34 A1 A2 A3 A4 18,19,24,25,26,34,39 R120 D1 D2 D3 D4 2 1 R111
4,5,6,9,10,14,17,19,23,28,29,30,31,32,33,36,37 +V3.3S R90 2 1 NO_STUFF_0.01_1% C117 22UF
C
4,9,17,19,20,24,31,32,33,35,36,37 +V5S 1
+V1.5S 7,9,36
18,19,24,25,26,34,39 +V5 1 R170 147_1% 22
2 DS6 GREEN
R164 147_1% 22
+V5S 4,9,17,19,20,24,31,32,33,35,36,37
7,8,17
+V1.8S 1 2 1 R449 200
29,34 AC_PRESENT# 29,34 SMC_SHUTDOWN 29,34 SMC_ONOFF# 29,33,34 SMB_SB_CLK 29,33,34 SMB_SB_DATA 29,33,34 SMB_SB_ALRT# 24,34 IDE_PPWR_EN 16,29,34 PM_SLP_S5# 14,16,21,29,34,39 PM_SLP_S3# 14,16,24,34 PM_SLP_S1# 29,36 PWR_PWROK 18,19 -V12S R92 2 1 NO_STUFF_0.01_1%
Q37 2N3904 2
DS13 GREEN 1 1
DS16 GREEN
2 1 NO_STUFF_0.01_1% R105 2 1 NO_STUFF_0.01_1% +UNUSEDV2.5S +UNUSEDV2.5
+V12S 9,19,22,34,35 +V1.8 17
9,16,17,18,19,24,25,26,29,32,33,34,39 9,16,17,18,19,24,25,26,29,32,33,34,39 9,16,17,18,19,24,25,26,29,32,33,34,39 9,16,17,18,19,24,25,26,29,32,33,34,39 +V3.3ALWAYS +V3.3ALWAYS +V3.3ALWAYS +V3.3ALWAYS R125 56 R158 56 R167 56 R136 56
+V5S_IDE_S
24
PS_ON_SW#
9,16,17,18,19,24,25,26,29,32,33,34,39 +V3.3ALWAYS
+V1.5ALWAYS 9 +V5ALWAYS 17,25,26
R110
2 1 NO_STUFF_0.01_1% C200 22UF
+V5ALWAYS is not connected on the Turner. You will need to rework a Turner to utalize it. (Turner Source = J2 pins 19 and 20)
1 2 1 R450 200
Q38 2N3904 2
1 2 1 R451 200
Q39 2N3904 2
1 2 1 R452 200
Q40 2N3904 2
1 2 1 R453 200
+V1.5ALWAYS is not connected on the Turner. You will need to rework a Turner to utalize it. (Turner Source = J13 pins 14 and 16)
7,8,13,39 +V2.5
DS5 GREEN 3 7,9,36 +V1.5S
DS12 GREEN 3
17 +V1.8
DS14 GREEN 3
17
+V1.8ALWAYS
2 DS8 GREEN 3
B
Q41 2N3904 2
+V1.8ALWAYS 17
NOTE: Pins D1 - D12 are used on Turner. (Do Not Use) NOTE: Turner pins are Sheeks pin + 11
4,9,17,19,20,24,31,32,33,35,36,37
+V5S R305 330 +V5 18,19,24,25,26,34,39 J77
+V5S 4,9,17,19,20,24,31,32,33,35,36,37 R310 330 SW5 2 4 6 8 10 12 16 3 4 1 2 Push button
23,24 IDE_PDACTIVE# +V5 4,5,6,9,10,14,17,19,23,28,29,30,31,32,33,36,37 +V3.3S C412 470PF SW6 3 4 1 2 Push button 1 R309 330 C415 2 1UF R308 10K C414 470PF C411 470PF
1 3 5 7 9 11 13 15
POWER
C410 470PF
C413 470PF
PS_ON_SW#
NO_STUFF_0.01_1%
RESET
HDR_2x8
14,17,19,21,24,27,29,34,36
+V3.3
R119 2 1 NO_STUFF_0.01_1%
F1 F2 F3 F4 3Pin_RECEPTICLE
3,5,36 MASTER_RESET#
Front Panel
Title
DC/DC Card Connector

Project: 845MP/MZ Platform m Sheet 40 of 42
Design Guide
249
PS_ON_SW# ATX PS
SW5
PM_PWROK 4
Turner ATX
PWR_PWROK 3
Power On Sequence
PCI_ICH_RST#
PG 40 U5A PG 36 ICH3
U7C PG 21
4
PM_SLP_S5# 7 MASTER_RESET#
U5B PG 15 PG 16 ADM1023
PM_LANPWROK
DOCKING PG 21
PG 40
SMC_SHUTDOWN
PG 5
PM_SLP_S3#
PM_RSMRST#
PM_PWRBTN#
PM_BATLOW#
VR_PWRGD
H_PWRGD
LPC PG 34
3
PM_THRM#
SMC_ONOFF# SMC_RST#
SMC U7D PG 29 SMC_RES# PG 29

FAN_ON
Q2 PG 27 Fan Power PG 35
LAN PG 27
MAX809 PG 30
SMC_PROG_RST#
2
PCI_RST_SLOTS#
PCI PG 18
2
Core VR
6
U11D PG 36 CPU PG 3
VR_ON
PG 36 U8 PG 30
INTERPOSER_PRES# H_CPURST#
MCH PG 6
AGP PG 9
PLD PG 4 ITP
Title
PG 5
A B C
Power On Check list

D
41
E
of
42
Design Guide
250
PS_ON_SW#
SW5 PG 40
Reset Map
PCI_ICH_RST# PCI_RST_SLOTS#
DC/DC Turner
4
SMC_SHUTDOWN PWR_PWROK
PG 40 SW6
PCI SLOTS PG18
U5A PG 36
PM_PWROK
ICH3-M PG 16
PM_RSMRST#
MASTER_RESET#
PG 40 Core VR PG 36
3
Q10 PG29
PCI_GATED_RST#
R=0 R=0
DOCKING ITP PG 5 U8 PG 30 SMC PG 21

PCI_RST_ONBD2#
PCI_RST_ONBD1#
LPC SLOT PG 34
U22 QSW PG 20 AGP SLOT PG 9 U23 EPROM PG 30 FWH PG 28
MAX809 PG 30
SMC_PROG_RST#
SMC_RST#
U7D PG 29
SMC_RES#
PG 29
H_CPURST#
MCH-M
H_PWRGD
SIO PG 31
CPU PG 6
1
PG 3
PLD
Title
Reset Map
E
PG 4
A B C
of
42
Design Guide
251

Mobile Pentium 4 M Ntel 845mp MZ Chipset Guide

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Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform

Order Number: 250688-002

Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform

Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform

Processor Power Requirements ................................................................................................ 40 4.1. 4.2.

Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform

4.7. 4.8. 4.9. 5. 5.1. 5.2.

AGP Port Design Guidelines ......................................................................................................85 6.1. 6.2. 6.3.

Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform

I/O Subsystem.......................................................................................................................... 100

Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform

Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform

Platform Power Guidelines....................................................................................................... 159 11.1. 11.2. 11.3.

Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform

System Design Checklist..........................................................................................................183

Customer Reference Board Schematics ..................................................................................210

Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform

Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform

Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform

Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform

Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform

Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform

Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform

Intel 82562ET LAN on Motherboard Design Guide (AP-414)

Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform

Document Intel 82562ET/EM PCB Design Platform LAN Connect (AP-412)

Document Number/Source Contact your Field Representative

Conventions and Terminology

Table 1. Conventions and Terminology

Bus Agent Corner

Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform

Convention/ Terminology Flight Time

Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform

Convention/ Terminology SSO

Stub Trunk Undershoot Victim VREF Guardband

Mobile Intel Pentium 4 Processor-M in 478- Pin Package

Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform

Intel 845MP/845MZ Chipset

Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform

Figure 1. Typical System Block Diagram

System Bus 400MT/S (3.2 GB/sec Data Rate)

4X AGP Graphic Controller

845MP/845MZ MCH-M 593 FC-BGA

8-Bit HUB Interface

6 USB 1.1 Port

2 ATA 66/100 IDE Channels

ICH3-M 421 mBGA

AC'97 Modem CODEC (Optional)

Intel Memory Controller Hub (MCH-M)

Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform

Processor System Bus Support

Integrated System Memory DRAM Controller

Accelerated Graphics Port (AGP) Interface

Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform

I/O Controller Hub (ICH3-M)

Firmware Hub (FWH)

Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform

Table 3. Platform Bandwidth Summary

Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform

General Design Considerations

Nominal Board Stackup