ABSTRACT

With the growing population of the country and its rising electric power need, the demands on the power grid continue to climb its ladder day by day. Particularly at the domain of mobile base station & networks, recent analysis by manufacturers and network operators has shown that current wireless networks are not very energy efficient, in specific to the base stations by which terminals access services from the network. A typical mobile phone network may consume approx 40-50MW, even excluding the power consumed by users handsets. When direct electricity connections are not readily available, these service providers use diesel to power their network. As a result, a polluted environment is established and a whole of about 1% of the total power generation is being consumed by the mobile networks itself. The ratio might seem to be a small sector but at industrial point of view it is extremely a huge sum. The specific object of this project is to provide a solution to this problem of power demand by means of implementing a technology that will enable efficient energy saving in BTS. To be precise its a pollution free technology where its aim is to keep only one mobile tower in active mode to take up all communications while the remaining towers are put into an idle state where there is no higher power consumption thereby saving power. When the users limit crosses the predetermined level, the neighboring towers are turned into active mode accordingly. Hence the project is to create an efficient method for reduction of total energy being consumed by the mobile tower. This approach also extends at the site of without any modification to the existing infrastructure. Thus the power could be saved at a greater rate. With the reduction in total power consumption the amount of carbon dioxide emissions into the atmosphere is being lowered, thereby providing a pollution free clean environment.

LIST OF FIGURES

FIGURE NO 1.1.a 1.1.b 2.1.a 2.2.1.a 2.2.2.a

FIGURE NAME Power Consumption In MCS Time Vs Cost In Mc Overall Block Diagram Resistor Color Code Polarized Capacitor And its Circuit Symbol

PAGE NO 2 2 9 10 12

2.2.2.b

Unpolarized Capacitor And its Circuit Symbol

13

2.2.3.a 2.2.3.b 2.2.4.a 2.2.5.a 2.2.6.a 3.1.a 3.1.1.a 3.1.2.a 3.1.3.a 3.1.5.a 3.1.6.a 3.2.a 3.2.b

Diodes And Its Circuit Symbol Zener Diode And Its Circuit Symbol Light Emitting Diode And Its Circuit Symbol Thermistor And Its Circuit Symbol LDR And Its Circuit Symbol Pic Overall Circuit Diagram Dual Power Supply Voltage Sensing Circuit Current Sensing Circuit Responder Frequency To Voltage Conversion Circuit Dc Voltage Measurement Circuit Bock Diagram Of Regulated Power Supply System Transformer And Its Waveform

14 15 16 17 18 19 21 24 26 27 28 29 29

3.2.c

Transformer With Rectifier And Its Waveform

30

3.2.d 3.2.e

Transformer With Rectifier and Smoothing Transformer With Rectifier, Smoothing And Regulator

30 30

3.2.2.1.a 3.2.3.a 3.2.4.a 3.3.5.a 3.5.a 3.5.2.a 3.6.a 3.7.a 3.9.a

Bridge Rectifier And Its Output Smoothing And Its Waveform Regulator Pin Diagram Of PIC16F877A ULN 2003 Pin Relay Driving Circuit Max 232 DB-9 Connector Transmitter And Receiver Circuit

33 33 34 37 41 43 44 46 49

LIST OF TABLES

TABLE NO 1.1a 3.7a

DESCRIPTION Power Consumption/Bts DB-9 Pin Detail

PAGE NO 2 46

LIST OF ABBREVIATIONS

AC ADC ADCON BCF CO CS CT DC DPST DPDT IC I/O LED LDR MCLR NC NO OST PGC PGD PGM PIC POR PSP

Alternating Current Analog - to - Digital Converter Analog to Digital Controller Bit Clear File Change-Over Chip Select Center Tap Direct Current Double Pole Single Throw Double Pole Double Throw Integrated Circuit Input/Output Light Emitting Diode Light Dependent Resistor Master Clear Reset Normally Closed Normally Open Oscillator Start-up Timer Programming Clock Programming Debug Programming Mode Peripheral Interface Controller Power-On Reset Parallel Slave Port

PUT PWM QPDT RAM RA RB RC RD RE RD/RW RISC RMS SSP SPST SPDT TRISA TRISB TRISC TRISD TRISE TTL USART VLSI VREF WR WDT

Power -Up Timer Pulse Width Modulation Quadruple Pole Double Throw Random Access Memory Port A Port B Port C Port D Port E Read/Write Reduced Instruction Set Computer Root Mean Square Synchronous Serial Port Single Pole Single Throw Single Pole Double Throw Temporary Storage Register A Temporary Storage Register B Temporary Storage Register C Temporary Storage Register D Temporary Storage Register E Transistor Transistor Logic Universal Asynchronous Receiver Transmitter Very Large Scale Integration Voltage Reference Write Watch Dog Timer