A quasi-analytical model for nanowire FETs with arbitrary polygonal cross section

L. De Michielis
a,
*
, L. Selmi
b
, A.M. Ionescu
a
a
Ecole Polytechnique Fdrale de Lausanne, Nanoelectronic Devices Laboratory (Nanolab), CH-1015 Lausanne, Switzerland
b
University of Udine, Dept. of Electrical, Managerial and Mechanical Engineering, 33100 Udine, Italy
a r t i c l e i n f o
Article history:
Available online 21 May 2010
The review of this paper was arranged by
Prof. S. Cristoloveanu
Keywords:
Silicon nanowire
Multi-gate MOSFET
Short-channel-effects
a b s t r a c t
In this work a quasi-analytical physical model has been developed for the prediction of the potential in
SiNW devices with arbitrary polygonal cross section. The model is then extended to the transport direc-
tion; a method for the calculation of the natural channel length has been proposed and validated by
means of 2D and 3D numerical device simulations. With the results based on the proposed model it is
possible to compare nanowires with cross sections of different shape and predict the minimum techno-
logical gate length able to assure immunity to the SCEs.
2010 Elsevier Ltd. All rights reserved.
1. Introduction
In a continuous effort to reduce the transistor dimensions tar-
geting higher packaging densities and faster circuit speeds, nano-
electronics is facing challenges in almost all the scaling rules, for
both physical and technological reasons. In particular reduction
of the channel length translates into a rapid rise in I
off
: primarily
due to the so-called short-channel-effects (SCEs) resulting from
the electrostatic perturbations that emanate from the source and
the drain regions affecting the control of the channel region [1].
The structure that is best placed to counter the SCEs is the gate-
all-around (GAA) MOSFET, which offers excellent electrostatic con-
trol and a very good subthreshold behavior. The ultimate in the
GAA architecture is the Silicon nanowire (SiNW) which has been
technologically demonstrated for different cross sections, most
common among them being the triangular [2], square [3], pentag-
onal [4] and cylindrical [2]. In this work we will develop a general
expression able to describe the electrostatics of NW MOSFETs of
arbitrary polygonal shape, and an original expression of the natural
length will be proposed, predicting the minimum technological
gate length L
G
able to assure good subthreshold characteristics.
2. Semi-analytical model for the potential in the cross section
The potential distribution in the bulk of a fully-depleted SiNW
MOSFET is governed by the Poissons equation:
r
2
u
q
c
e
Si
1
where q
c
is the charge density, approximately given by q N
A
in
the subthreshold region of a n-type device.
As shown in [6], the isolines of the potential inside the Silicon
core of GAA devices with a regular polygon as a cross section fol-
low a circular symmetry. This suggests to approximate the solution
of Eq. (1) in polar coordinate system as:
ur; h ur; 8h 2
This assumption yields:
1
r
d
dr
r
dur
dr
_ _

qN
A
e
Si
3
which is a simple differential equation of second order with the
general solution:
ur
q N
A
4 e
Si
r
2
K
1
lnr K
2

q N
A
4 e
Si
r
2
U
0
4
K
1
= 0 since at the center of the structure (i.e. r = 0) the potential has
a nite value u(0) = U
0
.
When a cylindrical cross section of radius R is considered, it
would be possible to calculate the potential at the center of the
cross section U
0
as shown in [6] using:
U
0
V
G
V
FB

qN
A
2e
ox
R
2
ln 1
t
ox
R
_ _

e
ox
2e
Si
_ _
5
In order to extend this approach for a generic GAA device with
an arbitrary regular polygon as a cross section, we observe that
essentially the same value for the potential at the center of the
structure should be expected, as long as the Silicon area of the
0038-1101/$ - see front matter 2010 Elsevier Ltd. All rights reserved.
doi:10.1016/j.sse.2010.04.039
* Corresponding author. Address: EPFL STI-IEL-NANOLAB, ELB 343, Station 11,
CH-1015 Lausanne, Switzerland.
E-mail address: Luca.DeMichielis@ep.ch (L. De Michielis).
URL: http://nanolab.ep.ch/ (A.M. Ionescu).
Solid-State Electronics 54 (2010) 929934
Contents lists available at ScienceDirect
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j our nal homepage: www. el sevi er . com/ l ocat e/ sse
cross section (that is the total depletion charge) is the same as that
of a circular device: Fig. 1 proves the validity of this assumption in-
side the depletion regime.
To this purpose, we can calculate the area of a generic regular
polygon (Fig. 2) using the relation:
Area apothem semiperimeter 6
Thus we need to calculate the apothem a (that is the inradius)
as:
a
W
G
2
cot
p
n
_ _
7
where n is the number of edges (hence of corners) of the polygon.
With these, the polygon area becomes:
Area
poly

W
G
2
cot
p
n
_ _

1
2
nW
G
8
In this way we can express the radius R
eq
of the circle with a Sil-
icon area equal to the area of the polygon as:
R
eq
W
G
r where r
1
2

n
p
cot
p
n
_ _
_
9
The potential inside the Silicon core will be expressed by Eq. (4),
where U
0
becomes:
U
0
V
G
V
FB

qN
A
2e
ox
W
2
G
r
2
ln 1
t
ox
W
G
r
_ _

e
ox
2e
Si
_ _
10
Fig. 3 demonstrates the agreement between Eq. (10) and
numerical simulations on a variety of polygonal NWs.
Once more, using Eq. (4) together with Eqs. (7) and (10) we can
derive the potential at the midpoint of an edge of the cross section
as:
U
E
U
0

qN
A
16e
Si
W
2
G
cot
2
p
n
_ _
11
3. The short-channel-effect
The SCEs are caused by the electric eld lines stemming from
the source and drain, penetrating into the channel, perturbing
the electrostatic distribution originally imposed by the gate and
degrading the subthreshold behavior. Fig. 4 represents a numerical
simulation of a SiNWdevice with a square cross section: these sim-
ulation are performed with the commercial simulator Sentaurus
Device version C2009.06 [5], in which the Poissons equation has
been solved fully coupled with the electron and hole current con-
tinuity equations. In order to include quantum effects in our clas-
sical device simulations, we have used the density gradient model
as it can describe the 2D and 3D quantization and gives a reason-
able description of the charge distribution inside the device. Hence,
our simulations are affected by the shift of the threshold voltage
Fig. 3. Comparison between simulated U
0
and the predictions of Eq. (10) for several different parameters of various polygonal devices. Geometrical parameters are dened in
Fig. 2.
Fig. 1. Numerical simulation [5] of the potential U
0
at the center of the cross
section as a function of the gate voltage for devices having the same silicon area and
different polygonal cross sections (i.e. triangular cross section: W
G
= 40.4 nm,
square: W
G
= 26.59 nm, hexagon: W
G
= 16.5 nm, decagon: W
G
= 9.59 nm);
N
A
= 10
16
cm
3
, t
ox
= 5 nm. Geometrical parameters are dened in Fig. 2.
Fig. 2. Sketch of the cross section of a GAA device with an arbitrary regular
polygonal shape, showing the notations used in this work. W
G
: edge length; n:
number of the edges.
930 L. De Michielis et al. / Solid-State Electronics 54 (2010) 929934
and reduction of the gate capacitance that are typical in small
MOSFETs. A simple mobility model accounting for phonon scatter-
ing has been activated. Observing the I
DS
V
GS
characteristics of
the low doped device it is possible to note that when the channel
length is reduced, the device exhibits a reduction of the threshold
voltage V
T
, termed the threshold voltage roll-off due to SCE. Sub-
sequently, if the drain bias in such an extremely scaled device with
a low doped core is increased, a further degradation of the thresh-
old voltage, called Drain Induced Barrier Lowering (DIBL) would be
observed. However, as shown in Fig. 4, these detrimental effects
disappear in highly doped GAA devices.
As explained in [6], it is possible to develop a semi-analytical
model that allows the calculation of the natural length k of a SiNW
with a regular polygon as a cross section. As will be shown next,
potential lines inside the channel region from source to drain fol-
low a prole that can be described by a combination of exponen-
tials. Thus, from a physical point of view, the potential
emanating from the source (or the drain) penetrates inside the
channel region and is attenuated following an exponential law.
As usual when dealing with exponentially varying physical phe-
nomena, the speed that describes this attenuation can be charac-
terized by a constant of decay, here the natural length, that is an
index of how much the perturbation is able to penetrate inside
the channel. Hence, the natural length describes how robust the
architecture of a GAA MOSFET is against SCEs.
It is important to observe that these devices exhibit a multitude
of natural lengths: in particular, as we saw in our 3D numerical
simulations, the minimum value is found along the corners of
the cross section where the proximity of the two gates assures
the best control of the electrostatics; the highest values (i.e. the
worst case) of the natural length is at the midpoint of the edges
of the cross section. In [6], the value of the natural length at the
midpoint of the edge, k
E
, for a GAA with a regular polygonal cross
section of n edges has been calculated as:
k
E

W
G
rt
ox
2
e
Si
e
ox

12
However, we observe in Fig. 5 that in a highly doped device
subthreshold current is located near the Silicon/oxide interface,
while in a low doped device current ows mainly at the center.
This is caused by the shift of the threshold voltage due to differ-
ent doping levels. Moreover, the at band voltage in a low doped
(or quasi-intrinsic) MOSFET is smaller compared to its highly
doped counterpart. For these reasons, as seen in Fig. 6, the con-
duction in the subthreshold region takes place mainly in the
accumulation region for the low doped case, and in depletion re-
gion for the high doped one. This would explain why Eq. (12) has
high accuracy in only describing the total current of SiNW devices
with high core doping. In [6], we have also proposed a model that
enables the calculation of the natural length describing the con-
duction at the center of the device, and the resulting expression
is:
k
0

rW
G
2

1
2e
Si
e
ox
ln 1
t
ox
rW
G
_ _

13
Fig. 7 reports k
E
and k
0
for triangular and square cross sectional
wires. k
0
is larger than k
E
for the larger part of the explored W
G
and
t
ox
range, and therefore this more stringent requirement should be
respected for devices with low channel doping during the design of
polygonal wires. Note that for device dimensions of W
G
$ 15 nm or
smaller, quantum effects detach the inversion layer from the SiSi
dioxide interface, thus contributing to de-conne the conduction
towards the center of the structure. For this reason, extremely
scaled devices should be scaled in accordance with Eq. (13) even
for the highly doped case.
Using Eq. (12) or Eq. (13) it is possible to calculate the potential
from the source to the drain, at the center of the edge or at the cen-
ter of the Silicon core of a GAA MOSFET with a gate length L
G
, as
[7]:
Fig. 4. Numerical simulation of a GAA SiNW with a square cross section and two
different gate lengths to demonstrate the short-channel-effects. Observe also that in
the GAA structures higher channel doping provides better control of the SCEs.
W
G
= 50 nm, t
ox
= 2 nm, the gate material is polysilicon N
D
= 10
20
cm
3
, and the
source and drain regions are doped N
D
= 10
19
cm
3
. Quantum corrections are taken
into account using the density gradient model.
Fig. 5. Longitudinal cross section of SiNW with square cross section (whose characteristics are reported in Fig. 4) describing the conduction due to the minority carriers in the
subthreshold region. Both pictures refer to: I
DS
50 pA, V
DS
= 75 mV. Left: core doping N
A
= 10
14
cm
3
, V
GS
= 0.9375 V. Right: core doping N
A
= 3 10
18
cm
3
,
V
GS
= 0.3125 V. Quantum corrections are taken into account using the density gradient model.
L. De Michielis et al. / Solid-State Electronics 54 (2010) 929934 931
Uz U

V
DS
sinh
z
k
_ _
sinh
L
G
k
_ _
Uz 0 U

sinh
z
k
_ _
sinh
L
G
z
k
_ _
sinh
L
G
k
_ _ 14
where U
*
is the long channel surface potential given by Eq. (11) or
Eq. (10) respectively. Fig. 8 validates Eq. (14) for two different GAA
MOSFETs with square cross section with SiO
2
and HfO
2
as the oxide
material. In all cases a good agreement with the model is veried.
Observing the variation of the DIBL, V
T
-roll-off and the increase
of subthreshold slope as a function of the gate length normalized
by the natural length k, as proposed in [6], it is not possible to ob-
serve a unique trend. This is mainly due to the fact that, below
threshold, the corner contribution to the total current can be
non-negligible, and this can be particularly important for devices
with smaller cross sectional areas. For this reason, we propose in
this work an empirical model based on a large number of simu-
lated devices, that enables the calculation of the natural length as:
k
0;corrected
k
0
a b
W
G
c lnt
ox
15
for devices with low core doping, and:
Fig. 6. Top: left-potential distribution along a line cross cutting the cross section; right-free carrier concentration for the low doped case and the high doped case (Bottom).
Fig. 7. Comparison between the natural length k
E
(Eq. (12)) describing the
subthreshold behavior in high doped devices, and k
0
(Eq. (13)) for low doping.
For a given t
ox
and total width W = nW
G
, triangular SiNWs are better than those with
a square cross section.
Fig. 8. Numerical 3D simulations of a SiNW with a square cross section showing the
agreement of Eqs. (12)(14) with the potentials at the center and at the surface, for
a standard SiO
2
and a High-K oxide material. W
G
= 50 nm, T
ox
= 2 nm,N
A
= 10
14
cm
3
.
Table 1
Table for the parameters of Eqs. (15) and (16).
LowDop, n = 3 HighDop, n = 3 LowDop, n = 4 HighDop, n = 4
a 4.4 2.06 7.88 0.016
b 0.049 1.012 0.142 1.053
c 1.26 0.182 2.60 0.586
932 L. De Michielis et al. / Solid-State Electronics 54 (2010) 929934
k
E;corrected
k
E
a b
W
G
t
c
ox
16
for high doped cases; the values of the tting parameters are re-
ported in Table 1.
Using Eqs. (15) and (16) we have reported in Fig. 9 the DIBL and
the subthreshold slope as a function of the normalized channel
length, for a number of different GAAs considered.
Judging by Fig. 9, a criterion of L
G
/2k
corrected
> 2.5 can be imposed
on Eqs. (15) and (16) in order to compute the relation between the
core periphery (that is, the equivalent device width W), t
ox
and L
G
for SiNWs of different shapes and provide a design space assuring
safely low SCEs. An example of this design space is proposed in
Fig. 10 for the case of low core doping, and it is possible to observe
that for a given technology (e.g. t
ox
= 3 nm, L
G
= 100 nm) the SiNW
with a triangular cross section offers a higher on-current, while
preserving at the same time a good off-performance; this is also
conrmed by the numerical simulations of Fig. 11. However, it is
worth noting that the analytical model developed in this work does
not take into account the quantum effects whereby for extremely
small device dimensions the inversion layer is detached from the
Silicon oxide interface. Thus, for extremely small cross sections
there is no longer a direct proportionality between the effective
width of the device and the on-current levels. In any case, for gate
lengths smaller than 40 nm, the validation of the approach de-
scribed in this chapter would need a more in-depth discussion
and systematic investigations both from the theory and simula-
tions point of view, but this is beyond the scope of this paper.
Moreover, triangular cross section devices can be more subject
to reliability problems due to the high levels of eld building-up in
their corners. Usually, corner rounding techniques such as anneal-
ing under H
2
are used to circumvent this problem.
4. Conclusion
In this work a general analytical model to describe the potential
of a GAA SiNW FETs with arbitrary regular polygon as a cross sec-
tion has been proposed and validated with a large number of
numerical simulations on 3D structures. The model predicts the
potential distribution in the transverse and longitudinal directions
with good accuracy and for a wide range of NW geometries. These
results have been used with the aim of characterizing the SCEs of
these types of structures and predict the minimum gate length re-
quired to assure good subthreshold characteristics: our model and
simulation results (in which quantum corrections has been taken
into account using the density gradient model) conrm that a min-
imum gate length L
G
larger than ve times the derived value for the
natural length insures immunity to SCE, DIBL, and a close to ideal
subthreshold slope.
Fig. 10. Design space for triangular and square cross section SiNWs, with the
assumption of low channel doping (Eq. (15)), as a function of the total width.
Observe the larger design space offered by the triangular cross section. The points A
and B refer to the devices compared in Fig. 11.
Fig. 11. Comparison between the characteristics of the two devices A and B of
Fig. 10: with the same technology (i.e. t
ox
= 3 nm and L
G
= 100 nm) the triangular
SiNW offers higher I
on
and a better subthreshold slope. Quantum corrections are
taken into account using the density gradient model.
Fig. 9. Top: DIBL. Bottom: increase of the subthreshold slope as a function of the normalized gate length L
G
/k. Data refers to SiNWs with triangular (M) and square (h) cross
sections, and two different doping levels: N
A
= 10
14
cm
3
and N
A
= 3 10
18
cm
3
. The dimensions of the symbols are proportional to the dimension of the cross section (i.e.
W
G
= {100, 60, 50, 25, 20, 15} nm); the thickness of the symbols is related to the oxide thickness (i.e. thick black: t
ox
= 10 nm; medium blue: t
ox
= 5 nm; thin red: t
ox
= 2 nm). L
G
ranging from 150 nm down to 15 nm. (For interpretation of the references to colour in this gure legend, the reader is referred to the web version of this article.)
L. De Michielis et al. / Solid-State Electronics 54 (2010) 929934 933
Acknowledgments
The authors would like to thank Suat Ayz for the helpful dis-
cussions. This work was partially supported by NANOSIL NoE
(FP7 IST-216171).
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