A 32-Bit Modified Carry Select Adder with Reduced Area and Low power Consumption

V.PavanKumar1, N.RajeevPankaj2
1, 2

School of Electronics Engineering

VIT University Vellore, Tamilnadu, India. 1 {pavan.vlsi43}@gmail.com 2{nrajeevpankaj}@vit.ac.in

Abstract: Arithmetic units play a major role in a general microprocessor. In these arithmetic units full adder plays a crucial role. Full adder is an essential component in the design of all the processors such as viz. microprocessor, digital signal processors etc. But mainly power dissipation in processors is due to adder in the arithmetic units. Minimising the power consumption of circuits is important for a wide variety of applications both because of the increasing levels of integration and the desire for portability. This paper presents performance analysis of different fast adders of 32 bit. The comparison is done on the basis of three performance parameters i.e. area, speed and power consumption. This paper proposes a new modified carry select adder with clock sharing which is better in terms of area and power. Here all these adders are designed using Verilog; Xilinx Project Navigator 9.1i is used for simulation. Cadence RTL Compiler is used for implementing the designs. Keywords: Adders, Verilog, Xilinx, Low Power, Cadence RTL Compiler

The most important parameter controlling power consumption is the supply voltage because of the square term of voltage in the total power equation.

I.

INTRODUCTION

As mentioned earlier, reducing power consumption will make your chip run faster and last longer, may reduce the required size and complexity of both your power supply and your cooling system, and perhaps enable you to use a less expensive package. And, of course, reducing power consumption is absolutely critical in battery powered applications. II. FAST ADDERS

The demands of selecting the optimised circuit architecture are based on two parameters such as low power dissipation and high speed. In mobile communication equipments and portable computers the battery life can be increased, when the adders consumed a minimum power. There are four factors which influence the power dissipation of cmos circuits such as technology, circuit design style, architecture and algorithm. There are three major sources of power consumption in digital CMOS circuits, which are given as below in the following equation. P total = P dynamic + P short-circuit + P static = 0 1 CL VDD2 F+ VDD I short circuit + VDD I leakage The 1st term in the equation represents the switching component of power, where the load capacitance CL, F is the clock frequency and 0 1 is the switching activity factor. The 2nd term in the equation is due to the short circuit currents, I short circuit, which arises when both the NMOS and PMOS transistors are simultaneously come into ON state, posing current directly from supply to ground. The 3rd term in equation is I leakage, which will arise from substrate injection and sub threshold effects.

A. Ripple Carry Adder (RCA) A Ripple Carry Adder is a digital circuit that produces the arithmetic sum of two binary Numbers. It can be constructed using one-bit full adders connected in serial, with the carry output from each full adder connected to the carry input of the next full adder in the chain. Figure 1 show the interconnection of four full adder (FA) circuits to provide a 4-bit ripple carry adder.

Figure 1 Block Diagram of 4 bit RCA [4]

It can be noted from Figure 1 that the input starts from the right side since the first cell traditionally represents the least significant bit (LSB). Bits x0 and y0 are the LSB bits of the numbers to be added. The Summation output is represented by (s0... s3). . The

delay of ripple carry adder is a linear function of the number of bits. Thus, as the number of bits increases the delay increases as well. Therefore RCA is the slowest in all adders (O (n) time) but it is very compact in size (O (n) area).The expressions for sum and carry are given as
CS1

1AP1+P2-1-AP1
0

BP1+P2-1-BP1

P2bitadd er 0

Si = Ai xor Bi xor Ci Ci+1 = Ai Bi + (Ai + Bi) Ci; where i = 0, 1 n-1 B. Carry Select Adder (CSA) The N-bit carry select adder which divides the N-bit into one N/2 bit for the LSB bits and two N/2 bits for the remaining MSB bits.Of theses two N/2 bit adder one is calculated using the input 0 and the other is calculated using input 1.The final sum and carry are calculated using a mux i.e the carry from one N/2 bit adder for LSB,which is used as select line for the mux ,by using this select line the final sum and carry are selected.The architecture of CSA is as shown in Figure 2
ci n

AP1+P2-1-AP1 BP1+P2-1-BP1 AP1-1-A0 BP1-1-B0 1 P1bitadder A2n-1-AP1+P2 B2n-1-BP1+P2 P2bitadd er

OP1+P21-OP1

CS2 OP1-1-O0 0 P2bitadd er 0 1 1 P2bitadd er O2n-1-OP1+P2

A2n-1-AP1+P2 B2n-1-BP1+P2

cout

An
Ar/2-A0 Br/2-B0 0 cin n/2 bit adder

Ar-1-Ar/2

Ar-1-Br/2

Figure 3 Variable Carry Select Adder [8]

n n/2 bit adder

Ar-1-Ar/2

A Ar-1-Br/2

0 1

Or-10r/2

Cr/2-C0

D. Carry Select Adder with Clock Sharing (CSAS) This adder which is going to overcome the disadvantage of carry select adder .In CSA the area is more compared to that of ripple carry adder .Instead of using two N/2 bit adders for MSB in CSA ,here only one N/2 bit adder is used as shown in Figure 4,therefore the area is going to be decrease.

n/2 bit adder

c cin
Figure 2 Carry Select Adder [8]

The advantage of this CSA is which speeds up the addition process and consumes less power compared to that of RCA. The usage of two N/2 bit adders for the MSB bits increases the area compared to that of RCA. C. Variable Carry Select Adder (VCSA) The variable carry select adder, which is similar to that of carry select adder as discussed above, but here the N/2 bit adder for the MSB bits is divided in two different stages as shown in Figure 3.The main advantage of this adder is to reduce the delay compared to that of CSA. The Figure 3 which is a three stage Variable carry select adder reduces the delay compared to that CSA shown in Figure 2 .The VCSA shown in figure 3which reduces the delay as well as power .The given N-bit is divided into p1 bit adder for LSB bit and the MSB bit adder is divide into two p2 bit adder and two p3 bit adder as shown in Figure 3, by using mux the final sum and carry are calculated, Like the three stage adder we can similarly design the 4 and 5 stage adder.

Figure 4 Carry Select Adder with Clock Sharing [8]

The Figure 4 shows the architecture of carry select adder with clock sharing, in which there are only two adders i.e. 22 bit adder and 10 bit adder. The 22 bit adder is a RCA which calculates the sum and carry, other 10 bit adder which is also a RCA with input as clock. When the clock is high the input is taken as 1 and the sum and carry are calculated and saved in latch. When the clock is low the input is taken as 0 and the result which is given to the mux, the output of latch is also given to mux .Therefore the final sum and carry are calculated by using the mux i.e. the carry coming from the first 22 bit adder for LSB acts as a select line and gives the final result. This Carry select adder with clock sharing which has low power and less delay compared to that of CSA and RCA.

Figure 6 Proposed Adder I E. Variable Carry Select Adder with Clock Sharing (VCSAS) This is also similar to that of carry select adder with clock sharing, but the N/2 bit adders for the MSB are further divided so as to reduce the delay.
A15-A0 B15-B0

Cin

16 bit Adder

O15-O0 A23-A16 B23-B16

The operation same to that of a CSA i.e. the N bit is divide into Three N/2 bit Adders, one is for LBS and the other two are for MSB. The one N/2 bit adder for LSB which calculates the sum and carry. The two N/2 bit adders for MSB ,the first N/2 Bit adder which takes the input as 0 and Calculates the carry and sum ,the second N/2 bit adder which takes the input as 1 and calculates the sum and carry. The final sum and carry are calculated by using the mux based on the select line coming from the initial N/2 bit adder i.e. carry from the first N/2 bit adder B. Proposed Adder II:

8bit adder
A31-A24 B31-B24

latch 0
O23-O16

8 bit adder

latch
CLK

This is the other proposed adder in this paper which is similar to that of carry select adder with clock sharing. In CSAS the addition is done by using RPC, here the addition is done using Carry look Ahead adder which reduce the delay and power compared to that of the other adders in this paper

0 1

O31-O24 Cout

Figure 5 Variable Carry Select Adder with clock sharing [8]

cin

22bitcla adder

The Figure 5 shows the architecture of variable carry select adder with clock sharing, with reduce delay and low power consumption .The above techniques is a three stage VCSAS which reduces the delay. By using the same technique we can design the 4 and 5 stages of the above adder. These 4 and 5 stages adders which reduce further delay and power compared to the other adders mentioned above. III PROPOSED ADDERS

1 10bit cla adder

A. Proposed Adder I This is one of the proposed adders in this paper, which is similar to that of CSA. In CSA the N/2bit adder is calculation is done through RPC, but here the calculation is done through Carry Look Ahead adder. Since Carry Look Ahead adder is faster and consumes less power this adder is used .Therefore the overall power and delay are going to be reduced compared to CSA.
Ar-1-Ar/2 Ar-1-Br/2

Figure 7 Proposed Adders II The figure 7 shows the architecture of proposed adder, the operation is explained with help of an example. A 32 bit adder, in which LSB 22 bit addition is done with help of a carry look ahead adder and the remaining 10 bit addition is done in such a way that the clock is given as input .when the clock goes high the input is takes as 1 and the result is saved in a latch and the output of a latch is given to the mux .when the clock goes low the input is taken as 0 and the result is calculated and given to the mux. The final sum and carry are calculated using the mux based on the select line which is coming from the initial 22 bit adder. Thus the final result which has less delay and low power

Ar/2-A0

Br/2-B0 0

n n/2 cla adder

Ar-1-Ar/2

cin

n/2 cla adder

A Ar-1-Br/2

0 1

Or-10r/2

Cr/2-C0

n/2 cla adder

IV

LAYOUT

A .Layout of Variable carry select adder with clock sharing:

Table II provides the area ,power and delay reports of Carry Select Adder, variable Carry Select Adder, carry select adder with clock sharing, variable carry select adder with clock sharing ,of theses adders CSAS and VCSAS has less delay and power

Table II Reports of Different Adders presented in paper

Area(m2) CSA VCSA CSAS VCSAS B. Layout of Proposed Adder II: 3779 4016 2428 2538

Power(mw) 59.163 59.115 54.261 52.21

Delay(ns) 36.723 30.894 35.136 29.457

Table III which provides the Area, power and delay of proposed adders, which has better performance compared to that of all the adders mentioned above .
Table III Reports of Proposed Adders

Area(m2) Proposed Adder I Proposed Adder II 3948 2641

Power(mw) 57.59 33.762

Delay(ns) 34.048 30.260

VI V RESULTS

CONCLUSION

Table I provides the comparison of area power and delay of Ripple Carry Adder and Carry look Ahead Adder ,of which CLA has less delay and power compared to that of RCA
Table I Comparison between RCA and CLA

This Paper addresses the behaviour of various adders in terms of area, power and delay. Of these the proposed adder, which has less delay and low power consumption. All the adders are 32 bit wide and are designed using verilog (HDL),Xilinx Project Navigator 9.1i is used as a synthesis tool and Cadence RTL Compiler is used for simulation and implementing the designs, and the back end i.e. layout for the VCSAS and proposed adder are done using SOC Encounter. REFERENCES [1] K. Rawwat, T. Darwish, and M. Bayoumi, .A low power carry select adder with reduces area,.Proc. of Midwest Symposium on Circuits and Systems, pp. 218221, 2001.

Area(m2) RCA CLA 2235 2368

Power(mw) 59.344 57.59

Delay(ns) 71.885 50.898

[2] A. Tyagi, .A reduced area scheme for carry-select adders,. IEEE Trans. on Computer, vol. 42, pp.11631170, 1993 [3] W. Jeong and K. Roy, .Robust high-performance low power adder,. Proc. of the Asia and South Pacific Design Automation Conference, pp. 503-506, 2003 [4]Improved Carry Select Adder with Reduced Area and Low Power Consumption [5] Y. Kim and L-S Kim, .64-bit carry-select adder with reduced area,. Electronics Letters, vol. 37,4pp. 614615, May 2001. [6] O. Kwon, E. Swartzlander, and K. Nowka, .A fast hybrid carry-look ahead/carry-select adder Design,. Proc.of the 11th Great Lakes symposium on VLSI, pp.149-152, March 2001. [7] K. Rawwat, T. Darwish, and M. Bayoumi, A low power carry select adder with reduces area, Proc. of Midwest Symposium on Circuits and Systems, pp. 218-221, 2001.
[8]Behnam Amelifard, Farzan Fallah, and Massoud Pedram, "Closing the gap between carry select adder and ripple carry adder: a n e w c l a s s o f l o w -power h i g h performance a d d e r s ", in Proc. of IEEE International Symposium on Quality Electronic Design (ISQED), 2005.

[9] W. Jeong and K. Roy, Robust high-performance low- power adder, Proc. of the Asia and South Pacific Design Automation Conference, pp. 503-506, 2003 [10] Y. Kim and L-S Kim, 64-bit carry-select adder with reduced area, Electronics Letters, vol. 37, pp. 614-615, May 2001. [11]O.Kwon,E.Swartzlander,and K. Nowka, A fast hybrid carry-lookahead/carry-select adder design, Proc. of the 11th Great Lakes symposium on VLSI, pp.149-152, March 2001.