CXD3059AR

CD Digital Signal Processor with Built-in RF Amplifier and Digital Servo + Digital High & Bass Boost
Description The CXD3059AR is a digital signal processor LSI for CD players. This LSI incorporates a RF amplifier and digital servo, high & bass boost, 1-bit DAC and analog low-pass filter. Features All digital signal processing during playback is performed with a single chip Highly integrated mounting possible due to a built-in RF amplifier RF Block Supports 4 speed playback CD RF system equalizer Supports pickup built-in RF summing amplifier Gain level switch TE balance adjustment function Digital Signal Processor (DSP) Block Supports CAV (Constant Angular Velocity) playback Frame jitter free 0.5 to 4 speed continuous playback possible Allows relative rotational velocity readout Supports variable pitch playback The bit clock, which strobes the EFM signal, is generated by the digital PLL. EFM data demodulation Enhanced EFM frame sync signal protection Refined super strategy-based powerful error correction C1: double correction, C2: quadruple correction Supported during 4 speed playback Noise reduction during track jumps Auto zero-cross mute Subcode demodulation and subcode-Q data error detection Digital spindle servo 16-bit traverse counter Asymmetry correction circuit CPU interface on serial bus Error correction monitor signal, etc. output from CPU interface Servo auto sequencer Fine search performs track jumps with high accuracy Digital audio interface outputs Digital level meter, peak meter Bilingual compatible VCO control mode CD TEXT data demodulation Digital Servo (DSSP) Block Microcomputer software-based flexible servo control Offset cancel function for servo error signal Auto gain control function for servo loop E:F balance, focus bias adjustment functions Surf jump function supporting micro two-axis Tracking filter: 6 stages, Focus filter: 5 stages Digital Filter, DAC and Analog Low-pass Filter Blocks Digital dynamic bass boost and high boost Bass Boost: 4th-order IIR 24dB/Oct +10dB/+14dB/+18dB/+22dB High Boost: Second-order IIR 12dB/Oct +4dB/+6dB/+8dB/+10dB Independent turnover frequency selection possible Bass Boost: 125Hz/160Hz/200Hz High Boost: 5kHz/7kHz

120 pin LQFP (Plastic)

Digital dynamics (compressor) Volume increased by +5dB at low level 8 oversampling digital filter (attenuation: 61dB, ripple within band: 0.0075dB) Digital signal output possible after boost Serial data format selectable from (output) 20 bits/18 bits/16 bits (rearward truncation, MSB first) Digital attenuation: , 60 to +6dB, 2048 steps (linear) Soft mute Digital de-emphasis High-cut filter Applications CD players Structure Silicon gate CMOS IC Absolute Maximum Supply voltage 1 Input voltage 1 Output voltage 1 Supply voltage 2 Ratings (Ta = 25C) VDD, XVDD VSS 0.5 to +3.5 V VSS 0.3 to VDD + 0.3 V V I1 VO1 VSS 0.3 to VDD + 0.3 V IOVDD0 to 2, AVDD0 to 5 IOVSS 0.5 to +4.5 V Input voltage 2 V I2 IOVSS 0.3 to IOVDD + 0.3 V IOVSS 0.3 to IOVDD + 0.3 V Output voltage 2 VO2 Storage temperature Tstg 55 to +150 C Supply voltage difference IOVSS, AVSS, XVSS VSS 0.3 to +0.3 V 0.3 to +0.3 V XVDD VDD IOVDD, AVDD, XVDD VDD 0.3 to +0.3 V (IOVDD, AVDD, XVDD < 2.3V) V V C pF pF pF

Recommended Operating Conditions 2.5 0.2 Supply voltage 1 VDD, XVDD Supply voltage 2 IOVDD0 to 2, AVDD0 to 5 3.3 0.3 Operating temperature Topr 20 to +75 I/O Pin Capacitance Input capacitance CI Output capacitance CO I/O capacitance CI/O Note) Measurement conditions 7 (Max.) 7 (Max.) 7 (Max.) VDD = VI = 0V fM = 1MHz

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

1
E03736-PS

CXD3059AR

Block Diagram
WDCK WFCK SQSO EMPH SCOR SYSM SQCK COUT SBSO XUGF C2PO SENS CLOK EXCK DATA SSTP ATSK SCLK

SERVO Block MIRR DFCT FOK LOCK MDP SFDR SRDR TFDR TRDR FFDR FRDR PWM Generator SERVO Interface MIRR DFCT FOK

CPU Interface Bass Boost Block LMUT RMUT LPF AOUT2 VREFR VREL AOUT1 EMPHI LRCKI PCMDI BCKI

XLAT

GFS

DAC

LPF

SERVO DSP CD Signal Prosessor Block Servo Auto Sequencer Digital CLV D/A Interface TE Error Corrector FE EFM Demodulator A B C D VC VC APC ATT EQ AMP SUM RFamp Block Asymmetry Corrector Digital PLL DC/DC Convertor Sub Code Processor 32K RAM Digital OUT Clock Generator

XTACN XTSL XTAI XTAO VCTL VPCO DOUT BCK Selector PCMD LRCK

TEI FEI A/D Converter

TEO E F FEO

XRST TES1 TEST AVDD0 to 5 AVSS0 to 5 IOVDD0 to 2 IOVSS0 to 2 VDD VSS

RFC

BIAS

ASYI

FILI

PDSENS

RFDCO

DDVROUT

RFACO

DDVRSEN

AC_SUM

EQ_IN

RFACI

DDCR

LD

ASYO

CLTV

FIFO

PD

PCO

XPCK

CXD3059AR

Pin Configuration
VREFR IOVDD0 AOUT2 AOUT1 VREFL IOVDD2 IOVSS2 AVDD1 EMPHI AVDD2 AVSS2 AVSS1 DOUT EMPH PCMDI LRCKI PCMD RMUT

XTAO

XVDD

TEST

TES1

VDD

90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

LMUT 91 NC 92 XTSL 93 IOVSS0 94 XTACN 95 SQSO 96 SQCK 97 SBSO 98 EXCK 99 XRST 100 SYSM 101 DATA 102 VSS 103

NC

LRCK

XVSS

XTAI

BCK

VSS

NC

60 BCKI 59 NC 58 DDCR 57 AVSS5 56 DDVRSEN 55 DDVROUT 54 AVDD5 53 PCO 52 FILI 51 FILO 50 CLTV 49 AVSS3 48 VCTL 47 VPCO 46 ASYO 45 ASYI 44 BIAS 43 AVDD3 42 RFACI 41 RFACO 40 AVSS4 39 RFC 38 NC 37 PD 36 LD 35 EQ_IN 34 AC_SUM 33 PDSENS 32 RFDCO 31 AVDD4

XLAT 104 CLOK 105 VDD 106 SENS 107 SCLK 108 ATSK 109 WFCK 110 XUGF 111 XPCK 112 GFS 113 C2PO 114 SCOR 115 VDD 116 C4M 117 WDCK 118 COUT 119 NC 120

1
MIRR

2
DFCT

3
FOK

4
VSS

5
LOCK

6
MDP

7
SSTP

8
IOVSS1

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
SFDR SRDR TFDR TRDR FFDR FRDR TEI TEO FEI FEO NC VC IOVDD1 AVDD0 AVSS0 NC E A B C D F

CXD3059AR

Pin Description Power supply Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A/D 3.3V 16 17 18 19 20 21 22 23 24 25 26 RFamp 3.3V 27 28 29 30 31 32 33 34 Symbol MIRR DFCT FOK VSS LOCK MDP SSTP IOVSS1 SFDR SRDR TFDR TRDR FFDR FRDR IOVDD1 AVDD0 AVSS0 NC E F TEI TEO FEI FEO VC A B C D NC AVDD4 RFDCO PDSENS I/O I/O I/O I/O I/O 1, 0 1, 0 1, 0 1, 0 Mirror signal input/output. Defect signal input/output. Focus OK signal input/output. Internal digital GND. GFS is sampled at 460Hz; when GFS is high , this pin outputs a high signal. If GFS is low eight consecutive samples, this pin outputs low. Or this pin inputs when LKIN = "1". Disk innermost detection signal input. 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 E signal input. F signal input. Tracking error signal input to DSSP block. Tracking error signal output from RF amplifier block. Focus error signal input to DSSP block. Focus error signal output from RF amplifier block. Center voltage output from RF amplifier block. Center voltage input to DSSP block by command switch. A signal input. B signal input. C signal input. D signal input. Analog power supply. RFDC signal output. RFDC signal input to DSSP block by command switch. Reference voltage pin for PD. I/O digital GND. Sled drive output. Sled drive output. Tracking drive output. Tracking drive output. Focus drive output. Focus drive output. I/O digital power supply. Analog power supply. Analog GND. Description

Digital I/O = 3.3V Internal = 2.5V

O 1, Z, 0 Spindle motor servo control output. I O O O O O O I I I O I O I/O I I I I I/O I

AC_SUM O Analog RFAC summing amplifier output. 4

CXD3059AR

Power supply

Pin No. 35 36 37

Symbol EQ_IN LD PD NC RFC AVSS4 RFACO RFACI AVDD3 BIAS ASYI ASYO VPCO VCTL AVSS3 CLTV FILO FILI PCO AVDD5 DDVROUT DDVRSEN AVSS5 DDCR NC BCKI PCMDI LRCKl LRCK VSS PCMD BCK VDD EMPH EMPHI I O I I O I I I O I I I O I I I I I O O O O I

I/O Equalizer circuit input. APC amplifier output. APC amplifier input.

Description

RFamp 3.3V

38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

Equalizer cut-off frequency adjustment pin. Analog GND. RFAC signal output. RFAC signal input or EFM signal input. Analog power supply. Asymmetry circuit constant current input. Asymmetry comparator voltage input. 1, 0 EFM full-swing output. (Low = VSS, High = VDD) Wide-band EFM PLL VCO2 control voltage input. Analog GND. Multiplier VCO1 control voltage input. Master PLL filter input. Analog power supply. DC/DC converter output. Leave open when not using. DC/DC converter output voltage monitor pin. Connect to analog power supply when not using. D/A interface bit clock input. D/A interface serial data input. (2's COMP, MSB first) D/A interface LR clock input. 1, 0 1, 0 1, 0 1, 0 D/A interface LR clock output. f = Fs Internal digital GND. D/A interface serial data output. (2's COMP, MSB first) D/A interface bit clock output. Internal digital power supply. High when the playback disc has emphasis, low it has not. High when de-emphasis is ON, low when input OFF. 5 Analog GND. DC/DC converter reset pin.

ASYM 3.3V

O 1, Z, 0 Wide-band EFM PLL charge pump output.

O Analog Master PLL (slave = digital PLL) filter output. O 1, Z, 0 Master PLL charge pump output.

DC/DC 3.3V

56 57 58

59 60 61 62

Digital I/O = 3.3V Internal = 2.5V

63 64 65 66 67 68 69

CXD3059AR

Power supply

Pin No. 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94

Symbol IOVDD2 DOUT TEST TES1 IOVss2 NC XVSS XTAO XTAI XVDD AVDD1 AOUT1 VREFL AVSS1 AVSS2 VREFR AOUT2 AVDD2 NC IOVDD0 RMUT LMUT NC XTSL IOVSS0 XTACN SQSO SQCK SBSO EXCK O I I O I O O O O O O I I O I O I I I I I

I/O 1, 0 I/O digital power supply. Digital Out output. Test pin. Normally GND. Test pin. Normally GND. Master clock GND. I/O digital GND.

Description

Digital I/O = 3.3V Internal = 2.5V

X'tal 2.5V

Crystal oscillation circuit output. Crystal oscillation circuit input. Master clock power supply. Analog power supply. Lch analog output. Lch reference voltage. Analog GND. Analog GND. Rch reference voltage. Rch analog output. 1, 0 1, 0 Crystal selection input. Low when the crystal is 16.9344MHz; high when the crystal is 33.8688MHz. I/O digital GND. Oscillation circuit control. Self-oscillation when high, oscillation stop when low. 1, 0 Subcode Q 80-bit and PCM peak and level data output. CD TEXT data output. SQSO readout clock input. 1, 0 Subcode P to W serial output. SBSO readout clock input. System reset. Reset when low. Mute input. Muted when high. Serial data input from CPU. Internal digital GND. Latch input from CPU. The serial data is latched at the falling edge. 6 I/O digital power supply. Rch "0" detection flag. Lch "0" detection flag. Analog power supply.

Lch 3.3V

Rch 3.3V

Digital I/O = 3.3V Internal = 2.5V

95 96 97 98 99

100 XRST 101 SYSM 102 D ATA 103 VSS 104 XLAT

CXD3059AR

Power supply

Pin No.

Symbol I O I I/O O O O O O O O O I/O

I/O

Description Serial data transfer clock input from CPU.

105 CLOK 106 VDD 107 SENS 108 SCLK 109 ATSK 110 WFCK 111 XUGF 112 XPCK Digital I/O = 3.3V 113 GFS Internal = 2.5V 114 C2PO 115 SCOR 116 VDD 117 C4M 118 WDCK 119 COUT 120 NC

1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0

Internal digital power supply. SENS output to CPU. SENS serial data readout clock input. Anti-shock input/output. WFCK output. XUGF output. Output MNT0, RFCK, SOUT by command switch. XPCK output. Output MNT1, SOCK by command switch. GFS output. Output MNT2, XROF, XOLT by command switch. C2PO output. Output MNT3, GTOP by command switch. High output when the subcode sync, S0 or S1, is detected. Internal digital power supply. 4.2336MHz output. 1/4 frequency-division output of the V16M in CAV-W mode and variable pitch mode. Word clock output. f = 2Fs. GRSCOR output by command switch. Track number count signal input/output.

Notes) PCMD is a MSB first, two's complement output. GTOP is used to monitor the frame sync protection status. (High: sync protection window released.) XUGF is the frame sync obtained from the EFM signal, and is negative pulse. It is the signal before sync protection. XPCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the EFM signal transition point coincide. The GFS signal goes high when the frame sync and the insertion protection timing match. RFCK is derived from the crystal accuracy, and has a cycle of 136s. C2PO represents the data error status. XROF is generated when the 32K RAM exceeds the 28 frame jitter margin. C4M is a 4.2336MHz output that changes in CAV-W mode and variable pitch mode. FSTO is the 2/3 frequency-division output of the XTAI pin. SOUT is the serial data output inside the servo block. SOCK is the serial data readout clock output inside the servo block. XOLT is the serial data latch output inside the servo block.

CXD3059AR

Monitor Pin Output Combinations Command bit SRO1 0 0 0 0 1 MTSL1 0 0 1 1 0 MTSL0 0 1 0 1 0 XUGF MNT0 RFCK C4M SOUT Output data XPCK MNT1 XPCK GSTO SOCK GFS MNT2 XROF GFS XOLT C2PO MNT3 GTOP C2PO C2PO

Reset Timing when Power on Power on with XRST pin low. Set XRST pin high after holding it low 100ns or more to cancel reset.

CXD3059AR

RF Block Pin Equivalent Circuit Pin No. Symbol I/O Equivalent circuit Description

19

19

VC

Tracking error amplifier input.

20

20

VC

21

TEI

21

Tracking error signal input to DSSP block.

22

TEO

1pF 22

Tracking error amplifier output.

23

FEI

23

Focus error signal input to DSSP block.

1pF

24

FEO

O
24

Focus error amplifier output.

25

VC

I/O
25

(AVDD4 AVSS4)/2 voltage output.

CXD3059AR

Pin No.

Symbol

I/O

Equivalent circuit

Description

26

I
15k 26

27

I
27

30k

RF summing amplifier and focus error amplifier input.

28

28 30k 29

29

30 31

NC AVDD4

10k

Analog power supply.

32

RFDCO

I/O

0.5pF 100 32

RFDC amplifier output.

33

PDSENS

10k 33

59k

APC amplifier reference voltage (GND signal) input.

34

AC_SUM

34

RFAC summing amplifier output.

10

CXD3059AR

Pin No.

Symbol

I/O

Equivalent circuit

Description

35 4k

35

EQ_IN

4k

Equalizer circuit input.

4k

4k VC

36

LD

57k 10k 500 36

APC amplifier output.

37

PD

1k 37

APC amplifier input.

38

NC

39

39

RFC

Equalizer cut-off frequency adjustment.

40

AVSS4

Analog GND.

41

RFACO

VC

25 41

RFAC amplifier output.

11

CXD3059AR

Electrical Characteristics 1. DC Characteristics (VDD = XVDD = 2.5 0.2V, IOVDD0 to 2 = AVDD0 to 5 = 3.3 0.3V, VSS = XVSS = IOVSS = AVSS = 0V, Topr = 20 to +75C) Item High level input voltage Low level input voltage High level input voltage Input voltage (2) Low level input voltage Hysteresis Input voltage (3) Output voltage (1) Input voltage VIH (1) VIL (1) VIH (2) VIL (2) Vt+ Vt VIN (3) Analog input IOH = 2.4mA IOL = 4mA IOH = 1.2mA IOL = 2mA IOH = 2.4, 4.8, 7.2, 9.6mA IOL = 4, 8, 12, 16mA IOH = 0.28mA IOL = 0.36mA VIN = VSS or VDD VIN = VDD VIN = VSS or VDD 10 40 10 100 VDD 0.4 V 0.4 10 240 10 A A A 1, 2, 9 3 8 VDD 0.4 V 0.4 VDD 0.4 V 0.4 VSS VDD 0.4 V 0.4 Schmitt input 0.5 VDD V 4, 12 0.7VDD 0.2VDD V 2 Conditions Min. 0.7VDD V 0.2VDD Typ. Max. Unit Applicable pins 1, 3, 9

Input voltage (1)

High level VOH (1) output voltage Low level VOL (1) output voltage High level VOH (2) output voltage Low level VOL (2) output voltage High level VOH (3) output voltage Low level VOL (3) output voltage High level VOH (4) output voltage Low level VOL (4) output voltage II IIH IOZ

5, 8, 9

Output voltage (2)

Output voltage (3)

Output voltage (4)

11

Input leak current Input leak current (with pull-down resistor) Tri-state output leak current (when high impedance)

12

CXD3059AR

Applicable pins 1 PCMDI, EMPHI, TEST, TES1, XTSL, XTACN, SYSM, DATA 2 BCKI, LRCKI, SQCK, EXCK, XRST, XLAT, CLOK, SCLK 3 SSTP 4 E, F, TEI, FEI, A, B, C, D, PDSENS, EQ_IN, PD, RFC, RFACI, BIAS, ASYI, VCTL, CLTV, FILI, DDVRSEN, DDCR 5 SFDR, SRDR, TFDR, TRDR, FFDR, FRDR, LRCK, PCMD, BCK, EMPH, RMUT, LMUT, SQSO, SBSO, WFCK, XUGF, XPCK, GFS, C2PO, SCOR, C4M, WDCK 6 ASYO 7 DOUT 8 MDP, VPCO, PCO, SENS 9 MIRR, DFCT, FOK, LOCK, ATSK, COUT 10 TEO, FEO, AC_SUM, LD, RFACO, DDVROUT, AOUT1, VREFL, VREFR, AOUT2 11 FILO 12 VC, RFDCO

13

CXD3059AR

2. AC Characteristics (1) XTAI pin (a) When using self-oscillation (VDD = XVDD = 2.5 0.2V, IOVDD0 to 2 = AVDD0 to 5 = 3.3 0.3V, VSS = XVSS = IOVSS = AVSS = 0V, Topr = 20 to +75C) Item Oscillation frequency Symbol fMAX Conditions XTSL = L, $AEXX1 CKSL (1, 0) = 00 XTSL = H, $AEXX1 CKSL (1, 0) = 00 XTSL = H, $AEXX1 CKSL (1, 0) = 01 or 10 or 11 Min. 16.8 33.5 67.1 Typ. 16.9344 33.8688 67.7376 Max. 17.1 34.2 68.4 MHz Unit

(b) When inputting pulses to XTAI pin (VDD = XVDD = 2.5 0.2V, IOVDD0 to 2 = AVDD0 to 5 = 3.3 0.3V, VSS = XVSS = IOVSS = AVSS = 0V, Topr = 20 to +75C) Item High level pulse width Low level pulse width Pulse cycle Input high level Input low level Rise time, fall time Symbol tWHX tWLX tCX VIHX VILX tR , t F 0 Min. 6.6 6.6 14.6 1.7 0.7 10 Typ. Max. 32.7 32.7 59.5 Unit ns ns ns V V ns

tCX tWHX tWLX VIHX VIHX 0.9

XTAI

VDD/2

VIHX 0.1 VILX tR tF

Note) When the pulse is input to the XTAI pin, be sure to input it via the capacitor. 14

CXD3059AR

(2) CLOK, DATA, XLAT, SQCK and EXCK pins (VDD = XVDD = 2.5 0.2V, IOVDD0 to 2 = AVDD0 to 5 = 3.3 0.3V, VSS = XVSS = IOVSS = AVSS = 0V, Topr = 20 to +75C) Item Clock frequency Clock pulse width Setup time Hold time Delay time Latch pulse width EXCK frequency EXCK pulse width SQCK frequency SQCK pulse width COUT frequency (during input) COUT pulse width (during input) Symbol fCK tWCK tSU tH tD tWL fT tWT fT tWT fT fWT 7.5 750 750 0.65 120000 65 62.5 300 300 300 750 0.65 30000 Min. Typ. Max. 16 30000 Unit MHz ns ns ns ns ns MHz ns MHz ns kHz s

Only when $44 and $45 are executed.

1/fCK tWCK CLOK tWCK

DATA tWSC XLAT EXCK SQCK COUT tWT 1/fT SBSO SQSO tSU tH tWT tSU tH

tD

tWL

15

CXD3059AR

(3) SCLK pin

XLAT tDLS tSPW

SCLK 1/fSCLK Serial Read Out Data (SENS)

...

MSB

...

LSB

(VDD = XVDD = 2.5 0.2V, IOVDD0 to 2 = AVDD0 to 5 = 3.3 0.3V, VSS = XVSS = IOVSS = AVSS = 0V, Topr = 20 to +75C) Item SCLK frequency SCLK pulse width Delay time Symbol fSCLK tSPW tDLS 31.3 15 Min. Typ. Max. 16 Unit MHz ns s

(4) COUT, MIRR and DFCT pins Operating frequency (VDD = XVDD = 2.5 0.2V, IOVDD0 to 2 = AVDD0 to 5 = 3.3 0.3V, VSS = XVSS = IOVSS = AVSS = 0V, Topr = 20 to +75C) Item COUT maximum operation frequency MIRR maximum operation frequency DFCT maximum operation frequency 1 When using a high-speed traverse TZC 2
B

Symbol fCOUT fMIRR fDFCTH

Min. 40 40 5

Typ.

Max.

Unit kHz kHz kHz

Conditions 1 2 3

When the RF signal continuously satisfies the following conditions during the traverse. A = 0.11VDD to 0.23VDD B 25% A+B

3 During complete RF signal omission. When settings related to DFCT signal generation are Typ.

16

CXD3059AR

1-bit DAC and LPF Block Analog Characteristics (VDD = XVDD = 2.5V, IOVDD0 to 2 = AVDD0 to 5 = 3.3V, VSS = XVSS = IOVSS = AVSS = 0V, Topr = +25C) Item Total harmonic distortion Signal-to-noise ratio Symbol THD S/N Conditions 1kHz sine wave, 0dB data, 20kHz LPF 1kHz sine wave, 0dB data, AMUT OFF (Using A-weighting filter 20kHz LPF) 90 Min. Typ. Max. Unit % dB

0.006 0.014 95

Fs = 44.1kHz in all cases. The total harmonic distortion and signal-to-noise ratio measurement circuits are shown below.

100 AOUT1 (2)

22F Audio Analyzer 2200pF 100k

VREFL (R) 1F

LPF external circuit diagram

Rch DATA TEST DISC RF CXD3059AR Lch

A Audio Analyzer B

Block diagram of analog characteristics measurement

(VDD = XVDD = 2.5V, IOVDD0 to 2 = AVDD0 to 5 = 3.3V, VSS = XVSS = IOVSS = AVSS = 0V, Topr = +25C) Item Output voltage Load resistance VREF pin capacitance Symbol VOUT RL CVREF Min. 920 10 1 Typ. 928 Max. Applicable pins 1 mVrms 1 k F 2 Unit

Measurement is conducted for the above circuit diagrams with the sine wave output of 1kHz and 0dB. Applicable pins 1 AOUT1, AOUT2 2 VREFL, VREFR 17

RF Block Electrical Characteristics (VDD = XVDD = 2.5V, IOVDD0 to 2 = AVDD0 to 5 = 3.3V, VSS = XVSS = IOVSS = AVSS = 0V, Topr = +25C)
Bias conditions Measurement item Symbol SW conditions Connect to VC except measurement pins. 2.5V 3.3V Sending command AC input AC input DC input amplitude frequency voltage DC input current VDD AVDD Measurement conditions Measurement pins Min. Typ. Max. Unit

Input impedance (A, B, C and D) Input impedance (E and F) Input impedance (PD) RF block current consumption (on operation)

RA,B,C,D

Pin current

A, B, C, D

10

15

20

RE,F

Pin current

E, F

21

30

39

RPD

Pin current

PD

10

IAVD

$3AF100 2.5V 3.3V

Pin current

AVDD4

40

70

mA

VC

APC

18

RF block current consumption (on standby) Output voltage

ISTB

$ADF7CC00

Pin current

AVDD4

mA

VVC

3mA

2.5V 3.3V Pin voltage

VC

0.5AVDD 0.1 100 AVDD 0.2 1.89

0.5AVDD

0.5AVDD + 0.1 200

Input voltage Output voltage (on standby)

VPD

PD input voltage which LD, PD LD pin voltage is 1.41V Pin voltage LD

150

mV

VLDstb

$AD000800 VPD + 12mV VPD 12mV 0

VPDT Input voltage range VPDB Maximum output current Output impedance

0 2.5V 3.3V 0

Pin voltage

LD

2.14

2.39

Pin voltage

LD

0.43

0.68

0.93

ILD

1mA

Pin voltage

LD

0.34

0.64

0.94

CXD3059AR

RLD

VPD

1mA

Pin voltage

LD

1.66

1.91

2.16

Bias conditions Measurement item Symbol SW conditions Sending command AC input AC input DC input amplitude frequency voltage DC input current VDD AVDD Measurement conditions Pin voltage, A+B+C+D Pin voltage Measurement pins Min. Typ. Max. Unit

Input voltage range Output voltage range

VIR-ACSUM

RFDC

0.5AVDD 0.1 0.47AVDD 0.5AVDD 0.23

0.9AVDD + 0.1 0.65AVDD 0.5AVDD + 0.23

VOR-ACSUM

RFDC

Input conversion VOF-ACSUM DC offset voltage ACSUM Input conversion VDF-ACSUM DC offset temperature drift Offset voltage VOFFSUM

$3AA000

Pin voltage

RFDC

$3AA01C

2.5V

3V Pin voltage RFDC 0.7 4

V/ C 1.1 1 V dB

0.9 0

Frequency FSUM1 characteristics 1 Frequency FSUM2 characteristics 2 Distortion rate Input voltage range Output voltage range DSUM VIR-RFDC

$3AA004

61mVp-p 0.2/6MHz VC + VAC1/2 20 log (V6M/V0.2M) RFDC

$3AA018

104mVp-p 600mVp-p 3MHz VC + VAC1/2 (V6M/V3M) 100 Pin voltage, A+B+C+D Pin voltage RFDC RFDC

1 3

dB % V

RFDC

19

0.3AVDD 0.1 0.25AVDD 0.3AVDD 0.23

0.7AVDD + 0.1 0.75AVDD 0.3AVDD + 0.23

VOR-RFDC

RFDC

Input conversion VOF-RFDC DC offset voltage Input conversion VDF-RFDC DC offset temperature drift Frequency FRFDC1 characteristics 1 Frequency FRFDC2 characteristics 2 Distortion rate DRFDC

$3AA000

Pin voltage

RFDC

$3AA01C

2.5V

3V

V/ C

$3AA004

61mVp-p 0.2/6MHz VC + VAC1/2 20 log (V6M/V0.2M) RFDC

dB

$3AA018

104mVp-p 1.5Vp-p 100kHz RFDC

0 0.1

dB

CXD3059AR

Bias conditions Measurement item Symbol SW conditions Sending command AC input AC input DC input amplitude frequency voltage DC input current VDD AVDD Measurement conditions VC reference about (B + D) and (A + C) Pin voltage Measurement pins Min. Typ. Max. Unit

Input voltage range Output voltage range

VIR-FE

FE

0.375 AVDD 0.5 0.5AVDD 0.03

0.625 AVDD AVDD 0.5 0.5AVDD + 0.03

VOR-FE

FE

Input conversion VOF-FE DC offset voltage Input conversion VDF-FE DC offset temperature drift Offset voltage VOFFFE $3AA104 30mVp-p 10/ 100kHz $3AA118 52mVp-p 600mVp-p 50kHz

Pin voltage

FE

FE

2.5V

3V Pin voltage FE 0.06 1 20 log (V100k/V10k) FE 1 (V50k/V100k) 100 VC reference about (B + D) and (A + C) Pin voltage FE TE 0.4AVDD

2.8

V/ C 0.06 1 V dB

0 0

Frequency FFE1 characteristics 1 Frequency FFE2 characteristics 2 Distortion rate Input voltage range Output voltage range DFE VIR-TE

1 3 0.6AVDD AVDD 0.5 0.5AVDD + 0.03

dB % V

TE

20

VOR-TE

TE

0.5 0.5AVDD 0.03

Input conversion VOF-TE DC offset voltage Input conversion VDF-TE DC offset temperature drift Offset voltage VOFFTE $3AA204 28mVp-p 10/ 100kHz $3AA218 $3AA200 45mVp-p 480mVp-p 50kHz 2.5V 3V

Pin voltage

TE

2.5

V/ C 0.075 1 V dB

Pin voltage

TE

0.075 1

0 0

Frequency FTE1 characteristics 1 Frequency FTE2 characteristics 2 Distortion rate DTE

20 log (V100k/V10k)

TE

CXD3059AR

1 (V50k/V100k) 100 TE

1 3

dB %

Bias conditions Measurement item Symbol SW conditions Sending command AC input AC input DC input amplitude frequency voltage DC input current VDD AVDD Measurement conditions Distortion rate 3% or less, no DC bias Pin voltage Measurement pins Min. Typ. Max. Unit

Input voltage range Output voltage range

VIR-EQ

RFACO

250 AVDD 0.5 0.25

mVp-p

VOR-EQ

RFACO

0.5

Input conversion VOF-EQ DC offset voltage Input conversion VDF-EQ DC offset temperature drift Offset voltage VOFFEQ $3AA204 28mVp-p 10/ 100kHz $3AA218 $3AA200 45mVp-p 1.2Vp-p 360kHz

Pin voltage

RFACO

0.25

EQ

2.5V

3V

Ta = 20 to +75C

0.1

Pin voltage

RFACO

0.5 1

0 0

0.5 1

V dB

Frequency FEQ1 characteristics 1 Frequency FEQ2 characteristics 2 Distortion rate DEQ

20 log (V100k/V10k)

RFACO 1 0 1 3 dB %

21

(V720k/V360k) 100 RFACO

CXD3059AR

CXD3059AR

Notes on Operation for RFC Pin Set each impedance of the heavy line shown bellow 0.1 or less. Make each wiring length of L1 to L4, L1 20mm, L2 20mm and L3 + L4 40mm. Use the bypass condenser C with capacitance led by resistance (regulator output impedance and wiring resistance to C) or more seeing the figure bellow.

5 Regulator GND OUT 4 3 2 1 C L1 15k 0.1F L2 0 0 20 40 C [F] 60 80 100

R AVS 0.1F

L3

L4

AVSS4

RFC

AVDD4

22

R []

Impedance R tolerance for bypass condenser C

CXD3059AR

DC-DC Converter Characteristics (VDD = XVDD = 2.5 0.2V, IOVDD0 to 2 = AVDD0 to 5 = 3.3 0.3V, VSS = XVSS = IOVSS = AVSS = 0V, Topr = 20 to +75C) Item Output voltage Output current Symbol VO Iope Conditions Min. 2.3 Typ. 2.5 Max. 2.7 100 Unit V mA

DDVROUT DDCR R1 C1 C2

VOUT

DC-DC converter application circuit sample

(1) C2 is the oscillation stopping capacitor. Since there is possibility of an oscillation when the capacity value changes by temperature change etc., the electrolytic capacitor with small internal series resistance (ESR) is recommended. Capacitance 100F is recommended. (Should be 50F or more) (2) Since protection circuit is built in the DC-DC converter output, it operates when an overcurrent flows. Cancelling after protection circuit operation needs to make power supply voltage 0.7V or less once. After that, when you switch ON power supply, set XRST pin in the condition of low. To cancel the reset, set high after holding XRST low 100ns or more after power ON. (3) The R1 and C1 of application circuit example have the constant assuming that power supply rise time is 400ms or less. When it is 400ms or more, it is necessary to enlarge the value of R1 C1.

23

CXD3059AR

CPU Interface Timing

750ns to 30s CLOK

DATA

D0

D1

D18

D19

D20

D21

D22

D23 750ns or more

XLAT Registers Valid

Spindle Output
n . 236 (ns) n = 0 to 31 Acceleration MDP 132kHz 7.6s Deceleration Z

Acceleration MDP 264kHz 3.8s Deceleration Z

Servo Output
MCK (5.6448MHz) Output value + A SLD 64tMCK SFDR SRDR AtMCK AtMCK 64tMCK 64tMCK Output value A Output value 0

FCS/TRK 32tMCK FFDR/ TFDR FRDR/ TRDR A tMCK 2 32tMCK A tMCK 2 A tMCK 2 A tMCK 2 32tMCK 32tMCK 32tMCK 32tMCK

24

CXD3059AR

DA Interface CDDSP output selected (1 speed playback LRCK = 44.1kHz, BCK = 2.1168MHz)
LRCK 1 BCK WDCK PCMD R0 Lch MSB (15) L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 Rch MSB 2 3 4 5 6 7 8 9 10 11 12 24

DAC output selected (1 speed playback LRCK = 44.1kHz, BCK = 2.8224MHz) $A5EA OBIT1 = 1, OBIT0 = 1
LRCK 1 BCK WDCK PCMD R0 Lch MSB (15) L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 Rch MSB 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32

$A5EA OBIT1 = 1, OBIT0 = 0

PCMD R0 Lch MSB (17) L16 L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 Rch MSB

$A5EA OBIT1 = 0, OBIT0 = 0

PCMD R0 Lch MSB (19) L18 L17 L16 L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 Rch MSB

DAC block input timing (LRCK = 44.1kHz, BCK = 2.1168MHz)

LRCKI 1 BCKI PCMDI R0 Lch MSB (15) L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 Rch MSB 2 3 4 5 6 7 8 9 10 11 12 24

25

CXD3059AR

Application Circuit
Rch Lch

EMPH

RMUT

DOUT

BCK PCMD LRCK

90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

XVDD

RMUT IOVDD0

AVDD2

AVSS2

AVSS1

AVDD1

IOVSS2

IOVDD2

XVSS

VDD

NC

NC

BCK

VSS

XTAO

PCMD

DOUT

EMPH

LRCK

XTAI

TES1

TEST

AOUT2

VREFL

VREFR

AOUT1

LMUT

91 LMUT 92 NC 93 XTSL

LRCKI PCMDI

EMPHI

BCKI 60 NC 59

DDCR 58 AVSS5 57 DDVRSEN 56 DDVROUT 55 AVDD5 54 PCO 53 FILI 52 FILO 51 CLTV 50 AVSS3 49 VCTL 48 VPCO 47 ASYO 46 CXD3059AR ASYI 45 BIAS 44 AVDD3 43 RFACI 42 RFACO 41 AVSS4 40 RFC 39 NC 38 PD 37 LD 36 EQ_IN 35 AC_SUM 34 PDSENS 33 RFDCO 32 RFDCO PD LD A.GND D C Driver circuit DDVROUT

94 IOVSS0 95 XTACN 96 SQSO 97 SQCK SQSO SQCK XRST SYSM DATA XLAT CLOK SENS SCLK SCOR FOK SBSO 98 SBSO 99 EXCK 100 XRST 101 SYSM 102 DATA 103 VSS 104 XLAT 105 CLOK 106 VDD 107 SENS 108 SCLK 109 ATSK WFCK XUGF XPCK GFS C2PO 110 WFCK 111 XUGF 112 XPCK 113 GFS 114 C2PO 115 SCOR 116 VDD C4M WDCK COUT 117 C4M 118 WDCK 119 COUT

IOVSS1

IOVDD1

AVDD0

SRDR

TRDR

LOCK

DFCT

SSTP

MIRR

MDP

FRDR

SFDR

TFDR

FFDR

TEO

FOK

VSS

FEO

120 NC

AVSS0

AVDD4 31

TEI

FEI

NC

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

NC

VC

LOCK

DFCT

MIRR

B A VC F E FD TD Driver circuit SLED SPDL

Limit switch

Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

26

CXD3059AR

Package Outline

Unit: mm

120PIN LQFP (PLASTIC)

18.0 0.2 16.0 0.1
90 61

1.7 MAX 1.4 0.1 S 0.1 S

91

60

120

31

30

0.5 0.1 0.05

0.1

0.6 0.15

0.25

(17.0)

b = 0.20 0.03

0 to 10 DETAIL A

DETAIL B

0.125 0.03

(0.5)

PACKAGE STRUCTURE
PACKAGE MATERIAL EPOXY RESIN PALLADIUM PLATING COPPER ALLOY 0.8g

SONY CODE EIAJ CODE JEDEC CODE

LQFP-120P-L01 LQFP120-P-1616

LEAD TREATMENT LEAD MATERIAL PACKAGE MASS

27

Sony Corporation