4.ic &ecad Lab Manual (With Readings)

IC APPLICATIONS & ECAD LAB
PART - A
VIIT, Department of Electronics and Communication
Engineering Page 1
BASIC OPERATIONAL AMPLIFIER APPLICATIONS
Experiment No: 1-A
AIM: To study a summing, scaling and averaging amplifier are to be realized in inverting
mode and con-inverting mode and a summer and subtractor in differential mode and also as
a voltage follower is to be realized.
APPARATUS:
S.NO. Equipment Specification Quantity
1 Operational amplifier 741 IC 1
2 Bread board - 1
3 CRO - 1
4 Function Generator (0 1)MHz 1
5 Regulated power supply (0 30)V 1
6
Resistors
3 K 1
2 K 1
1 K 1
7 Connecting wires - -
THEORY:
1. INVERTING SUMMING AMPLIFIER:
A typical summing amplifier with three input voltages V
1
, V
2
and V
3
with resistors
R
1,
R
2
and R
3
and feedback resistor R
f
is shown in fig(a) for following analysis assuming
that the op-amp is an ideal one, that is A
OL
=
and R
i
=
since the input bias current is

assumed to be zero, there is no voltage drop across the resistor R
comp
and hence non
inverting input terminal is at ground potential.
The voltage at node a is zero as the non-inverting input terminal is grounded the
nodal equation by KCL at node a is
3 0 1 2
1 2 3
0 1 2 3
1 2 3
0
f
f f f
V V V V
R R R R
R R R
V V V V
R R R
+ + +
_
+ +

,
Thus the output is an inverted weighted sum of inputs in the special case, when
R
1
=R
2
=R
3
=R
f
we have V
0
=-(V
1
+V
2
+V
3
). In practical circuit input bias current
compensation resistor R
comp
. To find R
comp,
make all inputs V
1
+V
2
+V
3
= 0 so that effective
input resistance R
i
= R
1
11R
2
11R
3
R
com
= R
i
11R
f
.
2. NON INVERTING SUMMING AMPLIFIER:
Engineering Page 2
A summer that gives a non inverted sum is the non inverting summing amplifier of
figure b. Let the voltage at the ve input terminal to be V
a
. The voltage at +ve input
terminal will also be V
a
. The nodal equation at node a is given by
1 2 3 0
1 2 3
3 0 1 2
1 2 3
0
0
1 2 3
0
1 1 1
a a a
f
f
f
V V V V V V V
R R R R
V V V V
R R R R
V
V
R R R R

+ + +
+++
+++
The op-amp and two resistors R
f
and R constitute a non inverting amplifier with
0
1
f
a
a
R
V V
R
_
+

,
.
3 0 1 2
1 2 3
0 0
0
1 2 3
1
1 1 1
f f
a
f
V V V V
R R R R R
V V
V
R
R R R R
_
+ + +

_

+

,
+ + +

,
3. SUBTRACTOR:
A basic differential amplifier can be used a subtractor as shown in fig(d). If all
resistors equal in value, then the output voltage can be derived by using superposition
principal. To find the output V
01
due to V
1
alone, make V
2
=0 then the circuit becomes a
non inverting amplifier having input voltage V
12
at the non inverting amplifier input
terminal and the output becomes.
1
01 1
1
2
V R
V V
R
1
+
1
]
0.
Similarly the ;output V
02
due to V
2
alone can be written simply for an inverting amplifier as
V
02
= - V
2
.
Thus the output voltage V
0
due to both the inputs can be written as V
0
= V
01
+ V
02
= V
1

V
2
.
4. ADDER SUBTRACTOR:
It is possible to perform addition and subtraction simultaneously with a single
op-amp using the circuit shown in fig. The output voltage V
0
can be obtained by using
Engineering Page 3
superposition theorem. To find out voltage
1
01 1
/ 2 2
V R
V V
R
, similarly, the output

voltage V
02
due to V
2
alone is V
02
= - V
2
.
Now the output voltage V
03
due to the input voltage signal V
3
alone applied at the
+ve input terminal can be found by setting V
1
,V
2
and V
4
equal to zero. The voltage V
a
at
the non-inverting terminal is
3
3
/ 2
/ 2 3
a
V R
V V
R R

+
so the output voltage V
03
due to V
3
alone is
3
03 3
1 3
/ 2 3
a
V R
V V V
R
_ _
+

, ,
Similarly, it can be shown that the output voltage V
04
due to V
4
alone is V
04
= V
4
. Thus the
output voltage V
0
due to all four input voltage is given by
0 01 02 03 04
V V V V V + + +
( ) ( )
3 4 1 2
V V V V + +
Engineering Page 4
CIRCUIT:
Engineering Page 5
Voltage follower:
TABULAR FORMS:
Inverting configuration
In inverting configuration output voltage
Vo= -[R
f
/R
a
Va+R
f
/R
a
V
b
+R
f
/R
c
V
c
].
Summing amplifier
Take R
a
= R
b
= R
c
= R
f
Vo= - (Va+V
b
+Vc)
S.NO.
Input Voltage (v)
Vo(practical
in volts)
Vo(theoretical
in volts)
Va V
b
V
c
1
2
1
2
2
4
3
6
-5.98
-11.98
-6
-12
Scaling amplifier
Take R
a
= R
b
= R
c
= R
f
Vo= -[(
R
f
/R
a)
V
a
+
(
R
f
/R
b)
V
b
+
(
R
f
/R
c)
V
c
]
S.NO.
Input Voltage (v)
Vo(practical
in volts)
Vo(theoretical
in volts)
Va V
b
V
c
1
2
1
2
2
4
3
6
-5.98
-11.98
-6
-12
Engineering Page 6
Non-Inverting configuration
Take R
a
= R
b
= R
c
= R
f
-[1+ (R
f
/R
1
)] [(Va+V
b
+Vc)/3]
Averaging amplifier
Assume R and Rf
(Va+V
b
+Vc)/3
S.NO.
Input Voltage (v)
Vo(practical
in volts)
Vo(theoretical
in volts)
Va V
b
V
c
1
2
1
2
2
4
3
6
1.99
3.99
2
4
Differential configuration
Assume R, Vo= V
b
Va
Summing Amplifier
Vo= - Va-V
b
+V
c
+V
d
S.NO.
Input Voltage (v)
Vo(practical
in volts)
Vo(theoretical
in volts)
Va V
b
V
c
V
d
1
2
1
2
2
1
3
4
4
8
3.85
8.88
4
9
Subtractor amplifier
Assume R, Vo= V
b
V
a
S.NO.
Input Voltage(v)
Vo(practical
in volts)
Vo(theoretical
in volts)
Va Vb
1
2
1
4
2
1
1
2.98
1
3
Engineering Page 7
Voltage follower
R
O
=0, V
o
= V
i
=V
a
S.NO. Input Voltage(v) Output voltage (Vo)
1
2
4
3
4
3
PROCEDURE:
1. The circuits are connected as per circuit diagram.
2. By varying the inputs we note the output in the tabular form.
3. The practical values should match with theoretical values.
OBSERVATIONS:
1. The various outputs for varying inputs are noted.
2. Loose and wrong connections are avoided.
3. Readings are taken without errors.
RESULT: The summing scaling and averaging amplifiers are realized in inverting mode
and non inverting mode summer and differential mode of subtractor and also a voltage
follower is realized.
Engineering Page 8
COMPARATORS AND SCHMITT TRIGGERS
Experiment No: 1-B
AIM:
To realize the operation of inverting comparator, noninverting comparator, zero
crossing detector and Schmitt trigger using IC-741 and IC-555 Timer.
APPARATUS:
S.NO. Item name Specification Quantity
1 Op-amp IC -741 1
2 Timer IC-555 1
3 Regulated power supply (0-30)V 1
4 Function Generator (0-1)MHz 1
5 Resistors
10K, 100K 2(each)
1 K,100 2(each)
6
C.R.O 30MHz
7 Capacitor 0.01F, 0.1F 1(each)
8 Bread board - 1
THEORY:
A comparator, as its name implies, compares a signal voltage on one input of an
op-amp with a known voltage called the reference voltage on the other input. In its simplest
form, it is nothing more than an open-loop op-amp, with two analog inputs and a digital
output. The output may be positive or negative saturation voltage, depending on which
input is the larger. Comparators are used in circuits such as digital interfacing. Schmitt
triggers, discriminators, voltage-level detectors, and Oscillators.
NON-INVERTING COMPARATOR:
In this comparator, the input voltage is applied to the non-inverting terminal
and no reference voltage is applied to other terminal. So inverting terminal is grounded.
The input voltage is denoted as Vin while the voltage applied to other terminal with which
Vin is compared is denoted as Vref. In the basic comparator, Vref=0V. The output
voltage is at Vsat for Vin less than Vref and Vo goes to +Vsat for Vin >Vref. The output
waveform for a sinusoidal input signal applied to positive input terminal is shown in figure
for both positive and negative Vref respectively.
INVERING COMPARATOR:
In an inverting comparator the reference voltage is applied to the positive input and
Vin is applied to the negative.
Engineering Page 9
The output voltage is at +Vsat for Vi>Vref and Vo goes to Vsat for Vi<Vref
which is shown in the figure.
ZEROCROSSING DETECTOR:
An immediate application of the comparator is the zero crossing detector or sine
wave to square wave convertor. The basic comparator can be used as zero crossing detector
provided that Vref is set to 0V(Vref=0V). In the output waveform the output voltage Vo is
driven into negative saturation. When the input signal Vin passes through zero in the
positive direction conventionally when Vin passes the zero in the negative direction the
output Vo switches and saturate positively.
SCHMITT TRIGGER:
An inverting comparator with positive feedback converts an irregular shaped
waveform to a square wave or pulse. The circuit is known as Schmitt trigger or squaring
circuit. The input voltage is applied to the negative input terminal and feedback voltage to
the positive input terminal.
The input voltage V
T
trigger the output Vo every time it exceeds certain voltage
levels are called upper threshold voltage(V
UT
)and lower threshold voltage (V
LT
) and the
hystersis width is the difference between these two threshold voltages i.e. V
UT
-V
LT
.
Suppose the output voltage Vo = +Vsat.The voltage at positive input terminal will be

2
1 2
( )
UT ref sat ref
R
V V V V
R R
+
+
For Vo = -Vsat the voltage at the positive input terminal is
2
1 2
( )
LT ref sat ref
R
V V V V
R R
+
+
The hystersis width V
H
can be written as
2
1 2
2
sat
H UT LT
R V
V V V
R R

+
Engineering Page 10
CIRCUIT DIAGRAM:
SCHIMITT TRIGGER:
SCHMITT TRIGGER CIRCUIT Using IC-741
Engineering Page 11

ZERO CROSSING DETECTORS:
Engineering Page 12
Engineering Page 13
MODEL WAVE FORM FOR SCHMITT TRIGGER:
V
P

2
3
cc
V
-
2
3
cc
V

+V
sat
- V
sat
MODEL WAVE FORM FOR ZERO CROSSING DETECTORS:
+ V
P

T

-
V
P
+V
SAT
T
-V
SAT

Engineering Page 14
PROCEDURE:
FOR COMPARATOR:
1. The circuits are connected as per the circuit diagram
2. A sine wave input signal is applied at pin 3 for non-inverting and pin2 for
inverting terminal of an op-amp.
3. Positive and negative reference voltages are given to the pin 2 for inverting and
pin3 for non-inverting of an op-amp.
4. Observe the output waveform for zero crossing detector, inverting and non-
inverting comparators and note down the waveforms.
FOR SCHMITT TRIGGER:
1. Connections are made as per the circuit diagram.
2 A sine wave input signal is applied at pin2 for both ICs .
3. Observe the output waveforms for IC-741 at pin6 and for IC-555 at pin3.

CALCULATIONS:
For Schmitt trigger circuit:
Upper Threshold voltage

2
1 2
1 2
10 , 100 , 14
100
14 0.138
10 100
UT sat sat
sat
UT
R
V V V
R R
R K R V V
V V
K

+

+
Lower Threshold voltage
2
1 2
1 2
10 , 100 , 14
100
14 0.138
10 100
LT sat sat
sat
LT
R
V V V
R R
R K R V V
V V
K

+

+
Hystersis voltage
0.138 ( 0.138) 0.276
Hy UT LT
V V V V
Engineering Page 15
MODELGRAPH: The input and output waveforms are plotted in between voltage on Y-
axis and time on X-axis for both comparator and Schmitt trigger circuits.
PRECAUTIONS:
1. Loose connections are avoided in the circuit.
2. All power supplies are kept in minimum position before the starting of the
experiment
3. Positive and negative supplies should be given to the correct pins of IC-741.
RESULT:
The operations of inverting comparator, non-inverting comparator, zero crossing
detector and Schmitt Trigger circuits are realized using IC-741 and IC-555 Timer and the
output waveforms are observed.
Engineering Page 16
LOW PASS AND HIGH PASS FILTERS
Experiment No: 2
AIM:
1. To Design a first order low pass filter with a cutoff frequency of 200 Hz and a pass
band signal gain of 2 and hence its characteristics curves are to be plotted.
2. To Design a first order high pass filter with a cut off frequency of 1KHz and a pass
band gain of 2 and hence its characteristic curve are to be plotted.
APPARATUS:
1 Op-amp IC =741 1
3 CRO 30MHz 1
4 Function Generator (0-1)MHz 1
5 Resistors
10K 2
79.5 K 1
6
Potentiometer
15.9 K 1
7 Capacitor 0.01F 2
8 Bread board - 1
THEORY:
LOW PASS FILTER: A low pass filter has a constant gain from 0Hz to a high cut-off
frequency f
H
. Therefore, the bandwidth is also, at the gain is down by 3dB after that it
decreases with the increase in input frequency. The frequencies between 0Hz and f
H
are
known as the pass band frequencies, where as the range of frequencies, those beyond f
H
that are called as the stop band frequencies.
The filter consists of a single RC network connected to the positive input terminal
of a non-inverting op-amp amplifier as shown in fig (a). resistors R
i
and R
f
determine the
gain of the filter in pass band. The gain of the filter as a function of frequency is given by
0/ /1 ( / )
F H
V Vin A j f f +

Where A
F
= 1+ R
F
/R
1
= Pass band gain of the filter
f = Frequency of the input signal.
f
H
= 1/2RC = Higher cutoff frequency of the filter.
The gain magnitude and phase angle equations of the low pass filter
HIGH PASS FILTER: High pass filters are formed by simply interchanging frequency
determing resistors and capacitors in low pass filter. It has the lower cut-off frequency f
L
.
This is the frequency at which the magnitude of the gain is 0.707 times its pass band value.
Engineering Page 17
The frequencies higher than f
L
are pass band frequencies, bandwidth of the op-amp the
frequency response is
0
( )
1
L
A
H T
f
J
f

_
+

,
where
1
2
L
f
RC
, f = frequency of input
( )
0 0
2
1 /
i
L
V A
V
f f
+
Engineering Page 18
CIRCUITS:
Engineering Page 19
GRAPHS: The graphs are plotted for 20 log
0
i
V
V
as input signal frequency on a semilog
graphs and also the 3dB frequency is calculated for both high pass as well as low pass
filter.
PROCEDURE:
1. Connections are made as per circuit diagram.
2. An input signal V
i
of 1V(p-p) is given to Non- inverting terminal of the Op-amp
and output voltage for different input frequencies are noted.
3. The frequency response of 20 log
0
i
V
V
versus input signal frequency is plotted and
the 3dB frequency is calculated from here.
Engineering Page 20
4. The theoretical values of upper cut-off frequency f
H
and the pass band gain A
0
are
calculated
( )
1 1
1
,
2
H
f R R C C
RC

0
1
20log 1
f
R
A
R
_
+

,
HIGH PASS FILTERS:
5. The resistor R is interchanged with capacitor C to make high pass filter and steps 2
and 3 are repeated.
6. The theoretical values of lower cut-off frequency f
L
and pass band gain A
0
using
formula.
TABULAR FORMS:
Low pass filter:
Vi= 1V
S.NO. Frequency (Hz) Output voltage Vo (v) Gain =20log
10
Vo/Vi (db)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
20
40
60
80
100
150
200
250
300
400
500
1K
2K
3K
5K
10K
2
2
2
1.9
1.8
1.6
1.4
1.3
1.2
1
0.8
0.38
0.26
0.14
0.09
0.04
6.02
6.02
6.02
5.57
5.10
4.08
2.92
2.27
1.58
0
-1.938
-8.40
-11.7
-17.0
-20.9
-27.95
High pass filter:
Vi= 1V
S.NO. Frequency(Hz) Output voltage Vo (v) Gain =20log
10
Vo/Vi (db)
1
2
3
4
5
500
550
650
750
850
0.9
1
1.1
1.2
1.3
-0.9151
0
0.83
1.58
2.27
Engineering Page 21
6
7
8
9
10
11
12
13
14
950
1K
2K
3K
10k
15K
20K
40K
50K
1.4
1.5
1.6
1.8
1.9
1.9
1.9
1.9
1.9
2.92
3.52
4.08
5.1
5.5
5.5
5.5
5.5
5.5
PRECAUTIONS:
1. Loose and wrong connections are to be avoided.
2. The values are observed without any parallax errors.
RESULT:
1. A. first order low pass filter with a cut-off frequency of 200Hz and a pass band gain
of 2 is to design and its characteristics are plotted.
2. A first order high pass filter with a cut-off frequency of 1KHz and a pass band gain
of 2 is designed and hence its characteristics are plotted.
Engineering Page 22
FUNCTION GENERATOR USING 741 IC
Experiment No: 3
AIM: To generate a sine wave, square wave and triangular wave using 741 op-amp.
APPARATUS:
S.NO. Equipment Range Quantity
1 Operational amplifier 741 IC 2
3 CRO -
4 Resistors
330 1
100K 3
10 K pot/1k pot 1
1 K 2
47k 2
5 Capacitors
0.01F 2
1 F 1
6 Bread board - 1
THEORY:
IC 741 consists of 8 pins.
Pin 1 is offset null.
Pin 2 is given inverting input (-).
Pin 3 is given non inverting input (+)
Pin 4 is given V
CC
supply.
Pin 5 is offset null.
Pin 6 is given the output terminal.
Pin 7 is given + V
CC
supply.
No connection is given to Pin 8.
A 741 IC can be used as a sine wave generator.
Theoretical frequency of sine wave is calculated using,
1
1 1
2 2
f
RC RC
_

,
Q
and time period = T =
1
1
f
A 741 IC can be used as a square wave generator.
Theoretical frequency of square wave generated is calculated using,
time period = T = 2 RC ln
2 1
1
2R R
R
_ +

,
Engineering Page 23
and frequency = f =
1
T
A 741 IC can be used as a triangular wave generator. From the 1
st
part i.e., Astable
Multivibrator part of circuit a square wave is generated and given to 2
nd
part i.e., integrator
of the circuit.
Q
The 1
st
part of the circuit generates a square wave, the triangular wave generated by
2
nd
part, should also have the same frequency as the square wave.
DESIGN:
I. Sine wave generator (or) wein bridge oscillator is to be designed for a frequency
15.9KHz
1. Assume C=0.01f.
2. Calculate R by using formula f =
3. We know the condition for wein bridge oscillator R
F
= 2R
1
(Because A
v
= 1/ =
3,
Hence 1 + = 3)
4. Assume R
1
= 330 . Hence calculate R
F
.
II. Design a square wave generator with a frequency f
o
= 455Hz.
1. Assume C = 0.01 F and calculate R by using formula f
0
= 1/ 2RC
2. For obtaining a symmetrical square wave use R
2
= 1.16 R
1
. choose R
1
= 10K.
Calculate R
2
.
Engineering Page 24
CIRCUIT:
Engineering Page 25
Engineering Page 26
PROCEDURE:
1. Connections are made as per the circuit diagram with the designed values.
2. The o/p wave form is observed at pin 6 by adjusting the R
F
(i.e., pot) to the design
value.
3. The frequency and amplitude of the o/p waveform is measured.
4. Practical values which are obtained from the waveforms should match the
theoretical value.
5. Waveforms are plotted on a graph paper from the CRO.
PRECAUTIONS:
1. loose connections are avoided.
2. All power supplies are kept in minimum position before we start the experiment.
CALCULATIONS:
for sin wave generator theoretical frequency
fo = 1 / 2*pi*RC.
For square wave generator
T = 2RC log(2R
2
+R
1
/R
1
)
OBSERVATION:
The output waveforms observed on CRO are plotted by taking voltage on y axis
and time period on x axis.
RESULT:
Engineering Page 27
IC 555 Timer Astable Multivibrator
Experiment No: 4-A
AIM: To construct and observe the waveforms of Astable multivibrator (Square waveform
generator) using 555 timer.
APPARATUS:
S.NO. Equipment Range Quantity
1 CRO 1
2 Regulated Power Supply 1
3 555 IC 1
4 Capacitors
0.1F,
1
0.01F
1
5 Resistors 2.2 K, 3.9 K
CIRCUIT:
Engineering Page 28
DESIGN ASPECTS:
Design an Astable multivibrator with a frequency f=1.44 KHz & duty cycle = 60%
1. f = 1.44 KHz, D = 60% = 0.60
2. For Astable multivibrator
( )
1.45
2
A B
f
R R C
+
----------- (1)
and Duty Cycle D =
2
B
A B
R
R R +
----------- (2)
3. Assume C = 0.1F.
4. Calculate values of R
A
and R
B
by substituting C in equation (1) and solve
equation(2) R
A
& R
B
values.
OR
1. T = 0.69 (R
A
+ 2R
B
).C,
2. Duty cycle =
ON
ON OFF
T
T T +
where T
ON
= 0.69 (R
A
+ R
B
)c
and T
OFF
= 0.69 R
B
. C
3. Assume C = 0.1 F and solve for R
A
and R
B
MODEL WAVE FORMS:
Engineering Page 29
Engineering Page 30
PROCEDURE:
1. Connections are to be made as per the designed values.
2. The o/p waveforms to be observed at pin 3 and sketch the same.
3. The capacitor voltage waveform is to be observed at pin 6 and sketch the same.
4. The frequency and duty cycle of the obtained output waveform is measured.
5. The obtained practical values of frequency are compared with the theoretical
values.
PRECAUTIONS:
2. All power supplies are kept in minimum position before the state of the experiment
3. The time periods of the output waveforms are noted down properly.
RESULTS:
Engineering Page 31
IC 555 Timer Monostable Multivibrator
Experiment No: 4-B
AIM: To construct and observe the waveform of a monostable multivibrator using 555
timer.
APPARATUS:
S.NO. Equipment Range
1 Resistors 3.9 K
2 Capacitor 0.1F, 0.01F
3 Function generator
4 CRO
CIRCUIT:
Engineering Page 32
DESIGN:
Design a monostable multivibrator to get a pulse width of 0.42 m sec.
Assume R
A
= 3.9 K.
t
p
= 1.1. R
A
.C
where t
p
= pulse width.

0.42 sec 1.1 3.9
0.42 sec
0.1
1.1 3.9
m K C
m
C F
K

Engineering Page 33
PROCEDURE:
1. Connections are to be made as per the circuit diagram.
2. Trigger i/p is to be given at pin 2 using function generator satisfying the below
condition.
Condition: The pulse width of the trigger input must be smaller than the expected
pulse width of the output waveform. Also the trigger pulse must be a
negative going input signal with an amplitude is larger than (1/3)V
CC
.
3. O/P waveform at pin 3 is observed and sketches the waveform.
4. The capacitor waveform is observed at pin 6
5. The obtained values of t
p
are compared theoretically and practically.
PRECAUTIONS:
2. All power supplies are kept in minimum position before the starting of the
experiment
3. The time periods of the output waveforms are noted down properly.
RESULTS: Monostable multivibrator is constructed using IC-555 and pulse width of
Monostable multivibrator is (0.42 msec) verified
Engineering Page 34
723
723 VOLTAGE REGULATOR
Experiment No: 5
Aim: To study the operation and to plot the load regulation characteristics of the 723
voltage regulator IC
Apparatus:
1 Op-amp IC =723 1
2 Un Regulated power supply (0 30)V 1
3
Millimeter Voltmeter and
Ammeter
2
5 Resistors
10K,2.2K,1K 3
680 ,100 2
6
Potentiometer
10 K 1
7 Capacitor 100pf 1
8 Bread board - 1
Theory:
The three terminal regulators discussed earlier have the following limitations:
1. No short circuit protection
2. Output voltage (
+
V or
-
V) is fixed
These limitations have been overcome in the 723 general-purpose
regulator, which can be adjusted over a wide range of both positive and
negative regulated voltage. This IC is inherently low current device but can be
boosted to provide 5 amps or more current by connecting external
components. The limitations of 723 are that it has no in-built protection. It
also has no short circuit current limits.

Important features:
1. Input voltage 40V maximum.
2. Output voltage adjustable from 2V to 37V.
3. 150mA output current without external pass transistor
4. Output currents in excess of 10 A possible by adding external
transistors.
Engineering Page 35
723
5. It can be used as either a linear or a switching regulator.
IT IS USED FOR :
Current limit protection
Current fold back
Current Boosting
Switching regulator.
IC-723 PIN DIAGRAM:
NC 1 14 NC
Current limit 2 13 Frequency component
Current Source3 12 V
+
Inverting i/p 4 11 Vi
5 10 V
out
V
ref
6 9 V
2
V
- 7 8 NC
CIRCUIT DIAGRAM:
Engineering Page 36
723
PROCEDURE:

1. Connections are made as the circuit diagram.
2. Set the DC power supply voltage V
in
to +10 V.
3. With R
L
removed from the circuit (open circuit). Measure the maximum and
minimum output voltages by rotating 1 K pot through its full range
4. Now adjust the 1 K pot. So that Vo is +5 V. Measure the voltage between wiper
arm of 1 K pot and ground as V
ref
.
5. Adjust the load R
L
(10K) until the load current I
L
=1mA. Record V
L
. Repeat for
different values of load currents: 2,3,4,5,6,6.85 mA also measure R
L
for all these
values and tabulated them in the tabular form.
6. Short the load and measure V
NL
at the output and also calculate % of regulation.
OBSERVATIONS:
1. Maximum and Minimum output voltages at no load are
V
max
= 6.59 V. V
min
=1.19 V.
2. V
ref
=6.60 V

3. No load voltage V
NL
= 5.01 V
Engineering Page 37
TABULAR FORM:
S.No I
L
(mA) V
L
(V) R
L
(K) % of Reg
( )
100
NL FL
FL
V V
V

1
2
3
4
5
6
7
8
1
2
3
4
5
5.5
6.5
6.85
5.01
5.01
5.01
5.01
5.01
5.00
5.00
0.52
5
2.50
1.01
1.25
0.95
0.90
0.84
0.07
0
0
0
0
0
0.2
0.2
863.46
CALCULATIONS:
% of load regulation =
100
NL FL
FL
V V
V
Where V
NL
=No load voltage
V
FL
= Full load voltage.
GRAPHS:
1. A graph is plotted with a regulation along Y-axis and load resistance R
L
on X-
axis is shown in figure.
2. A graph is plotted with I
L
along X- axis and V
L
along Y-axis which is shown in
figure.
% of Reg V
L
R
L
() I
L
Engineering Page 38
PRECAUTIONS:
1. Loose connections should be avoided.
2. All power supplies should be kept at minimum position before starting
the Experiment.
RESULT:
The operation of IC-723 regulator is studied and the regulation characteristics are
also plotted.
Engineering Page 39
DIGITAL TO ANOLOG CONVERTER
Experiment No: 6
AIM: study of digital to analog converter using R-2R ladder network method.
APPARATUS:
OP-AMP 741 IC
Multimeter
Regulated Power Supply
Resistors
Bread board
Potentiometer
THEORY:
Wide range of resistors is required in binary weighted resistor type DAC. This can
be avoided by using R-2R ladder type DAC, where only two values of resistors are
required. It is well suited for integrated circuit realization. The typical value of R ranges
from 2.5kohm to 10kohm.
For simplicity, consider a 3 bit DAC where the switch position d1,d2,d3
corresponds to binary word 100.
The circuit can be simplified to equivalent. Then voltage at node c con be easily
calculated by the set procedure of network analysis as
-[VR(2/3)*R] / [2R+(2/3)*R]=-VR/4
The output voltage
Vo = -2R/R (-VR/4)=VR/2 = VFS/2
The switch position corresponding to the binary word 001 in 3 bit DAC. The circuit
can be simplified to the equivalent from the voltages at the nodes A, B, C formed by the
resistor branches are calculated easily in a similar fashion and the output voltage becomes
In a similar fashion, the output voltage for R-2R ladder type DAC corresponding
tho other 3 bit binary words can be calculated. In R-2R ladder type DAC, current flowing
in the resistor changes as the input data changes. More power dissipation causes heating,
which in turn creates non-linearity in DAC.
Vo= (-2R/R)(-VR/16)=VR/8=VFS/8.
Engineering Page 40
CIRCUIT:
OBSERVATIONS:
S.No. D1 D2 D3
Theoretically
(Vo)
Practically
(Vo)
1.
2.
3.
4.
5.
6.
7.
8.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0.62
1.24
1.86
2.49
3.11
3.74
4.86
0
0.637
1.276
2.0
2.54
3.22
3.90
4.58
PROCEDURE:
1. Connect the circuit as shown in figure.
2. Measure output voltage for all binary inputs (000 to 111) states and plot a graph of
binary input vs. output voltage.
3. Compare theoretical and practical values.
RESULT: Hence the study of D to A converter using R-2R ladder network method has
been done.
Engineering Page 41
+VC
C
+15V
-VCC
-15V
LSB
MS
D FLIP FLOP
Experiment No: 1
TITLE OF THE EXPERIMENT: D FLIP FLOP
AIM: Simulation and Verification of D FLIP FLOP.
SOFTWARE USED: XILINX software (Modelsim Simulator and Xilinx Synthesis Tool
(XST)-Synthesis).
DESCRIPTION:
The commonly desired function in D-flipflop is the ability to hold the last
value stored, rather than load a new value, at the clock edge. This is accomplished by
adding an enable input, called EN or CE(clock enable). While the name clock enable is
Descriptive, the extra inputs function is not obtained by controlling the clock. A 2-input
multiplexer controls the value applied to the internal flipflop;s D input.
7474 IC D FLIP FLOP:
LOGIC DIAGRAM:
Engineering Page 42
TRUTH TABLE:
VHDL CODE FOR D FLIP FLOP IN BEHAVIORAL:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dff is
Port ( d,res,clk : in STD_LOGIC;
q : out STD_LOGIC);
end dff;
architecture Behavioral of dff is
begin
process(clk)
begin
if (res ='1')then q<='0';
elsif clk'event and clk='1'
then q<=d;
end if;
end process;
Engineering Page 43
end Behavioral;
VHDL CODE FOR D FLIP FLOP IN STRUCTURAL:
library IEEE;
entity dff1 is
Port ( d,clk,pr,clr : in STD_LOGIC;
q,qn : inout STD_LOGIC);
end dff1;
architecture struct of dff1 is
component clkdiv is ---components, entity and architecture
port(clk:in std_logic;clk_d:out std_logic); ---must be declared separately
end component;
component nand1 is
port(a,b,c:in std_logic; ---components, entity and architecture
d:out std_logic); ---must be declared separately
end component;
component nand12 is
port(x,y:in std_logic; ---components, entity and architecture
z:out std_logic); ---must be declared separately
end component;
component nand13 is
port(e:in std_logic; ---components, entity and architecture
f:out std_logic); ---must be declared separately
end component;
signal s1,s2,s3,s4,s5,s6,s7,s8,s9:std_logic;
begin
u10:clkdiv port map(clk,s7);
u1:nand1 port map(d,s7,qn,s1);
u2:nand1 port map(s9,s7,q,s2);
u3:nand1 port map(pr,s1,s4,s3);
u4:nand1 port map(s2,clr,s3,s4);
u5:nand12 port map(s3,s8,s5);
u6:nand12 port map(s8,s4,s6);
u7:nand12 port map(s5,qn,q);
u8:nand12 port map(s6,q,qn);
u9:nand13 port map(s7,s8);
Engineering Page 44
u11:nand13 port map(d,s9);
end struct;
Engineering Page 45
WAVEFORMS/TIMING DIAGRAMS:
RESULT:
Simulation and Verification of D FLIP FLOP is done and wave forms are
Engineering Page 46
Engineering Page 47
DECADE COUNTER 7490
Experiment No: 2
TITLE OF THE EXPERIMENT: Decade Counter 7490.
AIM: To Design and simulate Decade Counter 7490.
SOFTWARE USED: XILINX Software (Modelsim Simulator and Xilinx Synthesis
Tool (XST) Synthesis).
LOGIC DIAGRAM:
Engineering Page 48
TRUTH TABLE:

VHDL CODE FOR DECADE COUNTER IN BEHAVIORAL :
library IEEE;
entity dec_counter is
Port ( clock,reset,en : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (3 downto 0));
end dec_counter;
architecture Behavioral of dec_counter is
signal count : std_logic_vector(3 downto 0);
begin
process(clock,reset)
begin
if(reset='1') then count<="0000";
elsif(clock' event and clock='1') then
if en='1' then
count<=count+1;
else
count<=count;
end if;
if count="1001" then
count<="0000";
end if;
end if;
Engineering Page 49
end process;
q<=count;
end behavioral;

RESULT:
Simulation and Verification of Decade Counter is done and wave forms are
obtained.
Engineering Page 50
SERIAL-IN, PARALLEL-OUT SHIFT REGISTER
Experiment No: 3
TITLE OF THE EXPERIMENT: Serial-in, Parallel-out Shift Register.

AIM: To Design an N-Bit Registers performing Serial-in, Parallel-out Shift Register.
LOGIC DIAGRAM:
TRUTH TABLE:

VHDL CODE FOR SHIFT REGISTER IN BEHAVIORAL:
library IEEE;
entity sipo is
generic(3: NATURAL:=8);
Port ( a : in std_logic;
clock : in std_logic;
q : out std_logic_vector(3 to 0));
end sipo;
Engineering Page 51
architecture behavioral of sipo is
begin
p0:process(clock) is
variable reg: STD_LOGIC_VECTOR(3 downto 0);
begin
if rising_edge(clock) then
reg:= reg(2 downto 0) & a;
q<= reg;
end if;
end process p0;
end architecture behavioral;
RESULT:
Simulation and Verification of Serial-in, Parallel-out Shift Register is done and
wave forms are obtained.
Engineering Page 52
Universal Shift Register - 74194
TITLE OF THE EXPERIMENT: Universal Shift Register 74194.
AIM: simulation and verification of Universal Shift Register 74194.
LOGIC DIAGRAM:
TRUTH TABLE:

INPUT
FUNCTION
NEXT STATE
S1 S0 Q(3) Q(2) Q(1) Q(0)
0 0
0 1
1 0
1 1
HOLD
SHIFT RIGHT
SHIFT LEFT
LOAD
Q(3) Q(2) Q(1) Q(0)
Rin Q(3) Q(2) Q(1)
Q(2) Q(1) Q(0) Lin
D3 D2 D1 D0
VHDL CODE FOR UNIVERSAL SHIFT REGISTERS INBEHAVIORAL:
library IEEE;
entity shiftreg is
Engineering Page 53
port(clk,clr,lin,rin:in std_logic;
s:in std_logic_vector(1 downto 0);
d:in std_logic_vector(3 downto 0);
q:inout std_logic_vector(3 downto 0));
end siftreg;
architecture Behavioral of shiftreg is
begin
process(clk,clr,lin,rin,s,d)
begin
if(clr = 0)then q<=0000;
elsif(clkevent and clk=1)then
if(s=00)then q<=q;
elsif(s=01)then q<=rin & q(3 downto 1);
elsif(s=10)then q<=q(2 downto 0) & lin;
elsif(s=11)then q<=d;
end if;
end if;
end process;
end Behavioral;
WAVEFORMS/TIMINGDIAGRAMS:
RESULT:
Engineering Page 54
Simulation and Verification of Universal Shift Register is done and wave forms
are obtained.
Engineering Page 55
3 TO 8 DECODER
Experiment No: 4
TITLE OF THE EXPERIMENT: 3-8 Decoder 74138.
AIM: Simulation and verification of 3-8 Decoder 74138.
DESCRIPTION:
A Decoder is a multiple-input, multiple-output logic circuit which
converts coded inputs into coded outputs, where the input and output codes are different.
The input code generally has fewer bits than the output code. Each input code word
produces a different output code word, i.e.,there is one-to-one mapping from input code
words into output code words. A 3 to 8 Decoder is consist of 3-inputs that are decoded into
eight outputs, each output represent one of the minterms of the 3-input variables. Enable
input is provided to activate decoded output based on data input is provided to activate
decoded output based on data inputs A,B and C.
74x138 IC DIAGRAM:
TRUTH TABLE:
Engineering Page 56
VHDL CODE FOR 3:8 DECODER IN BEHAVIORAL:
library IEEE;
entity dec1 is
Port ( s : in STD_LOGIC_VECTOR (2 downto 0);
y : out STD_LOGIC_VECTOR (7 downto 0));
end dec1;
architecture Behavioral of dec1 is
begin
with sel select
y<="00000001" when "000",
"00000010" when "001",
"00000100" when "010",
"00001000" when "011",
"00010000" when "100",
"00100000" when "101",
"01000000" when "110",
"10000000" when "111",
"00000000" when others;
end Behavioral;
Engineering Page 57
RESULT:
Simulation and Verification of 3-8 Decoder is done and wave forms are
obtained.
Engineering Page 58
4 BIT COMPARATOR 7485
Experiment No: 5
TITLE OF THE EXPERIMENT: 4 Bit Comparator 7485.
AIM: To simulate and synthesize 4 Bit Comparator 7485.
DESCRIPTION:
A Comparator is a special combinational circuit designed primarily to
compare the relative magnitude of two binary numbers. For a comparator two n-bit
numbers A and B as inputs and the outputs are A>B , A=B , A<B.Depending upon the
relative magnitude of the two numbers, one of the outputs will be high.
IC 7485 is used as a comparator. It can be used to compare 4-bit binary
words. These ICs can be cascaded to compare words of almost any length. Its 4-bits inputs
are weighted (A0-A3) and (B0-B3), where A3 and B3 are the most significant bits. The
operation of the is can be described by the below Truth Table.
74X85 IC PIN DIAGRAM:
Engineering Page 59
TRUTH TABLE:
INPUTS OUTPUTS
AeqBin AgtBin AltBin Condition AeqB AgtB
AltB
0 0 1 Any Case 0 0
1
0 1 0 Any Case 0 1 0
1 0 0 A=B 1 0
0
1 0 0 A>B 0 1 0
1 0 0 A<B 0 0 1
0 0 0 A=B 1 0 0
0 0 0 A>B 0 1 0
0 0 0 A<B 0 0 1
VHDL CODE FOR 4 BIT COMPARATOR IN BEHAVIORAL:
library IEEE;
entity fbc is
port(a,b: in std_logic_vector(3 downto 0);
aeqbin,agtbin,altbin: in std_logic;
aeqb,altb,agtb: out std_logic);
end fbc;
architecture behavioral of fbc is
begin
process(a,b,aeqbin,agtbin,altbin)
begin
if(a=b and aeqbin='1' and agtbin ='0' and altbin ='0')
then aeqb<='1';
else aeqb<='0';
end if;
if((a>b and aeqbin='1') or agtbin ='1')
then agtb<='1';
else agtb<='0';
end if;
Engineering Page 60
if((a<b and aeqbin='1') or altbin ='1')
then altb<='1';
else altb<='0';
end if;
end process;
end behavioral;
RESULT:
Simulation and Verification of 4-BIT Comparator is done and wave forms are
obtained.
Engineering Page 61
8 1 MULTIPLEXER 74151
Experiment No: 6 - A
TITLE OF THE EXPERIMENT: 8X1 Multiplexer 74151.
AIM: Simulation and verification of 8X1 multiplexer.
SOFTWARE USED: XILINX Software (Modelsim Simulator and Xilinx
Synthesis Tool (XST) Synthesis).
DESCRIPTION:
Multiplexer is a digital switch. It allows digital information from several sources to
be routed onto a single output line. The basic multiplexer has several data-input lines and a
single output line. The selection of a particular input line is controlled by a set of selection
lines. The 74XX151 is a 8 to 1 multiplexer, it has eight inputs. It provides two outputs, one
is active high, the other is active low. The relation between inputs and outputs is may
derived from the Truth Table below.
74X151 IC DIAGRAM:
Engineering Page 62
TRUTH TABLE:
VHDL CODE FOR MULTIPLEXER (8:1) IN BEHAVIORAL:
library IEEE;
entity mux1 is
Port ( d : in STD_LOGIC_VECTOR (7 downto 0);
s : in STD_LOGIC_VECTOR (2 downto 0);
f : out STD_LOGIC);
end mux1;
architecture Behavioral of mux1 is
begin
f<= d(0) when s="000" else
d(1) when s="001" else
Engineering Page 63
d(7) when s="111";
end Behavioral;
RESULT:
Simulation and Verification of 8X1 Multiplexer is done and wave forms are
obtained.
Engineering Page 64
2 TO 4 DEMULTIPLEXER
Experiment No: 6 - B
TITLE OF THE EXPERIMENT: 2X4 Demultiplexer.
AIM : To design a 2 to 4 Demultiplexer circuit using a VHDL software.
DESCRIPTION :
Demultiplexer is a digital switch. It allows digital information from a single
input line to several outputs. The basic demultiplexer has single data-input line and a
several output lines. The selection of a particular output line is controlled by a set of
selection lines. The 74XX155 is a 2 to 4 demultiplexer. The input code generally has fewer
bits than the output code. Each input code word produces a different output code word, i.e.,
there is one-to-one mapping from input code words into output code words. A 2 to 4
demultiplexer is consist of 2-inputs that are demultiplexed into four outputs, each output
represent one of the minterms of the 2-input variables.It has two inputs. It provides four
outputs, one is active high, the other is active low. The relation between inputs and outputs
is may derived from the below truth table.
LOGIC DIAGRAM:
Engineering Page 65
TRUTH TABLE:

Inputs Outputs
A B1 B0 Y3 Y2 Y1 Y0
0 X X 0 0 0 0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0
VHDL CODE FOR MULTIPLEXER (8:1) IN BEHAVIORAL:
library IEEE;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity demultiplexer2to4 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC_VECTOR (1 DOWNTO 0);
y : out STD_LOGIC_VECTOR (3 DOWNTO 0));
end demultiplexer2to4;
architecture Behavioral of demultiplexer2to4 is
begin
process (b)
begin
if b = "00" then y(0)<=a;
elsif b = "01" then y(1)<=a;
end if;

Engineering Page 66
end process;
end Behavioral;
RESULT: Hence the 2to4 Demultiplexer circuit is designed using VHDL
software and the output is also observed.
Engineering Page 67
RAM (16 4) 74189
Experiment No: 7
TITLE OF THE EXPERIMENT: 16 X 4 RAM 74189.
AIM: simulation and verification of 16 X 4 RAM 74189.
LOGIC DIAGRAM:
TECHNOLOGY SCHIMATIC :
Engineering Page 68
VHDL CODE 16 X 4 RAM IN BEHAVIORAL:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity SRAM is
generic( width: integer:=4;
depth: integer:=4;
addr: integer:=2);
port( Clock: in std_logic;
Enable: in std_logic;
Read: in std_logic;
Write: in std_logic;
Read_Addr: in std_logic_vector(1 downto 0);
Write_Addr: in std_logic_vector(1 downto 0);
Data_in: in std_logic_vector(3 downto 0);
Data_out: out std_logic_vector(3 downto 0));
end SRAM;
architecture behavioral of SRAM is
-- use array to define the bunch of internal temporary signals
type ram_type is array (0 to depth-1) of
std_logic_vector(width-1 downto 0);
signal tmp_ram: ram_type;
begin
Engineering Page 69

-- Read Functional Section
process(Clock, Read)
begin
if (Clock' event and Clock='1') then
if Enable='1' then
if Read='1' then
-- buildin function conv_integer change the type
-- from std_logic_vector to integer
Data_out <= tmp_ram(conv_integer(Read_Addr));
else
Data_out <= (Data_out'range => 'Z');
end if;
end if;
end if;
end process;
-- Write Functional Section
process(Clock, Write)
begin
if (Clock' event and Clock='1') then
if Enable='1' then
if Write='1' then
tmp_ram(conv_integer(Write_Addr)) <= Data_in;
end if;
end if;
end if;
end process;
end behavioral;
WAVEFORM/TIMING DIAGRAM:
Engineering Page 70
RESULT:
Simulation and Verification of 16 X 4 RAM is done and wave forms are
obtained.
Engineering Page 71

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since the input bias current is

, similarly, the output

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