SHAUNAK

JANI
101 E San Fernando St, Apt 428, San Jose, CA 95112, US. Tel: +1 (408) 859 4549. Email: shaunak.jani@students.sjsu.edu Website: shaunakjani.blogspot.com

OBJECTIVE
Seeking an internship opportunity in the field of ASIC / FPGA design, testing, and verification which offers me professionalgrowthandchallengeswhilefulfillingcorporateobjectivesofdeliveringasuccessfulproduct.

EDUCATION
MSElectricalEngineering(VLSIDesign)August2011May2013(Expected)GPA3.3 SanJoseStateUniversity B.E.ElectronicsandTelecommunicationsEngineeringAugust2006July2010 UniversityofMumbaiIndia

TECHNICALSKILLS
HandsonExperienceinRTLsynthesis,gatelevelsimulationaswellasSTA,usingvariousEDAtoolsets. ExpertisewithDigitalCircuitDesign,DebugandformalVerificationusingVerilogHDL. GoodbasicunderstandingofCMOStransistorcircuitdesignfundamentals. GoodinDesigning&Analyzingpower,performance,andareatradeoffsindigitalcircuits. WorkedonFloorplanningandplace&routeusingCadenceEncounter. GoodbasicunderstandingonASIC/ICdesignflowand,CMOSphysicaldesign. Abilitytolearnnewtechnologies,teamplayer,goalorientedandhighlymotivated Languages:VerilogHDL,C,C++,learningPerl. Tools:SynopsysVCS,SynopsysDesignVision,Modelsim,TurboC,PCBExpress,CadenceEncounter,NCverilog, IcarusVerilog. Microprocessors&Microcontrollers:8085,8086,8051and80196Microcontrollers Productivitysuite:MSOffice,AdobePhotoshop,Notepad++. OperatingSystem:WindowsXP/Vista/Seven,MacOS,Fedora,Unix.

PERTINENTCOURSES
DigitalSystemDesignusingVerilogHDL ASICCMOSDesign SemiconductorDevices Probabilities,RandomVariables&StochastiProcesses 8051microcontroller8085&8086 Microprocessors DigitalTimeSignalProcessing ComputerNetworking EngineeringDevicesandCircuit LinearSystemTheory

ACADEMICPROJECTS
>>DesignofTokenRinginterfaceforI2CBus(Ongoing) May2012(Expected) ImplementingTokenRinginterfaceforI2CBusworkingforvariousmodesofoperation. UsingconceptofFiniteStateMachine(FSM). ImplementingFIFO. >>Designtocalculatecirclecoordinates February2012 DesignedamultiplierandasquarerootcalculatorinordertocalculateYinthecircleequationY^2+X^2=R^2. Implementedasynchronousdesignusingtheconceptofpipeliningandflags. Optimizedthecircuittoworkat200MHzand300MHz. ExploredconceptsofTimingclosureSetupandHoldtimeviolation. ImplementedFIFO. PlaceandRouteusingEncounter.

ACADEMICPROJECTS(Continued)
>>DesignandAnalysisofAreaDelayandPowerDelayTradeoffsinAdditionCircuitsDecember2011 Designed adders using Verilog HDL at RTL level used simple ripplecarry algorithm and other used carrylooked aheadalgorithm. Performed testing and verification for 16, 32, 48and 64bit adders. Simulated the designs in Synopsys VCS and synthesizedandoptimizedusingToshibaLibraryinSynopsysDesignVision. Simulatednetlisttocheckforshortest,medium,andlongestdelaybypassingvariousdatainputsinthetestbench, andgeneratedthesummationandcarryoutputs. Performedpostsynthesisonthedesignusingnetlist. Optimizedthedesignlogicuntiltheresultsensuredthattheslackwasnotviolated. >>TouchscreenbasedElectronicVotingMachine May2010 Designed and implemented a novel touch screen based voting machine, as a proposal to improve the current electoralvotingmechanisminIndia.Projectandimplementationwaschosenasthe3rdbestideaamongstatotalof 30classprojects. Rectified the problems occurring in current voting mechanism by exploring modern hardware circuit design techniquesandimplementingefficientanduserfriendlysoftware. Enableddatasecurityandbackupofthevotesbybuildingafourdigitpasswordverificationandprotectionsystem. ImplementedPCinterfacewiththedeviceusingRS232toallowtimelydatabackups. ProgrammedthemicrocontrollerusingEmbeddedC.

ACHIEVEMENTS

Creative head of KJSIEIT student councils annual sports festival SCORE2KX and KJSIEITIETE student council 2009. Won2ndPriceatMVLUcollegeIntracollegiatequizcontestheldinAugust2004. Won3rdPriceatRoyalcollegeIntercollegiatesciencequizQUEST2004. MemberofchieforganizingcommitteeofKJSIEITstudentcouncilsandIEEEKJSIEITstudentchapter.