MC TE3001 Chapter 3 Architecture PIC18 1

TE3001 Microcontrollers
Chapter #3
PIC18F4585 Architecture
Dr. Rodolfo J. Castell Z.
4 16 bits-timers (T0 T3). 5 I/O ports (A, B, C, D, y E) . Serial port, parallel communication, and A/D converter of 10 bits and 11 channels.
PIC18 Clock Sources
Source: PIC18C Reference Manual, Microchip DS39500a, 2000 Dr. Rodolfo J. Castell Z. 4
PIC18 Clock Sources
Mode EC ECIO LP XT HS RC RCIO HS4
Description External Clock External Clock with I/O pin enabled Low Frequency (Power) Crystal Crystal/Resonator High Speed Crystal/Resonator External Resistor/Capacitor External Resistor/Capacitor with I/O pin enabled High Speed Crystal/Resonator with 4x fequency PLL multiplier enabled
PIC18 Clock Sources
Bit
0
Symbol
SCS
Reset value
0
Description
System Clock Switch bit: 1 = Timer1 Oscillator is the system clock 0 = Use External clock Unimplemented bits. Read as 0
17
Source: PIC18C Reference Manual, Microchip DS39500a, 2000
PIC18 Clock Sources
FOSC2:FOSC0 Configuration Bits 111 110 101 100 011 010 001 000
Oscillator Mode RCIO HS4 ECIO EC RC HS XT LP
PIC18F4585 Clock Sources
Source: PIC18F4585 Data Sheet, Microchip DS39625C, 2007 Dr. Rodolfo J. Castell Z. 8
Mode EC ECIO LP XT HS RC RCIO HSPLL INTIO1 INTIO2
Description External Clock External Clock with I/O pin enabled Low Frequency (Power) Crystal Crystal/Resonator High Speed Crystal/Resonator External Resistor/Capacitor with FOSC/4 output on RA6 External Resistor/Capacitor with I/O on RA6 High Speed Crystal/Resonator with PLL multiplier enabled Internal Oscillator with FOSC/4 output on RA6 and I/O on RA7 Internal Oscillator with I/O on RA6 and RA7
9
Source: PIC18F4585 Data Sheet, Microchip DS39625C, 2007 Dr. Rodolfo J. Castell Z.
Bit
0-1
Symbol
SCS1:SCS0
Reset value
00
Description
System Clock Select bits: 1x = Internal Oscillator Block 01 = Timer1 Oscillator 00 = Primary Oscillator specified by FOSC3:FOSC0 of CONFIG1H INTOSC Frequency Stable bit 1 = Stable. 0 = Not stable Oscillator Start-up time-out status bit Internal Oscillator Frequency Select Bits 111 = 8MHz 011 = 500KHz 110 = 4MHz 010 = 250KHz 101 = 2MHz 001 =125KHz 100 = 1MHz 000 = 31KHz Idle Enable Bit
2 3 6-4
IOFS OSTS IRCF2:IRCF0
0 0 100
IDLEN
Source: PIC18F4585 Data Sheet, Microchip DS39625C, 2007 Dr. Rodolfo J. Castell Z.
10
FOSC3:FOSC0 Configuration Bits 11xx 1001 1000 0111 0110 0101 0100
Oscillator Mode RC INTIO1 INTIO2 RCIO HSPLL EC ECIO
FOSC3:FOSC0 Configuration Bits 0001 0000
Oscillator Mode XT LP
Source: PIC18F4585 Data Sheet, Microchip DS39625C, 2007 11
2M Program Space
Programs Address Bus Datas Address Bus
4K (212= 4096)
Program Memory (Flash)
21 lines 16 lines
12 lines
Processor
8 lines
Data Memory (SFRs and GP RAM)
Instructions Bus
Data Bus
16 bits Opcode
12
12 Address PC 21 Program Memory (Flash) 16 12 IR 8 Instruction Decoder 8 8 FSRs 4 4 Address 12 Data Memory (SRAM) MPX
BSR Access Bank
31 Levels Stack
Internal Resources
I/O Ports 8 8 Timers EEPROM A/D Converter
Clock
ALU
8 STATUS
Serial Port Parallel Port
W (accumulator)
13
14
15
16
PIC18F4585 Program Memory

Code Memory
0000H 0008H 21 20 0018H 0 Level 1 Level 31 20 Reset Vector Address 21 20 PC 0
48 KB @ el PIC18F4585
BFFFH C000H
Internal Program Memory
Stack
2 MB
1FFFFFH 7 Dr. Rodolfo J. Castell Z. 0 17
SFRs to Control Program Memory

Data Bus <8>
8 8 8
Address Bus
PCLATU
PCLATH
<20 0>
20 16 15 8 7 0
31 Level Stack
18
19
20
10
Code Storage in Program Memory
Address 000000H 000001H 000002H 000003H 000004H 000005H 000006H 000007H
Contents
Instruction
Operand(s)
0x55 0x0F 0x23 0xC1 0x56 0x04
MOVLW MOVFF
0x55 0x123, 0x456
21
22
11
RAM Data Memory Map for the PIC 18 Family

Bank # 0 1 2 00H FFH 00H FFH 00H FFH GPRs 000H 07FH 080H 0FFH 100H 1FFH 200H 2FFH
See Data Sheet for each PIC
BSR <3 0>
" " " "

13 14 15 00H FFH 00H FFH 00H FFH
" " " "
" " " "

D00H DFFH E00H EFFH F00H F7FH
Access Bank GPRs SFRs
00H 7FH 80H FFH
SFRs
F80H FFFH 23
24
12
Bank Select Register (BSR)

Data Memory
7 0 0 0 0 1 1 0 0 0 0 1 2 3 4 Bank # 0 Bank # 1 Bank # 2 Bank # 3 Bank # 4 00H FFH 00H FFH 00H FFH 00H FFH 00H FFH 7 1 1 1 1 1 1 1 0 1
" " "

C D E F Bank # 12 Bank # 13 Bank # 14 Bank # 15 00H FFH 00H FFH 00H FFH 00H FFH
25
Bank Select Register (BSR)
The only instruction from PIC18 core instruction set that fully specifies by itself the 12-bit address of both, the source and target registers, is MOVFF.
26
13
Access Bank GPRs SFRs
00H 7FH 80H FFH
27
28
14
29
I/O Ports. Interruptions. Serial Port. Timers. A/D Converters. CPU Functionality.
30
15
Bank #15, PIC18 Basic SFRs Set

F80h F81h F82h F83h F84h F85h F86h F87h F88h F89h F8Ah F8Bh F8Ch F8Dh F8Eh F8Fh F90h F91h F92h F93h F94h F95h F96h F97h F98h F99h F9Ah F9Bh F9Ch F9Dh F9Eh F9Fh FA0h FA1h FA2h FA3h FA4h FA5h FA6h FA7h FA8h FA9h FAAh FABh FACh FADh FAEh FAFh FB0h FB1h FB2h FB3h FB4h FB5h FB6h FB7h FB8h FB9h FBAh FBBh FBCh FBDh FBEh FBFh PIE2 PIR2 IPR2 FC0h FC1h FC2h FC3h FC4h FC5h FC6h FC7h FC8h FC9h FCAh FCBh FCCh FCDh FCEh FCFh FD0h FD1h FD2h FD3h FD4h FD5h FD6h FD7h FD8h FD9h FDAh FDBh FDCh FDDh FDEh FDFh ADCON1 ADCON0 ADRESL ADRESH SSPCON2 SSPCON1 SSPSTAT SSPADD SSPBUF T2CON PR2 TMR2 T1CON TMR1L TMR1H RCON WDTCON LVDCON OSCCON T0CON TMR0L TMR0H FE0h FE1h FE2h FE3h FE4h FE5h FE6h FE7h FE8h FE9h FEAh FEBh FECh FEDh FEEh FEFh FF0h FF1h FF2h FF3h FF4h FF5h FF6h FF7h FF8h FF9h FFAh FFBh FFCh FFDh FFEh FFFh PLUSW1 PREINC1 POSTDEC1 POSTINC1 INDF1
LATA LATB LATC LATD LATE
RCSTA TXSTA TXREG RCREG SPBRG T3CON TMR3L TMR3H
PIE1 PIR1 IPR1
CCP2CON CCPR2L CCPR2H CCP1CON CCPR1L CCPR1H
PLUSW2 PREINC2 POSTDEC2 POSTINC2 INDF2
PLUSW0 PREINC0 POSTDEC0 POSTINC0 INDF0 INTCON3 INTCON2 INTCON PRODL PRODH TABLAT TBLPTRL TBLPTRH TBLPTRU PCL PCLATH PCLATU TOSL TOSH TOSU
31
32
16
Data
8 Bits Carry Bit
WREG ALU
8 Bits N, OV, Z, DC, C Dr. Rodolfo J. Castell Z. 33
STATUS
Bit
0
Symbol
C
Reset value
R/W-x
Description
Carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF) 1 = A carry-out from the MSb of the result occurred 0 = No carry Digit carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF) 1 = A carry-out of the Least Significant Nibbles Msb of the result occurred 0 = No carry-out from the 4th low order bit of the result Zero Bit 1 = The result of an arithmetic or logic operation is cero. 0 = The result of an arithmetic or logic operation is NO cero. Overflow Bit 1 = Overflow on bit 7 for arithmetic signed operations. 0 = No overflow. Negative Bit 1 = Result was negative, when the MSb = 1 0 = Result was positive. Unimplemented, read as0
Significado de los valores de Reset R Readable bit 1 - Bit is set 0 Bit is cleared x Bit is unknown U Unimplemented bit, read as 0
DC
R/W-x
R/W-x
OV
R/W-x
R/W-x
5-7
U-O
W Writable bit
34
17
PIC18F4585 Pin Out
35
36
18
37
I/O Ports
38
19
I/O Ports
39
Bit RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7
Function AN0/CVREF AN1 AN2/VREFAN3/VREF+ T0CKI AN4/SS OSC2 OSC1
Description A/D input channel 0 / Comparator Voltage ref A/D input channel 1 A/D input channel 2 / Negative Voltage ref. A/D input channel 3 / Positive Voltage reg. TIMER 0 External Clock Signal Input A/D input channel 4 External Oscillator External Oscillator
Default Function (POR) As Analog Inputs (AN0) As Analog Inputs (AN1) As Analog Inputs (AN2) As Analog Inputs (AN3) As Digital Input (RA4) As Analog Inputs (AN4) As Digital Input (RA6) External RC Oscillator 40
20
41
Port A
42
21
MOVLW MOVWF MOVLW MOVWF
0x00 TRISA 0x3A PORTA
; WREG = 0 ; PORT A as output ; WREG = 0x3A ; Write 0x3A to PORT A
MOVLW MOVWF MOVFF
0xFF TRISA PORTA, W
; WREG = 255 ; PORT A as input ; WREG = PORT A

43
Bit RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7
Function AN10/INT0 AN8/INT1 CANTX/INT2 CANRX AN9/KBIO KBI1 KBI2 KBI3
Description A/D channel 10 / External Interruption #0 A/D channel 8 / External Interruption #1 CAN transmit / External Interruption #2. CAN receive A/D channel 9 / Interrupt on pin change Interrupt on pin change Interrupt on pin change Interrupt on pin change
Default Function (POR) As Analog Inputs (AN10) As Analog Inputs (AN8) As Analog Inputs As Analog Inputs As Analog Inputs (AN9) As Digital Input As Digital Input As Digital Input 44
22
45
Port B
list p=18f4585 #include "p18f4585.inc" CONFIG CONFIG MOVLW MOVWF CLRF CLRF MOVLW MOVWF PBADEN = OFF LVP= OFF 0x0F ADCON1 PORTB LATB 0xFF / 0x00 TRISB ; CONFIG3H.1 = 0: RBO RB4 digital ; CONFIG4L.2 = 0: RB5 digital ; WREG = 0x07 ; Disables A/D Converter ; PORTB reset ; Clears latch ; Set bits as inputs or outputs
46
23
Their double functionality is activated when the related devices are used. (see data sheet)
47
Port C
CLRF CLRF MOVLW MOVWF
PORTC LATC 0xFF / 0x00 TRISC
; PORTC reset ; Clears latch ; Set bits as inputs or outputs
48
24
Bit RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7
Function PSP0/C1IN+ PSP1/C1INPSP2/C2IN+ PSP3/C2INPSP4/ECCP1 PSP5/ECCP1 PSP6/ECCP1 PSP7/ECCP1
Description Parallel Slave Port / Comparator 1 Pos IN Parallel Slave Port / Comparator 1 Neg IN Parallel Slave Port / Comparator 2 Pos IN Parallel Slave Port / Comparator 2 Neg IN Parallel Slave Port / Comparator Out Parallel Slave Port / Comparator Out Parallel Slave Port / Comparator Out Parallel Slave Port / Comparator Out
Default Funtion (POR) Comparator 1 Pos IN (C1IN+) Comparator 1 Neg IN (C1IN-) Comparator 2 Pos IN (C2IN) Comparator 2 Neg IN (C2IN-) I/O Digital I/O Digital I/O Digital I/O Digital 49
Port D
50
25
Port D
MOVLW MOVWF CLRF CLRF MOVLW MOVWF
0x07 CMCON PORTD LATD 0xFF / 0x00 TRISD
; WREG = 0x07 ; Disables Comparators CM2:CM0 = 111 ; PORTD reset ; Clears latch ; Set bits as inputs or outputs
51
Bit RE0 RE1 RE2 RE3
Function AN5 AN6 AN7 MCLR
Description A/D channel 5 A/D channel 6 A/D channel 7 External Reset Input
Default Function (POR) As Analog Inputs (AN5) As Analog Inputs (AN6) As Analog Inputs (AN7) Master Reset
52
26
53
Read Followed by Write I/O Operation
loop
CLRF SETF MOVF MOVWF BRA
TRISB TRISC PORTC, W PORTB loop
;PORTB as Output ;PORTC as Input ;WREG PORTC ;PORTB WREG
54
27

Read After Write (RAW) cycle:
Instruction
Fetch D R P W MOVF PORTC, W ;WREG Port C
Fetch
D R P
MOVWF PORTB
;Port B WREG
Meaning of Letter Values
55
loop
CLRF SETF MOVF NOP MOVWF BRA
TRISB TRISC PORTC, W PORTB loop
;PORTB as Output ;PORTC as Input ;WREG PORTC ;PORTB WREG

56
loop
CLRF SETF MOVFF BRA
TRISB ;PORTB as Output TRISC ;PORTC as Input PORTC, PORTB ;PORTB PORTC loop
28
Some of the features that can be configured are: Oscillator selection, Type of Resets, Interruptions, Code Protection. Etc see data sheet.
Dr. Rodolfo J. Castell Z. 57
58
29
Configuration Registers
FLASH ROM`

CONFIG1H CONFIG2L CONFIG2H CONFIG3H CONFIG4L CONFIG5L CONFIG5H CONFIG6L CONFIG6H CONFIG7L
CONFIG7H DEVID1 DEVID2
59
The way to set the configuration through table writing will be seen in the following chapter when table operations are introduced.
60
30
61
Configuration Registers
62
31
7. Minimum System
10K 100K
27 pF
Vcc
4 MHz
27 pF
Dr. Rodolfo J. Castell Z. 63
32

MC TE3001 Chapter 3 Architecture PIC18 1

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TE3001 Microcontrollers

Dr. Rodolfo J. Castell Z.

Dr. Rodolfo J. Castell Z.

PIC18 Clock Sources

PIC18 Clock Sources

Mode EC ECIO LP XT HS RC RCIO HS4

PIC18 Clock Sources

Source: PIC18C Reference Manual, Microchip DS39500a, 2000

Dr. Rodolfo J. Castell Z.

PIC18 Clock Sources

Oscillator Mode RCIO HS4 ECIO EC RC HS XT LP

PIC18F4585 Clock Sources

PIC18F4585 Clock Sources

Mode EC ECIO LP XT HS RC RCIO HSPLL INTIO1 INTIO2

PIC18F4585 Clock Sources

IOFS OSTS IRCF2:IRCF0

PIC18F4585 Clock Sources

Oscillator Mode RC INTIO1 INTIO2 RCIO HSPLL EC ECIO

FOSC3:FOSC0 Configuration Bits 0001 0000

Source: PIC18F4585 Data Sheet, Microchip DS39625C, 2007 11

Program Memory (Flash)

Data Memory (SFRs and GP RAM)

Dr. Rodolfo J. Castell Z.

BSR Access Bank

I/O Ports 8 8 Timers EEPROM A/D Converter

Serial Port Parallel Port

Dr. Rodolfo J. Castell Z.

Dr. Rodolfo J. Castell Z.

Dr. Rodolfo J. Castell Z.

Dr. Rodolfo J. Castell Z.

PIC18F4585 Program Memory

Internal Program Memory

SFRs to Control Program Memory

Code Storage in Program Memory

Address 000000H 000001H 000002H 000003H 000004H 000005H 000006H 000007H

0x55 0x0F 0x23 0xC1 0x56 0x04

0x55 0x123, 0x456

Dr. Rodolfo J. Castell Z.

RAM Data Memory Map for the PIC 18 Family

See Data Sheet for each PIC

BSR <3 0>

" " " "

" " " "

" " " "

Access Bank GPRs SFRs

00H 7FH 80H FFH

Dr. Rodolfo J. Castell Z.

Bank Select Register (BSR)

" " "

Dr. Rodolfo J. Castell Z.

Bank Select Register (BSR)

Dr. Rodolfo J. Castell Z.

Access Bank GPRs SFRs

00H 7FH 80H FFH

Dr. Rodolfo J. Castell Z.

Dr. Rodolfo J. Castell Z.

Dr. Rodolfo J. Castell Z.

Dr. Rodolfo J. Castell Z.

Bank #15, PIC18 Basic SFRs Set

LATA LATB LATC LATD LATE

RCSTA TXSTA TXREG RCREG SPBRG T3CON TMR3L TMR3H

PIE1 PIR1 IPR1

CCP2CON CCPR2L CCPR2H CCP1CON CCPR1L CCPR1H