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Product specification
ADC0803/4-1
DESCRIPTION
The ADC0803 family is a series of three CMOS 8-bit successive approximation A/D converters using a resistive ladder and capacitive array together with an auto-zero comparator. These converters are designed to operate with microprocessor-controlled buses using a minimum of external circuitry. The 3-State output data lines can be connected directly to the data bus. The differential analog voltage input allows for increased common-mode rejection and provides a means to adjust the zero-scale offset. Additionally, the voltage reference input provides a means of encoding small analog voltages to the full 8 bits of resolution.
PIN CONFIGURATION
D1, N PACKAGES CS 1 RD 2 WR 3 CLK IN 4 20 VCC 19 CLK R 18 D0 17 D1 16 D2 15 D3 14 D4 13 D5 12 D6 11 D7
FEATURES
VREF/2 9 D GND 10 TOP VIEW NOTE: SOL Released in large SO package only.
Compatible with most microprocessors Differential inputs 3-State outputs Logic levels TTL and MOS compatible Can be used with internal or external clock Analog input range 0V to VCC Single 5V supply Guaranteed specification with 1MHz clock
APPLICATIONS
Transducer-to-microprocessor interface Digital thermometer Digitally-controlled thermostat Microprocessor-based monitoring and control systems
ORDERING INFORMATION
DESCRIPTION 20-Pin Plastic Dual In-Line Package (DIP) 20-Pin Plastic Dual In-Line Package (DIP) 20-Pin Plastic Small Outline (SO) Package 20-Pin Plastic Small Outline (SO) Package TEMPERATURE RANGE -40 to +85C 0 to 70C 0 to 70C -40 to 85C ORDER CODE ADC0803/04-1 LCN ADC0803/04-1 CN ADC0803/04-1 CD ADC0803/04-1 LCD DWG # 0408B 0408B 1021B 1021B
555
853-0034 13721
Product specification
ADC0803/4-1
BLOCK DIAGRAM
VIN (+) 6 VIN () 7
9
VREF/2 LADDER AND DECODER
8 A GND
VCC
20
D7 (MSB) (11) D6 D5 D4 D3 D2 D1 D0 (LSB) (12) (13) (14) (15) (16) (17) (18)
1 CS S INTR FF R 2 RD Q
5 INTR
4 CLK IN
19 CLK R
556
Product specification
ADC0803/4-1
DC ELECTRICAL CHARACTERISTICS
VCC = 5.0V, fCLK = 1MHz, TMIN TA TMAX, unless otherwise specified. SYMBOL PARAMETER ADC0803 relative accuracy error (adjusted) ADC0804 relative accuracy error (unadjusted) RIN VREF/2 input resistance3 Analog input voltage range3 DC common-mode error Power supply sensitivity Control inputs VIH VIL IIH IIL VT+ VT VH VOL VOH VOL Logical 1 input voltage Logical 0 input voltage Logical 1 input current Logical 0 input current VCC = 5.25VDC VCC = 4.75VDC VIN = 5VDC VIN = 0VDC 1 0.005 0.005 2.0 15 0.8 1 VDC VDC ADC ADC 3.5 2.1 2.0 0.4 2.4 VDC VDC VDC VDC VDC Over analog input voltage range VCC = 5V 10%1 TEST CONDITIONS Full-Scale adjusted VREF/2 = 2.500VDC VCC = 0V2 400 0.05 1/16 1/16 680 VCC+0.05 1/8 ADC0803/4 Min Typ Max 0.50 1 UNIT LSB LSB V LSB LSB
Clock in and clock R Clock in positive-going threshold voltage Clock in negative-going threshold voltage Clock in hysteresis (VT+)(VT) Logical 0 clock R output voltage Logical 1 clock R output voltage IOL = 360A, VCC = 4.75VDC IOH = 360A, VCC = 4.75VDC 2.7 1.5 0.6 3.1 1.8 1.3
Data output and INTR Logical 0 output voltage Data outputs INTR outputs VOH IOZL IOZH ISC ISC ICC Logical 1 output voltage 3-state output leakage 3-state output leakage +Output short-circuit current Output short-circuit current Power supply current IOL = 1.6mA, VCC = 4.75VDC IOL = 1.0mA, VCC = 4.75VDC IOH = 360A, VCC = 4.75VDC IOH = 10A, VCC = 4.75VDC VOUT = 0VDC, CS = logical 1 VOUT = 5VDC, CS = logical 1 VOUT = 0V, TA = 25C VOUT = VCC, TA = 25C fCLK = 1MHz, VREF/2 = OPEN, CS = Logical 1, TA = 25C 4.5 9.0 12 30 3.0 3.5 2.4 4.5 3 3 0.4 0.4 VDC VDC VDC ADC ADC mADC mADC mA
NOTES: 1. Analog inputs must remain within the range: 0.05 VIN VCC + 0.05V. 2. See typical performance characteristics for input resistance at VCC = 5V. 3. VREF/2 and VIN must be applied after the VCC has been turned on to prevent the possibility of latching.
557
Product specification
ADC0803/4-1
AC ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER Conversion time fCLK Clock frequency1 Clock duty cycle1 CR tW(WR)L tACC t1H, t0H tW1, tR1 CIN COUT Free-running conversion rate Start pulse width Access time 3-State control INTR delay Logic input=capacitance 3-State output capacitance Output Output INTR RD RD WD or RD CS=0, fCLK=1MHz INTR tied to WR CS=0 CS=0, CL=100pF CL=10pF, RL=10k See 3-State test circuit 30 75 70 100 5 5 100 100 150 7.5 7.5 TO FROM TEST CONDITIONS fCLK=1MHz1 ADC0803/4 Min 66 0.1 40 1.0 Typ Max 73 3.0 60 13690 UNIT s MHz % conv/s ns ns ns ns pF pF
NOTES: 1. Accuracy is guaranteed at fCLK=1MHz. Accuracy may degrade at higher clock frequencies.
FUNCTIONAL DESCRIPTION
These devices operate on the Successive Approximation principle. Analog switches are closed sequentially by successive approximation logic until the input to the auto-zero comparator [ VIN(+)-VIN(-) ] matches the voltage from the decoder. After all bits are tested and determined, the 8-bit binary code corresponding to the input voltage is transferred to an output latch. Conversion begins with the arrival of a pulse at the WR input if the CS input is low. On the High-to-Low transition of the signal at the WR or the CS input, the SAR is initialized, the shift register is reset, and the INTR output is set high. The A/D will remain in the reset state as long as the CS and WR inputs remain low. Conversion will start from one to eight clock periods after one or both of these inputs makes a Low-to-High transition. After the conversion is complete, the INTR pin will make a High-to-Low transition. This can be used to interrupt a processor, or otherwise signal the availability of a new conversion result. A read (RD) operation (with CS low) will clear the INTR line and enable the output latches. The device may be run in the free-running mode as described later. A conversion in progress can be interrupted by issuing another start command.
558
Product specification
ADC0803/4-1
Large values of source resistance where an input bypass capacitor is not used will not cause errors as the input currents settle out prior to the comparison time. If a low pass filter is required in the system, use a low valued series resistor (< 1k) for a passive RC section or add an op amp active filter (low pass). For applications with source resistances at or below 1k, a 0.1F bypass capacitor at the inputs will prevent pickup due to series lead inductance or a long wire. A 100 series resistor can be used to isolate this capacitor (both the resistor and capacitor should be placed out of the feedback loop) from the output of the op amp, if used.
Operating Mode
These converters can be operated in two modes: 1) absolute mode 2) ratiometric mode In absolute mode applications, both the initial accuracy and the temperature stability of the reference voltage are important factors in the accuracy of the conversion. For VREF/2 voltages of 2.5V, initial errors of 10mV will cause conversion errors of 1 LSB due to the gain of 2 at the VREF/2 input. In reduced span applications, the initial value and stability of the VREF/2 input voltage become even more important as the same error is a larger percentage of the VREF/2 nominal value. See Figure 3. In ratiometric converter applications, the magnitude of the reference voltage is a factor in both the output of the source transducer and the output of the A/D converter, and, therefore, cancels out in the final digital code. See Figure 4. Generally, the reference voltage will require an initial adjustment. Errors due to an improper reference voltage value appear as full-scale errors in the A/D transfer function.
The allowed range of analog input voltages usually places more severe restrictions on input common-mode voltage levels than this, however. An analog input span less than the full 5V capability of the device, together with a relatively large zero offset, can be easily handled by use of the differential input. (See Reference Voltage Span Adjust).
Reference Voltage
For application flexibility, these A/D converters have been designed to accommodate fixed reference voltages of 5V to Pin 20 or 2.5V to Pin 9, or an adjusted reference voltage at Pin 9. The reference can be set by forcing it at VREF/2 input, or can be determined by the supply voltage (Pin 20). Figure 1 indicates how this is accomplished.
559
Product specification
ADC0803/4-1
differential mode of the converter. Any offset adjustment should be done prior to full scale adjustment.
At higher CPU clock frequencies, time can be extended for I/O reads (and/or writes) by inserting wait states (8880) or using clock-extending circuits (6800, 8035). Finally, if time is critical and capacitive loading is high, external bus drivers must be used. These can be 3-State buffers (low power Schottky is recommended, such as the N74LS240 series) or special higher current drive products designed as bus drivers. High current bipolar bus drivers with PNP inputs are recommended as the PNP input offers low loading of the A/D output, allowing better response time.
POWER SUPPLIES
Noise spikes on the VCC line can cause conversion errors as the internal comparator will respond to them. A low inductance filter capacitor should be used close to the converter VCC pin and values of 1F or greater are recommended. A separate 5V regulator for the converter (and other 5V linear circuitry) will greatly reduce digital noise on the VCC supply and the attendant problems.
Continuous Conversion
To provide continuous conversion of input data, the CS and RD inputs are grounded and INTR output is tied to the WR input. This INTR/WR connection should be momentarily forced to a logic low upon power-up to insure circuit operation. See Figure 5 for one way to accomplish this.
560
Product specification
ADC0803/4-1
decoder. The RD and WR signals are generated by reading from and writing to a dummy address.
A Digital Thermostat
Circuit Description The schematic of a Digital Thermostat is shown in Figure 11. The A/D digitizes the output of the LM35, a temperature transducer IC with an output of 10mV per C. With VREF/2 set for 2.56V, this 10mV corresponds to 1/2 LSB and the circuit resolution is 2C. Reducing VREF/2 to 1.28 yields a resolution of 1C. Of course, the lower VREF/2 is, the more sensitive the A/D will be to noise. The desired temperature is set by holding either of the set buttons closed. The SCC80C451 programming could cause the desired (set) temperature to be displayed while either button is depressed and for a short time after it is released. At other times the ambient temperature could be displayed. The set temperature is stored in an SCN8051 internal register. The A/D conversion is started by writing anything at all to the A/D with port pin P10 set high. The desired temperature is compared with the digitized actual temperature, and the heater is turned on or off by clearing setting port pin P12. If desired, another port pin could be used to turn on or off an air conditioner. The display drivers are NE587s if common anode LED displays are used. Of course, it is possible to interface to LCD displays as well.
561
Product specification
ADC0803/4-1
5.5V
REF/2
1.60
+25oC +125oC
1.50
VO = 2.5V
1.40
8 6 50
1.30 4.50
4.75
5.00
5.25
5.50
4.75
5.00
5.25
5.50
25
25
50
75
100
125
2.5V
200
400
600
800
1000
562
Product specification
ADC0803/4-1
RD GND
RD GND
VOH
GND
GND
t1H
tOH
TIMING DIAGRAMS (All timing is measured from the 50% voltage points)
START CONVERSION CS
WR
tWI tW(WR)L BUSY ACTUAL INTERNAL STATUS OF THE CONVERTER INTR (LAST DATA WAS NOT READ) INT ASSERTED 1/2 TCLK NOT BUSY (LAST DATA WAS READ) 1 TO 8 X 1/fCLK INTERNAL TC DATA IS VALID IN OUTPUT LATCHES
INTR
INTR RESET
CS
tRI
563
Product specification
ADC0803/4-1
VCC
20
VREF
(5V) VREF
R VREF/2 9 FS OFFSET ADJUST DIGITAL CIRCUITS ZS OFFSET ADJUST + 330 TO VREF/2 0.1F
ANALOG CIRCUITS
TO VIN()
Figure 2. Offsetting the Zero Scale and Adjusting the Input Range (Span)
8 10
NOTE: The VREF/2 voltage is either 1/2 the VCC voltage or is that which is forced at Pin 9.
+5V
+
10F A/D
2k 2k
10F
VREF/2 VREF/2
100
VIN()
2k
2k
a. Fixed Reference
VCC
VCC
+
10F
2k
VIN()
VREF/2
2k
564
Product specification
ADC0803/4-1
10k +5V CS RD WR 10K 2.7k CLK IN INTR 10k 47F TO 100F VIN(+) 56pF VIN() A GND VREF/2 1 2 3 4 5 6 7 8 9 A/D 20 VCC 19 CLK R 18 D0 17 D1 16 D2 15 D3 14 D4 13 D5 12 D6 11 D7 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0
+5V
D GND 10
CLK R 19
R CLK IN 4 VCC 40 1 fCLK = 1/1.7 R C R = 10K 2 3 4 5 6 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 D0 18 D1 17 D2 16 D3 15 D4 14 D5 13 D6 12 D7 11 A/D 6 VIN(+) 7 VREF/2 12 A GND 11 D GND ANALOG INPUTS 4 CLK IN 56pF 10k VCC
20
19 CLK R
CLK
C
A/D
SCN8051 OR SCN80C51
7 8
17 RD 16 WR 12 INTO 39 P0.0
RD 2 WR 3 INTR CS 5 1
OE
Figure 9. Buffering the A/D Output to Drive High Capacitance Loads and for Driving Off-Board Loads
565
Product specification
ADC0803/4-1
+5V
Ct
1F
4.7k
0.47F
470
VCC VIN(+)
566
Product specification
ADC0803/4-1
6 2 1 1/4 HEF4071 7 3
RBI 5
NE587
8 RBO 4
10K
6 2 1 1/4 HEF4071 7 3
RBI 5
NE587
8 10K
13
14 18 17 16 15 14 13 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 D0 18 D1 17 D2 16 D3 15 D4 14 D5 13 D6 12 D7 11 A/D 4 10K CLK IN 56pF 8 10 6 27 RD WR INT P10 RD 2 WR INTR CS 3 5 1 D GND 10 8 6 VIN(+) 7 VIN() A GND LM35 19 CLK R 20 VCC + 10F +5V
SCC80C51
12 11
+V 2N3906
29 P12 20 GND
1N4148
TO HEATER
567