No.132, AECS Layout, I.T.P.L. Road, Kundalahalli, Bangalore 560 037 Ph: 080 28524466, Extn: 213 (EC Dept. HOD)
A LAB MANUAL ON
ANALOG ELECTRONICS
Subject Code: 06ESL37
(As per VTU Syllabus)
PREPARED BY
No.132, AECS Layout, I.T.P.L. Road, Kundalahalli, Bangalore 560 037 Ph: 080 28524466, Extn: 213 (EC Dept. HOD)
CONTENTS
EXPT. NO.
01 02 03 04 05 06 07 08 09 10 11 12 13 14
NAME
OF THE
EXPERIMENT
PAGE NO.
01 10 16 23 31 38 41 45 51 55 59 63 65 66
Half wave, full wave and bridge rectifier Clamping circuits Clipping circuits RC coupled amplifier using BJT and FET Hartley oscillator / Colpitts oscillator Crystal oscillator RC phase shift oscillator Voltage series feedback amplifier using BJT Thevenins theorem and maximum power transfer theorem
Series and parallel resonance circuits. Darlington emitter follower. ClassB push pull power amplifier. Bibliography Vivovoce questions
Ex.No:01
AIM:
To study Half Wave Rectifier and to calculate ripple factor, efficiency and regulation with filter and without filter. COMPONENTS REQUIRED:
Sl. No. Components Details Specification Qty
1. 2. 3. 4. 5. THEORY:
Half wave rectifier circuit consists of resistive load, a diode and source of ac voltage, all connected in series. In half wave rectifier, rectifying element conducts only during positive half cycle of input ac supply. The negative half cycles of ac supply are eliminated from the output. The dc output waveform is expected to be a straight line but the half wave rectifier gives output in the form of positive sinusoidal pulses. Thus the output is called pulsating dc. CIRCUIT DIAGRAM: HALF WAVE RECTIFIER WITHOUT FILTER CAPACITOR
Step down Transformer
12V
Ammeter(0250mA)
A K BY127
C2 0.1UF
VODC
AC (230V/50HZ)
0
RL
VOAC
12V
12V
Ammeter(0250mA)
A K BY127
C2 0.1UF
+ C1
AC (230V/50HZ)
RL
VODC
VOAC
12V
470UF 
DESIGN:
VINrm s = 12V
VINm = 2VINrms = 16 .97 V
VO( DC ) = Vm / = 5.4V
Given
Ripple = r = Vo rms / VO DC = 1.21 Design for the filter capacitor Ripple = 1/(43 f C RL) Given r = 0.25 C = 1/(43 f r RL) RL = 50 f = 50Hz Efficiency = 461.88 F = PDC /PAC 470 F 2 2 * (RL + RF)] (I DC * RL) / [(Irms)
Regulation
PROCEDURE: 1. Connections are made as shown in the circuit diagram 2. Switch on the AC power supply 3. Observe the wave form on CRO across the load resistor and measure the o/p amplitude and frequency.
4. Note down RL, IDC, VODC, VINAC, and VOAC in the tabular column for different
load resistances.
5. Calculate the ripple and efficiency and Regulation for each load resistance. 6. Repeat the above procedure with filter capacitor. TABULAR COLUMN: Sl. No. RL IDC VO (DC) VIN
(AC)
VO (AC)
Ripple
Efficiency
Regulation
WAVEFORMS:
20 VIN 0  20 t
VO
0 t
Vo (Without Filter)
VC Vo (with filter)
FULL WAVE RECTIFIER AIM: To study the full wave rectifier and to calculate ripple factor and efficiency and Regulation with filter and without filter. COMPONENTS REQUIRED:
Sl. No. Components Details Specification Qty
1. 2. 3. 4. 5. THEORY:
The center tapped full wave rectifier circuit is similar to a half wave rectifier circuit, using two diodes and a center tapped transformer. Both the input half cycles are converted into unidirectional pulsating DC. CIRCUIT DIAGRAM: FULL WAVE RECTIFIER WITHOUT FILTER CAPACITOR
Step down Transformer
12V
Ammeter(0250mA)
A K BY127
C2 0.1UF
VO(DC)
AC (230V/50HZ)
0
RL A K BY127
VO (AC)
12V
12V
Ammeter(0250mA)
A K BY127
C2 0.1UF
+ C1
AC (230V/50HZ)
0
A K BY127
RL
VO(DC)
VO(AC)
12V
470UF 
DESIGN: Vin rms = 12V Vin m = 2Vin rms = 16.97V VO DC = 2Vm/ = 10.8V Given VO DC = 10V IO DC = 100mA RL = VO DC / IO DC = 100
Ripple = r = Vo rms / VO DC = 0.48 Design for the filter capacitor Ripple = 1/(43 f C RL) Given r = .06 C = 1/(43 f r RL) RL = 100 f = 50Hz = 470UF Efficiency Regulation PROCEDURE: 1. Connections are made as shown in the circuit diagram 2. Switch on the AC power supply 3. Observe the wave form on CRO across the load resistor and measure the o/p amplitude and frequency.
4. Note down RL, IDC, VODC
= PDC /PAC (I2DC * RL) / [(Irms)2 * (RL + RF)] VNL VFL 100 VFL % Regulation =
load resistances.
5. Calculate the ripple and efficiency and regulation for each load resistance. 6. Repeat the above procedure with filter capacitor. TABULAR COLUMN: Sl. No. RL IDC VO (DC) VIN
(AC)
VO (AC)
Ripple
Efficiency
Regulation
WAVEFORMS:
t
VIN
0 
VO
0 t
Vo (Without Filter)
VC
Vo (with filter)
BRIDGE RECTIFIER AIM: To study the bridge rectifier and to calculate ripple factor and efficiency and regulation with filter and without filter. COMPONENTS REQUIRED:
Sl. No. Components Details Specification Qty
1. 2. 3. 4. 5. THEORY:
The bridge rectifier circuit is essentially a full wave rectifier circuit, using four diodes, forming the four arms of an electrical bridge. To one diagonal of the bridge, the ac voltage is applied through a transformer and the rectified dc voltage is taken from the other diagonal of the bridge. The main advantage of this circuit is that it does not require a center tap on the secondary winding of the transformer; ac voltage can be directly applied to the bridge. The bridge rectifier circuit is mainly used as a power rectifier circuit for converting ac power to dc power, and a rectifying system in rectifier type ac meters, such as ac voltmeter in which the ac voltage under measurement is first converted into dc and measured with conventional meter. CIRCUIT DIAGRAM: BRIDGE RECTIFIER WITHOUT FILTER CAPACITOR
Step down Transformer Ammeter(0250mA)
12V
BRIDGE
C2 0.1UF
+
+ 4
AC (230V/50HZ)
2 
RL
Vo
12V
12V
B R ID G E 1
C 2 0 .1 U F
+
+ 4
A C (2 3 0 V / 5 0 H Z )
C 1 470U F
R L
Vo
+ 
12V
DESIGN: Vin rms = 12V Vin m = 2Vin rms = 16.97V VO DC = 2Vm/ = 10.8V Given VO DC = 10V IO DC = 100mA RL = VO DC / IO DC = 100
Ripple = r = Vo rms / VO DC = 0.48 Design for the filter capacitor Ripple = 1/(43 f C RL) Given r = .06 C = 1/(43 f r RL) RL = 100 f = 50Hz = 470UF Efficiency = PDC /PAC = (I2DC * RL) / [(Irms)2 * (RL + RF)]
Regulation
PROCEDURE: 1. Connections are made as shown in the circuit diagram 2. Switch on the AC power supply 3. Observe the wave form on CRO across the load resistor and measure the o/p amplitude and frequency.
4.
5. Calculate the ripple factor, efficiency and regulation for each load resistance. 6. Repeat the above procedure with filter capacitor. TABULAR COLUMN: Sl. No. RL IDC VO (DC) VIN
(AC)
VO (AC)
Ripple
Efficiency
Regulation
WAVEFORMS: Vin 20 t 0  20
Vo 0 t Vo (Without Filter)
Ex.No:02
AIM:
CLAMPING CIRCUITS
1. 2.
Diodes Capacitors
BY127 0.1 F
1 No 1 No
Signal generator, Cathode Ray Oscilloscope (CRO) with Probes, Dual Power Supply, Connecting Board THEORY: A clamper is one, which provides a D.C shift to the input signal. The D.C shift can be positive or negative. The clamper with positive D.C shift is called positive clamper and clamper with negative shift is called negative clamper. Consider a clamper circuit shown below.
0 . 1 u + 
C V i n
B
D Y
V o
1 2 7
In the positive half cycle as the diode is forward biased the capacitor charges to the value ( VIN VD ) with the polarity as shown in the figure. In the negative half cycle the diode is reverse biased. Hence the output is VO = VIN VC . Initially let us assume that the capacitor has charged to i.e. (5 0.5) = 4.5V Then in the positive half cycle diode is forward biased and applying KVL to the loop, Vin VC V0 = 0 When Vin = 0 Vin = 5V In the negative half cycle When Vin = 5V down by 4.5V The peak to peak voltage at the output of a clamper is the same as that of the input.
Department of Electronics & Communication Engg. CMRIT 10
( VIN VD )
V0 =Vin VC
The output shifts between 0.5V and 9.5V.Here the output has shifted
CIRCUIT DIAGRAM AND DESIGN: Given Vin = 10V (pp) A] In the positive half cycle: Diode is forward biased. Applying KVL to loop 1 Vin VC VD = 0 VC = Vin VD = 5  0.5 4.5V In the negative half cycle: Vin VC V0 = 0 V0 = Vin VC When Vin = 0 When Vin = 5V V0 =  4.5V V0 = 0.5V
V i n
B Y 1 2 7 + 0 . 1 u
V o
When Vin = 5V V0 = 9.5V B]In the negative half cycle: Diode is forward biased Applying KVL to loop 1 Vin + VC + VD = 0 VC =  ( Vin + VD) VC =  (5 + 0.5) = 4.5V In the positive half cycle: Diode is reverse biased. Apply KVL to the loop Vin + VC V0 = 0 V0 = Vin + VC When Vin = 0 When Vin = 5V When Vin =  5V V0 = 4.5V V0 = 5 + 4.5 = 9.5V V0 =  0.5V
V i n

0
+
. 1
u B Y 1 D2 71
V o
11
C] Assume VR = 2V In the positive half cycle: Diode is forward biased. Apply KVL to loop 1 Vin VC VD VR = 0 VC = Vin VD VR = 5  0.5 2 = 2.5V In the negative half cycle: Diode is reverse biased Vin VC V0 = 0 V0 = Vin VC When Vin = 0V When Vin = 5V When Vin = 5V D] Assume VR = 2V In the positive half cycle: Diode is forward biased and the capacitor charges. Apply KVL to loop 1 Vin VC VD + VR = 0 VC = Vin VD + VR = 5 0.5 +2 = 6.5V In the negative half cycle: Vin VC V0 = 0 V0 = Vin VC When Vin = 0V When Vin = 5V When Vin = 5V V0 =  6.5V V0 =  1.5V V0 =  11.5V
Vin VR
+ +
0.1u

D1 BY127
Vin VR
Vo
0.1u

D1 BY127
Vo
12
E]In the negative half cycle: Assume VR = 2V Diode is forward biased and capacitor charges. Apply KVL to the loop1 Vin + VC + VD + VR = 0 VC =  ( Vin + VR + VD) =  ( 5 + 0.5 + 2) = 2.5V From the fig. we see that Vin + VC V0 = 0 V0 = Vin + VC When Vin = 0 When Vin = 5V When Vin = 5V F] VR = 2V In the negative half cycle: Diode is forward biased and capacitor charges. Apply KVL to loop 1 Vin + VC + VD  VR =0 VC =  ( Vin + VD  VR) =  ( 5 + 0.5 2) = 6.5V From the circuit we see that, Vin + VC  V0 =0 V0 = Vin VC When Vin =0V When Vin = 5V When Vin =  5V PROCEDURE: 1. Rig up the circuit as shown in the circuit diagram. 2. Give a sinusoidal input of 10V peak to peak 3. Check and verify the output. V0=6.5V V0= 11.5V V0= 1.5V
Vin

0.1u
+
Vin
BY127
D1
Vo VR
BY127
D1
Vo
VR
13
WAVEFORMS: Vin
5V
 5V
V0
0.5 0
[A]
 4.5  9.5
V0
9.5
4.5
[B] 
0 0.5
V0
2.5 0
[C]
 2.5
 7.5
14
V0 [D]
0  1.5 t
 6.5
 11.5
V0
7.5
2.5
[E]
0  2.5
V0
11.5
6.5
[F]
1.5 0 t
RESULT:
15
Ex.No:03
AIM:
CLIPPING CIRCUITS
1. 2. THEORY:
Diodes Resistors
BY127 10 K
1 No 1 No
The process by which the shape of a signal is changed by passing the signal through a network consisting of linear elements is called linear wave shaping. Most commonly used wave shaping circuit is clipper. Clipping circuits are those, which cut off the unwanted portion of the waveform or signal without distorting the remaining part of the signal. There are two types of clippers namely parallel and series. A series clipper is one in which the diode is connected in series with the load and a parallel clipper is one in which the diode is connected in parallel with the load. CIRCUIT DIAGRAM AND DESIGN: Assume Vin = 10V (Peak to Peak) (a) Consider the circuit in fig. 1 In the positive half cycle D is forward biased In the negative half cycle D is reverse biased V0 = 0V (b) Consider the circuit in fig. 2 In the positive half cycle D is reverse biased V0 = 0V In the negative half cycle D is forward biased Applying KVL to the loop Vin + VD V0 = 0 V0 = Vin + VD = 5 + 0.5 =  4.5V
V i n
B D Y 1 1 2 7
( a )
D B Y
1 1 2 7
V i n
1 0 kV o
1 0 kV o
16
(c) Consider the circuit in fig. 3 Given VR = 2.5V In the positive half cycle (i) When Vin > VD + VR, D is forward biased Applying KVL, we get Vin = VD + VR + V0 V0 = Vin VD VR V0 = 5 0.5 2.5 V0 = 2V (ii) When Vin < VD + VR, D is reverse biased V0 = 0V In the negative half cycle, D is reverse biased V0 = 0V (d) Consider the circuit in fig. 4 Assume VR = 3V In the positive half cycle, D is reverse biased V0 = 0V In the negative half cycle (i) When Vin > VD + VR, D is forward biased Applying KVL, we get Vin =  VD  VR + V0 V0 = Vin + VD + VR V0 = 5 + 0.5 + 3 V0 = 1.5V (ii) When Vin < VD + VR, D is reverse biased V0 = 0V
V i n
B D Y 1 1 2 D B 1 Y 1 2
V
7
R 1 0 kV o
V i n
V
7
R 1 0 kV o
17
(e) Consider the circuit in fig. 5 Assume VR1 = 2.5V and VR2 = 3V In the positive half cycle, D2 is reverse biased (i) When Vin > VD1 + VR1, D1 is forward biased Applying KVL, we get Vin = VD1 + VR1 + V0 V0 = Vin  VD1  VR1 V0 = 5  0.5 2.5 V0 = 2V V0 = 0V In the negative half cycle (i) When Vin > VD2 + VR2, D2 is forward biased Applying KVL, we get Vin =  VD  VR + V0 V0 = Vin + VD2 + VR2 V0 = 5 + 0.5 + 3 V0 = 1.5V (ii) When Vin < VD2 + VR2, D2 is reverse biased V0 = 0V (f) Consider the circuit in fig. 6 During the positive half cycle, D is forward biased V0 = VD = 0.5V During negative half cycle, D is reverse biased V0 = Vin
V i n 1 0 k
B D Y 1 1 2 7 B Y 1 D 2 2 7 V
V i n
1D 2 2 1 7
1
1 1 0 kV o
V o
18
(g) Consider the circuit in fig. 7 During positive half cycle, D is reverse biased V0 = Vin During negative half cycle, D is forward biased V0 = VD = 0.5V (h)Consider the circuit in fig. 8 During positive half cycle
(i) When Vin > VD + VR,
1 0 k
B Y 1 D 2 1 7
1 0 k V i n
D B Y 1 2 1 7
V o
V i n V R
V o
(ii) When Vin < VD + VR, D is reverse biased V0 = Vin During negative half cycle, D is reverse biased V0 = Vin (i)Consider the circuit in fig. 9 Assume VR = 2.5V During positive half cycle, D is reverse biased V0 = Vin During negative half cycle
(i) When Vin > VD + VR,
B Y
1 0 k
D 1 1 2
+
V i n V R
V o

D is forward biased Applying KVL to the loop, we get V0 = VD  VR =  0.5  2.5 V0 = 3V (ii) When Vin < VD + VR, D is reverse biased V0 = Vin During negative half cycle, D is reverse biased V0 = Vin
19
(j) Consider the circuit in fig. 10 Assume VR1 = VR2 = 2.5V During positive half cycle, D2 is reverse biased. (i) When Vin > VD1 + VR1, D1 is forward biased V0 = VD1 + VR1 = 0.5 + 2.5 V0 = 3V (ii) When Vin < VD1 + VR1, D1 is reverse biased V0 = Vin During negative half cycle, D1 is reverse biased (i)When Vin > VD2 + VR2, D2 is forward biased Applying KVL to the loop, we get V0 = VD2  VR2 = 0.5  2.5 V0 = 3V (ii) When Vin < VD2 + VR2, D2 is reverse biased V0 = Vin (k) Consider the circuit in fig. 11 Assume VR1 = 3.5V and VR2 = 2V During positive half cycle (i) When Vin > VD1 + VR1 D1 is forward biased and D2 is reverse biased V0 = VD1 + VR1 = 0.5 + 3.5 (ii) When Vin < VR2 VD2 D1 is reverse biased and D2 is forward biased V0 = VD2 + VR2 =  0.5 + 2 1.5V During negative half cycle, D1 is reverse biased and D2 is forward biased V0 = VD2 + VR2 =  0.5 + 2 V0 = 1.5V PROCEDURE: 1. Rig up the circuit as shown in the fig. 2. Give a sinusoidal input of 10V peak to peak. 3. Check the output at the output terminal. 4. To plot the transfer characteristics, connect channel 1 of the CRO to the output and channel 2 to the input and press the XY knob 5. Adjust the grounds of both the channels to the centre. 6. Measure the designed values. =4V
Vin 10k
D1 BY127 D2 BY127 Vo B Y
1 0 k
D 1 1 2 D 7 B 2 Y 1 2 7
V i n V R 1
1
V o V R 2
V o
VR1
VR2
20
(a)
t
Vo
Vo (b) 0 t
Vin
 4.5
Vo
2.0 (c) 0 t
Vin 3
Vo
3.5
(d)
0
1.5
Vin
Vo
2 (e) 0 1.5 t
3.5 3
Vin
21
+5
Vo
(f)
0.5 5
t
0.5
Vin
Vo
4.5 (g) 0 t
Vin
0.5
VO
3 (h) t
Vo 3.0 Vin
5
Vo
+5 (i) 0 3 t
3.0 Vin
Vo +3 (j) 3 +4
1.5 (k) 0
t Vo
t
Vin
3.0
Vin
RESULT:
Department of Electronics & Communication Engg. CMRIT 22
Ex.No:04
AIM:
Design an RC coupled single stage BJT amplifier and determine its gain and frequency response, input and output impedances. COMPONENTS REQUIRED:
Sl. No. Components Details Specification Qty
1. 2. 3.
1 No Each 1 No Each 1 No
Vcc = 12 v
R1
22K
Rc
1.2 K
Cc Vo
0.1 f
CB
0.1 f
B
4.7K 330
SL100 CE
47 f
Vs
R2
RE
0
To Find Input Impedance
DRB
I/P
RC COUPLED AMPLIFIER
VOUT
I/P
RC COUPLED AMPLIFIER
D R B
VOUT
23
DESIGN: Given VCC = 12V, IC = 4mA, = 100. RE: W.K.T. VRE = VCC / 10 = 12 / 10 = 1.2V for biasing IE IC = 4 mA From the fig. We see that, IERE = VRE RE = 1.2 / (4 x 103 ) = 300 Therefore RE 330 RC: VCE = VCC / 2 = 6V  for Q point to be in active region. Applying KVL to output loop VCC ICRCVCE VRE = 0 12 4 x 103 RC 6 1.2 = 0 Therefore RC = 1.2k R1 & R2: From biasing circuit VB = VBE+ VRE = 0.7 + 1.2 VB = 1.9V Assume 10 IB flows through R1 and 9 IB flows through R2. W.K.T. IC = IB 4 x 103 = 100 IB Therefore IB = 40 A From the fig. we see that, R1 = VCC VB / 10 IB = 12 1.9 / (10 x 40 x 106 ) = 25.25k Therefore R1 22k R2 = VB / 9IB = 1.9 / ( 9 x 40 x 106 ) = 5.28k Therefore R2 4.7k CE, CC, CB : Let CB = CC = 0.1 F XCE = RE/10 Therefore f = 10 / (2 CE RE) Let f = 100Hz and W.K.T RE = 330 Therefore CE = 10 / 2 f.RE = 48 F Therefore CE 47 F.
24
PROCEDURE: 1) To find Q point: Connect the circuit without Vs and capacitors. Set Vcc= 12V. Measure dc voltages at the base VB, collector Vc and VE with respect to ground Determine VCE = VC VE =  V IC = (VCCVC)/RC =  mA Q point is Q(VCE,IC) To check biasing conditions: With VCC=12V; VCE should be VCC/2 = 6V VRE should be VCC/10 = 1.2V VBE = 0.6V 2) Connect the circuit of Fig(1) 3) Feed a sine wave of peak to peak amplitude about 40Mv from signal generator.
4) Vary the input sine wave frequency from 10Hz
measure the output voltage VO of the amplifier. Input voltage Vi should remain constant throughout the frequency range. 5) Tabulate the results. 6) Plot the graph of frequency f versus Gain in dB and determine the GBW product Procedure to measure input impedance Zi: 1) Connect the circuit of Fig(2). 2) Set the following: DRB to zero. Input sine wave amplitude of 40Mv Input sine wave frequency to any mid band frequency. 3) Measure Vopp. 4) Increase DRB till VO = Vopp/2. The corresponding DRB value gives the input impedance Zi. Procedure to measure output impedance: 1) Connect as in Fig(3). 2) Set the following: DRB to maximum value. Input sine wave amplitude to 40mv. Input sine wave frequency to any mid band frequency 3) Measure Vopp.
Department of Electronics & Communication Engg. CMRIT 25
4) Decrease DRB till Vo = Vopp/2. The corresponding DRB value gives the output impedance Zo. WAVEFORM: Vin
V0
Output Voltage
AV = V0 / Vi
AV (dB) = 20log AV
26
AV (db) 3db
f1 Bandwidth = f2 f1 RESULT:
f2
27
Ex.No:04
AIM:
Design an RC coupled single stage FET amplifier and determine its gain and frequency response, input and output impedances. COMPONENTS REQUIRED: Sl. No. 1. 2. 3. Components Details FET Capacitors Resistors BFW10 0.37 f 100 f 2.2 M , 1 K , 330 , 10 K DC Supply, Signal Generator, CRO with Probe CIRCUIT DIAGRAM:
VDD = 12V RD =1 K C2=0.3f C1=0.37f G D S BFW10 Vo
Specification
VIN i
RG 2.2M
RS 330
CS 100f
RL
10 K
Vout
Vin
D R B
Vout
28
DESIGN: Given VDD = 12V, IDss = 10 mA, VGS =  2V, VP = 6 V For proper biasing: VDD=12 V; VDS = 6 V; VRS = VDD/10 = 1.2V VGS =  0.7 to 2V To find RD : Applying KVL to the output loop of the circuit VDD = VDS + IDRD + VRS 12 = RD (5 x 103 ) + 6 + 1.2 To find RS : RD = 960 1 k ID = IDSS (1VGS/ VP)2 = 10x103 (1 2/6)2 = 4.4 mA 5mA
VRS = ISRS RS = VRS/IS = 1.2 / 5x10 Assume RS = 2 M To find CS : XS = 0.1 Rs = 27 XS = 1/2 fCS Let f = 50 Hz Let C1 = C2 = C XD = 10 RD = 10K XD = 1/2 fC TABULAR COLUMN: Vin = Frequency (Hz) 10 20 . . . . . 1M mV V0 (V) AV AV (dB) therefore C = 0.318f Therefore CS = 100f
3
240 270
AV (db) 3db
f2
V0
RESULT:
30
Ex.No:05
AIM:
Design of Hartley/Colpitts oscillator for a given Radio frequency of f0 =100 KHz using BJT. COMPONENTS REQUIRED:
Sl. No. Components Details Specification Qty
1. 2. 3. 4.
BC109 0.1 f, 1000 pf 47f, 0.0023 f 18K , 1.8K , 3.9K , 4700 1 K Pot 100 H, 1mH, 5mH
THEORY: Oscillators are devices, which generate oscillations. The frequency of oscillations depends on the feedback network. Feedback may be of two types namely positive and negative. In positive feedback, the feedback signal is applied in phase with the input signal thus increasing it. In negative feedback, the feedback signal is applied out of phase with the input thus reducing it. The feedback used in oscillators is positive feedback. The oscillators work on the principle of Barkhausen criteria. This states that for sustained oscillations
i)
ii) The phase shift around the loop must be 0 deg of 360 deg. Here Av is the gain of the amplifier and is the attenuation of the feedback network. Consider the feedback network shown in the fig (1) below. Assume an amplifier with input signal Vin. The output signal VO will be 180 deg out of phase with Vin. So to get an in phase output, the feedback network provides 180deg phase shift. Therefore the output Vf from the feedback network can be made in phase and equal in amplitude to Vin and Vin can be removed. Even then the oscillations continue. Practical oscillations do not need any input signal to start oscillations. They are selfstarting due to thermally produced noise in resistors and other components. Only one frequency (fo) of noise satisfies, Barkhausen
31
criteria and the circuit oscillates with that frequency. The magnitude of fo keeps on increasing each time it goes around the loop. The amplification of fo is limited by circuits own nonlinearities. Therefore to start oscillations Av > 1 and to sustain it, the loop gain Av = 1. Fig 1.
A m p l i f i e r V i n V o
A v
V f
The feedback network used here consists of L and C. Consider the circuit shown below fig 2. This circuit consists of L and C in parallel. The capacitor stores energy in its electric field whenever there is voltage across it and the inductor stores energy in its magnetic field whenever there is current through it. Initially let us assume that the capacitor has charged to V volts. When S is closed c= 0. When S is closed at t = t 0 , capacitor starts charging through the inductor. Thus a voltage gets built up across the inductor due to the change in current through it. If the capacitor was changed with the polarity as shown in the fig 2 the current starts flowing from the positive plate of the capacitor to the negativ4 plate of the capacitor. As shown the voltage across the capacitor reduces during the discharge time v reduces and I increases. At time t1 v will be 0 and I will be maximum as c is fully discharged, the capacitor charges like sinusoidal oscillations. Thus the circuit oscillates with the frequency fo = 1/ 2 LC
S t = t o
Fig.2
L i
+ 
The Hartley oscillator consists of two inductors and a capacitor and Colpitts oscillator consists of two capacitors and an inductor.
32
The resonant frequency fo for Hartley oscillator is fo =1/ 2 LeqC where Leq = L1 + L2. The resonant frequency fo for Colpitts oscillator is fo = 1/ 2 LCeq where Ceq = C1C2/(C1 + C2)
Rc
1.8 K
Cc
0.1 f
VO
CB
0.1 f
BC109
Variable 1 K Pot
3.9K
R2
470
RE
CE
47 f
L1 = 100 H
L2 = 1mH
GND
C = 0.0023 f
33
COLPITTS OSCILLATOR: R1
18K
Vcc = 9 v Rc
1.8 K
Cc
0.1 f
VO
CB
0.1 f
BC109
Variable 1 K Pot
3.9K
R2
470
RE
CE
47 f
C1 = 1000pf
C2 = 1000pf
GND
RE: W.K.T. VRE = VCC / 10 = 9 / 10 = 0.9V for biasing IE IC = 2 mA From the fig. We see that, IERE = VRE RE = 0.9 / (2 x 103 ) = 450 Therefore RE 470 RC: VCE = VCC / 2 = 4.5V  for Q point to be in active region. Applying KVL to output loop VCC ICRCVCE VRE = 0 9 2 x 103 RC 4.5 0.9 = 0 Therefore RC = 1.8k R1 & R2: From biasing circuit VB = VBE+ VRE
Department of Electronics & Communication Engg. CMRIT 34
= 0.7 + 0.9 VB = 1.6V Assume 10 IB flows through R1 and 9 IB flows through R2. W.K.T. IC = IB 2 x 103 = 50 IB Therefore IB = 40 A From the fig. we see that, R1 = VCC VB / 10 IB = 9 1.6 / (10 x 40 x 106 ) = 18.5k Therefore R1 18k R2 = VB / 9IB = 1.6 / ( 9 x 40 x 106 ) = 4.44k Therefore R2 3.9k CE, CC, CB : Let CB = CC = 0.1 F XCE = RE/10 Therefore f = 10 / (2 CE RE) Let f = 100Hz and W.K.T RE = 470 Therefore CE = 10 / 2 f.RE = 34 F Therefore CE 47 F.
35
= XL1 / X
L2
For sustained oscillations Av = 1  Av = 1/ = L2/L1 For oscillations to start Av > 1 Av COLPITTS OSCILLATOR: Attenuation C1/C2 = Vf / Vo = IXC1/IXC2 = XC1/ XC2 = (1/ 2 foC1)/(1/2 foC2) = > L2/L1
For sustained oscillations Av = 1  Av = C1/C2 For oscillations to start Av > 1Av > C1/C2 DESIGN OF TANK CIRCUIT Assume = fo = 100 KHz HARTLEY OSCILLATOR fo = 1/ (2 LeqC) where Leq = L1 + L2. Assume L1 = 100 H, L2 =1mH
LEQ = fO =1/ (2 2*103 C) C = 0.0023 f (Decade capacitance box)
COLPITTS OSCILLATOR fO = 1/ (2 LCeq ) where Ceq = (C1C2)/(C1 + C2) Assume C1 = C2 = 1000 pF Ceq =
36
PROCEDURE: 1.
2.
Before connecting the feedback network, check the circuit for biasing conditions i.e. check VCE, and VRE. 3. After connecting the feedback network. Check the output. 4. Check for the sinusoidal waveform at output. Note down the frequency of the output waveform and check for any deviation from the designed value of the frequency.
5.
6. DCB/DIB can be varied to vary the frequency of the output waveform. TABULAR COLUMN HARTLEY OSCILLATOR SL NO C fo COLPITTS OSCILLATOR SL NO L fo
WAVEFORM:
Vo
37
Ex.No:06
AIM:
CRYSTAL OSCILLATOR
To design a crystal oscillator to oscillate at the specified crystal frequency. COMPONENTS REQUIRED:
Sl. No. Components Details Specification Qty
1. 2. 3. 4.
BC109 0.1 f 47f 18K , 1.8K , 3.9K , 470 1 K Pot 2 MHz or 1.8 MHz
1 No 2 No 1 No Each 1 No 1 No
Vcc = 9 v R1
18K
Rc
1.8 K
Cc
0.1 f
VO
CB
0.1 f
BC109
Variable 1 K Pot
3.9K
R2
470
RE
CE
47 f
38
DESIGN: Given VCC = 9V, IC = 2mA, = 50 RE: W.K.T. VRE = VCC / 10 = 9 / 10 = 0.9V for biasing IE IC = 2 mA From the fig. We see that, IERE = VRE RE = 0.9 / (2 x 103 ) = 450 Therefore RE 470 RC: VCE = VCC / 2 = 4.5V  for Q point to be in active region. Applying KVL to output loop VCC ICRCVCE VRE = 0 9 2 x 103 RC 4.5 0.9 = 0 Therefore RC = 1.8k R1 & R2: From biasing circuit VB = VBE+ VRE = 0.7 + 0.9 VB = 1.6V Assume 10 IB flows through R1 and 9 IB flows through R2. W.K.T. IC = IB 2 x 103 = 50 IB Therefore IB = 40 A From the fig. we see that, R1 = VCC VB / 10 IB = 9 1.6 / (10 x 40 x 106 ) = 18.5k Therefore R1 18k R2 = VB / 9IB = 1.6 / ( 9 x 40 x 106 ) = 4.44k Therefore R2 3.9k CE, CC, CB : Let CB = CC = 0.1 F XCE = RE/10 Therefore f = 10 / (2 CE RE) Let f = 100Hz and W.K.T RE = 470 Therefore CE = 10 / 2 f.RE = 34 F Therefore CE 47 F.
39
PROCEDURE: 1. Rig up the circuit as shown in the circuit diagram. Before connecting the feedback network, check the circuit for biasing conditions i.e. check VCE, and VRE.
2.
3.
4. Check for the sinusoidal waveform at output. Note down the frequency of the output waveform and check for any deviation from the designed value of the frequency.
5.
WAVEFORM:
Vo
40
Ex.No:07
AIM:
Design a circuit, which generates repetitive waveform (Sinusoidal signal) of frequency 7 KHz. COMPONENTS REQUIRED: Sl. No. 1. 2. Components Details Transistor Capacitors SL100 0.02 f 0.1 f 47f 3. Resistors 22K , 4.7K , 1.2K , 330 1 K Pot 470 DC Supply, CRO with Probe THEORY: RC Phase shift oscillator consists of a single transistor amplifier and a RCphase shift network. The Phase shift network consists of three RC sections. Here a fraction of the output of the amplifier is passed through a phase shift network before feeding back to the input. The phase shift in each section is 600 so that the total phase shift is 1800.Another 1800 phase shift is provided by the transistor amplifier and therefore the total phase shift of the oscillator is 360 .The frequency of oscillations is given by fo = 1 / [2 6(RC)] Let us consider a RC circuit.. Let I be the current flowing through both R and C. Then using I as the reference vector,Vo is in phase with I while Vc ,the voltage across the capacitor is 900 behind as shown in the figure. Vi is the sum of Vo and Vc.Hence Vc is degrees ahead of Vi and represents a phase shift of degrees Vo = IR, Vc =IXc Tan =Vc/Vo =Ixc/IR = Xc/R = 1/(2 fCR) Therefore f = 1/(2 fCR Tan ) If there are 3 sections each must give approximately 600 i.e. = 600 Tan =3 =1.73 f= 1/(2 CR3)
Department of Electronics & Communication Engg. CMRIT 41
0
Specification
The above phase discussion ignored the additional current I that flows through C for other sections, so that Vc is actually larger than the value indicated,which means f is smaller. More accurately f = 1/2 6(RC)
D A
C
C 0.02f
C
R 470
470
R2=4.7 K
3
1k
RE=330
CE=47f
DESIGN: Given VCC = 12V, IC = 4mA, = 100. RE: W.K.T. VRE = VCC / 10 = 12 / 10 = 1.2V for biasing IE IC = 4 mA From the fig. We see that, IERE = VRE RE = 1.2 / (4 x 103 ) = 300 Therefore RE 330 RC: VCE = VCC / 2 = 6V  for Q point to be in active region. Applying KVL to output loop VCC ICRCVCE VRE = 0 12 4 x 103 RC 6 1.2 = 0 Therefore RC = 1.2k R1 & R2: From biasing circuit VB = VBE+ VRE = 0.7 + 1.2
Department of Electronics & Communication Engg. CMRIT 42
VB = 1.9V Assume 10 IB flows through R1 and 9 IB flows through R2. W.K.T. IC = IB 4 x 103 = 100 IB Therefore IB = 40 A From the fig. we see that, R1 = VCC VB / 10 IB = 12 1.9 / (10 x 40 x 106 ) = 25.25k Therefore R1 22k R2 = VB / 9IB = 1.9 / ( 9 x 40 x 106 ) = 5.28k Therefore R2 4.7k CE, CC, CB : Let CB = CC = 0.1 F XCE = RE/10 Therefore f = 10 / (2 CE RE) Let f = 100Hz and W.K.T RE = 330 Therefore CE = 10 / 2 f.RE = 48 F Therefore CE 47 F. DESIGN OF TANK CIRCUIT: We know that f=1/(2 RC6) Given fO = 7 KHz Assume C = 0.02 F R = 1/(2 x 0.02 x 106 x 7 x 10+3 x 6) =527 470
PROCEDURE: 1. 2. 3. 4. Make the connections as shown in the circuit diagram. Check the circuit for biasing. Adjust the 1k potentiometer to get sinusoidal waveform at the To measure the phase shift
output. Method 1: Connect the channel 1 of the CRO to point D and channel 2 to point A. We will get two sine waves with a phase difference Measure the difference by converting the time into angle.
43
Method 2: a] Connect channel 1 to point D and channel 2 to point A. Press the XY knob and measure the phase shift. =Sin1 (a/b) (approx.=600)
b a
b a
= Sin1(a/b) Phase angle =1800 (approx. = 1200) C] Connect channel 2 to point C The transfer function will be almost a straight line and =00 and therefore phase angle =1800  00 = 1800
WAVEFORM:
f=1/T
RESULT:
Department of Electronics & Communication Engg. CMRIT 44
Ex.No:08
AIM: To design and test a two stage voltage series feedback amplifier using BJT and to determine gain, frequency response, input and output impedance with and without feedback. COMPONENTS REQUIRED:
Sl. No. Components Details Specification Qty
1. 2. 3. 4.
SL100 0.47 f 10f 12K , 2.7K , 2.2K , 560 4.7 K , 100 1K Pot
DC Supply, Signal Generator, CRO with Probe THEORY: The high gain amplifier is widely used in analog circuit design and will serve as the step to the next higher level of complex analog systems. The philosophy behind the high gain amplifier is based on the concept of feedback. In analog circuits we must be able to precisely define transfer function. A familiar representation of this concept is illustrated in the block diagram below:
xs
+
_ xf
xi
x0
The overall gain of the amplifier with feedback is given by Af = x0 / xs = A / (1 + A ) The high gain amplifier is defined by A = x0 / xi The gains defined above may be current gain or voltage gain. In the circuit shown below, the feedback signal is the voltage Vf across R1 and the sampled signal is the output voltage V0 across R. It is called voltage series feedback amplifier because a part of the output voltage is fed back in series with the input. CIRCUIT DIAGRAM: WITHOUT FEEDBACK
Vcc = 12 v
12K
R1 12K
0.47 f
2.2 K
Rc Cc
R1
2.2 K
Rc Cc
0.47 f
CB
0.47 f
Vo
SL100 Vs
B
2.7K 560
SL100 CE
10 f
2.7K
560
R2
RE
CE
10 f
R2
RE
WITH FEEDBACK
Vcc = 12 v
12K
R1
12K
2.2 K
Rc Cc
R1
2.2 K
Rc Cc
0.47 f
CB
0.47 f 2.7K 560
0.47 f
Vo
10R K
SL100 RE CE
B
2.7K 560
SL100 CE
10 f
Vs
R2
100
R2 RF
RE
46
Vout
Vin
D R B
Vout
= 25.
RE: W.K.T. VRE = VCC / 10 = 12 / 10 = 1.2V for biasing IE IC = 2 mA From the fig. We see that, IERE = VRE RE = 1.2 / (2 x 103 ) RE 560 RC: VCE = VCC / 2 = 6V  for Q point to be in active region. Applying KVL to output loop VCC ICRCVCE VRE = 0 12 2 x 103 RC 6 1.2 = 0 Therefore RC = 2.2k R1 & R2: From biasing circuit VB = VBE+ VRE = 0.7 + 1.2 VB = 1.9V Assume 10 IB flows through R1 and 9 IB flows through R2. W.K.T. IC = IB 2 x 103 = 100 IB Therefore IB = 20 A
47
From the fig. we see that, R1 = VCC VB / 10 IB = 12 1.9 / (10 x 20 x 106 ) Therefore R1 12k R2 = VB / 9IB = 1.9 / ( 9 x 20 x 106 ) R2 2.7k CE, CC, CB : Let CB = CC = 0.1 F XCE = RE/10 Therefore f = 10 / (2 CE RE) Let f = 100Hz and W.K.T RE = 560 Therefore CE = 10 / 2 f.RE = 10 f Therefore CE 10 f. DESIGN FEED BACK CIRCUIT Let = 0.02 = Rf/ Rf + R Rf = R / 1 Let R = 4.7 K Therefore Rf = 100 PROCEDURE: 1. Rig the circuit as shown in the fig.
2. 3.
Check the circuit for biasing i.e. check VDD, VDS and VRS. Give a sinusoidal input of 10kHz from signal generator. Adjust the
amplitude of this sine wave such that the output doesnt get clipped. 4. Observe the output waveform on the CRO. 5. Measure the output voltage using AC milli voltmeter. 6. Measure the output voltage for different frequencies of the input and tabulate the readings as shown in the tabular column. 7. Plot the graph of gain vs frequency on a semilog graph sheet as shown in the fig.
8.
with the signal generator. 9. Measure the voltage at the input point (VS) and at the point after the resistor (Vin).
10. Current
through
the
resistor
is
given
by
the
expression
I = ( VS Vin ) / 47k
11. Input impedance is given by Zin = Vin / 47k Department of Electronics & Communication Engg. CMRIT 48
To measure output impedance connect a DRB in parallel with Adjust all the knobs of the DRB to maximum. Start reducing the resistance in the DRB from a large value The resistance in the DRB is the output impedance.
the output.
TABULAR COLUMN: Without Feedback Vin = constant Frequen cy (Hz) 10 20 . . . . . 1M With Feedback Vin = constant Frequen cy (Hz) 10 20 . . . . . . 1M V0 (V) AV AV (dB) V0 (V) AV AV (dB)
49
EXPECTED GRAPH:
AV
V0
RESULT:
50
Ex.No:09
AIM: To State and verify the thevenins theorem for the given circuit. COMPONENTS REQUIRED:
Sl. No. Components Details Specification Qty
1.
Resistors
1 K
4 Nos.
DC Supply, Multimeter, Ammeter (010)mA THEORY: Any Linear, bilateral network containing energy sources and impedances can be replaced with equivalent circuit consisting of a voltage source in series with an impedance. The Value of voltage source is open circuit voltage between terminals of a network and value of impedance is the impedance measured between the two terminal of a network with all energy sources eliminated. Circuit diagram:
1 k +
R 1 R 3
1 k
R 21
5 v
R L
B
1 k
F I G
1 k +
1 R 21
R 1 R 3
1 k
A +
V o
5 v
R L
1 k
I L
0  1 0 m A
F I G
010mA
1k + 1k
R1 R3
R2
1k
+ +
5v
+
Vo
FIG 3
51
ZTH
010mA A Ith
_
RL 1k
VTH
Supply voltage is adjusted to 5v and the ammeter reading IL is noted down. Open circuit the terminal A & B , Voltmeter reading Vo is measure which is the thevenins voltage. Vo=VTH= ___________Volts .
4. To find the Thevenins impedance, connections are made as shown in the fig (3) 5. The reading of voltmeter V and ammeter I are noted . the thevenins Impedance ZTH=V/I W ZTH=_____________ W 6. Thevenins equivalent circuit connection are made as shown in the fig (4)
7. 8.
The supply voltage is set to Vth as measured above. The ammeter reading Ith is noted. If Ith=IL, Thevenins theorem is verified.
52
(2) MAXIMUM POWER TRANSFER THEOREM: Aim: (i) To state and verify maximum power transfer theorem. (ii) To determine maximum power and the value of RL for Maximum power transfer. COMPONENTS REQUIRED:
Sl. No. Components Details Specification Qty
1.
Resistors
1 K
1 No.
Circuit diagram:
1 k R s 1 0 v + _ +
0  1 0 m A A
R l 0 k p o t
1 k R s 
0  1 0 m A + A I s V s _ + + 1 0 v
53
3. The readings of voltmeter (V) and ammeter (I) are noted down in the table.
4. 5.
RL is decreased in steps and at each steps readings of V and I are tabulated in the table. A graph of RL versus power is plotted, the maximum power Pmax and value of RL for maximum power transfer are noted from graph PMAX =_______W, RL = .
6. To measure source resistance the connection are made as shown in the fig (2) 7. Supply is set to 10V, the ammeter reading I and voltmeter reading are noted down. The source resistance RS=V/I =__________ If RS = RL, MPT Theorem is verified
V (volts)
I mAmps
P = VI in W
RL= V/I
Power , Watts PM X A
RL,
RESULT :
54
Ex.No: 10
Aim : To obtain the frequency response of an RLC series circuit and hence to determine a) Resonance frequency fo b) Band width ,Upper and Lower half power frequency c) Qfactor.
COMPONENTS REQUIRED:
Sl. No. Components Details Specification Qty
1. 2. 3.
100 0.22f 1 mH
Circuit diagram:
C R
VO
DESIGN: fo = 1/2 LC Let L = 1mH C = 1/4 2Lfo2 C = 0.22f R = 100 Find fo Procedure: 1. Connections are made as shown in the circuit diagram. 2. AC Supply is switched on. oscillator output voltage is adjusted to about maximum i.e 10V PP 3. The frequency is gradually varied from zero hertz and for different value of f, voltage is noted down. The results are tabulated in the tabular column. 4. Frequency response i.e a graph of frequency versus voltage is drawn.
55
5. From the graph , resonant frequency fo is noted down at which voltage is maximum(Vo). 6. Lower half power frequency f1 and upper half power frequency f2 are noted corresponding to a voltage of Vo/ 2 Band width=f2f1=_____________ hertz 7. The Qfactor =fo/f2f1
VOmax VOmax/2
BW f1 f0 f2 f, Hz
56
PARALLEL RESONANCE CIRCUIT: Aim : To obtain the frequency response of an RLC series circuit and hence to determine
a) Resonance frequency fo b) Band width ,upper and lower half power frequency c) Qfactor.
COMPONENTS REQUIRED:
Sl. No. Components Details Specification Qty
1. 2. 3.
100 0.22f 1 mH
Circuit diagram:
VO
Frequency response
Vo
Vomin x 2
Vomin BW 0 f1 fO f2 fin Hz
57
Procedure:
1. 2.
Connections are made as shown in the circuit diagram. AC Supply is switched on. oscillator output voltage is adjusted to about maximum i.e 10V PP 3. The frequency is gradually varied from zero hertz and for different value of f, voltage is noted down. The results are tabulated in the tabular column. 4. Frequency response i.e a graph of frequency versus voltage is drawn. 5. From the graph , resonant frequency fo is noted down at which voltage is minimum (Vo). 6. Lower half power frequency f1 and upper half power frequency f2 are noted corresponding to a voltage of VOmin x 2. a. Band width = f2  f1=_____________ Hz 7. The Qfactor =fo/f2f1
RESULT:
58
Ex.No:
AIM:
11
To design and test a Darlington emitter follower circuit with and without boot strapping and determine the gain, input and output impedance for both the circuits. COMPONENTS REQUIRED:
Sl. No. Components Details Specification Qty
1. 2. 3.
THEORY: Normally transistors are used as amplifiers. But there are some applications in which, matching of impedance is required between two circuits without any gain or attenuation. In such applications emitter followers are used. Emitter followers have large input impedance and small output impedance. Darlington emitter follower has two transistors connected in cascade such that the emitter of first transistor is connected to the base of second transistor. The voltage gain of the darlington emitter follower is close to unity. The major drawback of this circuit is that the second transistor amplifies leakage current of the first transistor and overall leakage current becomes high. The output is observed at the emitter terminal of the second transistor. Hence it is called an emitter follower.
59
DESIGN: Given IC = 4mA, VCC = 12V, VBE = 0.6V, To find RE: Applying KVL to the output loop of the second transistor, we get VCC = VCE + VRE Therefore VRE = VCC VCE = 12 6 Therefore VRE = 6V W.K.T RE = VRE / IE2 Here IE2 = IC2 Therefore RE = 6 / 4 x 103 RE = 1.5k
Department of Electronics & Communication Engg. CMRIT 60
1
= 100
To find R1 & R2: From the circuit we have VA = VBE1 + VBE2 + VRE = 0.6 + 0.6 + 6 = 7.2V W.K.T. IC = IB Therefore IB = (4 x 103)/ 100 = 40 A Let 10IB be the current through R1 and 9IB be the current through R2. From the fig. we see that R1 = (VCC VA) / 10IB Therefore R1 = 12K From the fig. R2 = VA / 9IB Therefore R2 = 20 K 22K W.K.T. CC = 10 / XRE = 10 / ( 2. .f.RE) Assume f = 50Hz Therefore CC = 21.2 F 47 F W.K.T. Cb = 10 / XRB = 10 / ( 2. .f.RB ) Therefore Cb = 4.2 F 4.7 F Chose R3 = 10 K , CB = 10f for bootstrapping PROCEDURE: 1. Rig up the circuit as shown in the fig.
2.
where RB = R1  R2 = 7.5k
Check the circuit for biasing, i.e. check VCE, VCC and VRE.
3. Give a sinusoidal input signal of 1KHz from a signal generator. 4. Set the input signal to a value such that the output doesnt get clipped. 5. For different frequencies of the input signal, read the output on the voltmeter and verify that the gain is 1. To measure input impedance, connect a resistor of 47k in series with the signal generator.
6. 7. 8. 9.
Measure the voltage at the input point (VS) and at the point after the resistor (VIN). Current through the I = (VS  VIN) / 47K. resistor is given by the expression
ZIN = VIN / 47 K
10. To measure output impedance, connect a DRB in parallel with the output. 11. Adjust all the knobs of the DRB to maximum. 12. Start reducing the resistance in the DRB from a large value until the output reduces to half.
61
13. The resistance in the DRB is the output impedance. TABULAR COLUMN: VIN = __________ constant Frequency (Hz) V0 (V) AV AV (dB)
WAVEFORM: Vin
Vin
V0
Vin
RESULT:
62
Ex.No:
12
Aim: Testing of a transformer less classB push pull power amplifier and determination of its conversion efficiency. COMPONENTS REQUIRED:
Sl. No. Components Details Specification Qty
1. 2. 3. 4.
SL100 SK100 BY127 47 f 470 f 220 DRB with Probe, Signal generator,
Theory: In class B operation, to obtain output for the full cycle of signal, it is necessary to use two transistors and have each conduct on opposite half cycle, the combined operation providing a full cycle of output signal. Since one part of the circuit pushes the signal high during one half cycle and the other part pulls the signal low during the other half cycle, the circuit is referred to as a push pull circuit.
Circuit diagram:
VCC
Ci
R1
Q1
SL100 CO RL 10 .
Ci Vi=50mV
D1 D2 R2
SK100 Q2
VO
63
12v A
0500A
SL100
SK100
DESIGN: Given Vcc =2.5V; RL= 10 ; IDC = 3mA To Find R1 & R2: Applying KVL at the input circuit; We get ; Vcc = 2VR1 + 1.4 Therefore; VR1 = 0.55V; VR1 =IDCR1 = 0.55V; R1 = 183. Choose; R1 = R2 = 220. To Find Ci : Input coupling capacitor is given by, Xci >Zieff/10 >1.1K/10 Resistance() Xci > 1/2fCi ;Ci >28F; Choose Ci = 47F To Find CO: Output coupling capacitor is given by, Xco = 10 Xco > 1/2fCo Co > 318F; Choose; Co = 470F Poac=Vo2/8RL Pidc=VccIdc Calculate circuit efficiency, = Po (ac)/Pi(dc) = (/4)Vo/Vcc = ? Procedure: 1. Connect the circuit as per the circuit diagram. 2. Set VI = 3V, using the signal generator. 3. Keeping the input voltage constant, vary the load resistor and note down the readings of the ammeter and peak to peak output voltage. 4. Calculate PDC, PAC and % efficiency . 5. Draw the plot of resistance versus output power.
Po (watts)
64
Result:
BIBLIOGRAPHY
1. 2. 3. 4. Electronic devices and circuit theory, Robert L.Boylestad and Louis Nashelsky. Integrated electronics, Jacob Millman and Christos C Halkias. Electronic devices and circuits, David A. Bell. Electronic devices and circuits, G.K.Mittal.
65
VIVAVOCE QUESTIONS
1. What are conductors, insulators, and semiconductors? Give egs. 2. Name different types of semiconductors. 3. What are intrinsic semiconductors and extrinsic semiconductors? 4. How do you get Pwpe and Ntype semiconductors? 5. What is doping? Name different levels of doping. 6. Name different types of Dopants. . 7. What do you understand by Donor and acceptor atoms? 8. What is the other name for ptype and Ntype semiconductors? 9. What are majority carriers and minority carriers? 10. What is the effect of temperature on semiconductors? 11. What is drift current?. 12. What is depletion region or space charge region? 13. What is junction potential or potential barrier in PN junctioI).? 14. What is a diode? Name different types of diodes and name its applications 15. What is biasing? Name different types w.r.t. Diode biasing 16. How does a diode behave in its forward and reverse biased conditions? 17. What is static and dyriantic resistance of diode? 18. Why the current in the fo~ard biased diode takes exponential path? 19. What do you understand 1?y AvaJanche breakdown and zener breakdown? 20. Why diode is called unidirectional device. 21. What is PIV of a diode 22. What is knee voltage or cutin voltage? 23. What do you mean by transition capacitance or space charge capacitor? 24. What do you mean by diffusion capacitance or storage capacitance? 25. What is a transistor? Why is it called so? . 26. Name different types, of transistors? 27. Name different configurations in which the transistor is operated 28. Mention the applications of transistor. Explain how transistor is used as switch 29. What is transistor biasing? Why is it necessary? 30. What are the three different regions in which the transistor works? 31. Why trmisistor is called current controlled device? 32. What is FET? Why it is called so? 33. What are the parameters ofFET? 34. What are the characteristics of FET? 35. Why FET is known as voltage controlled device? 36. What are the differences between BJT and FET? 37. Mention applications ofFET. What is pinch offvQltage, VGS(ofJ) and lDss 38. What is an amplifier? What is the need for an amplifier circuit? 39. How do you classify amplifiers? , 40. What is faithful amplification? How do you achieve this? 41. What is coupling? Name different type.s of coupling 42. What is operating point or quiescent point? 43. What do you mean by frequency response of an amplifier? 44. What are gain, Bandwidth, lower cutoff frequency and upper cutoff frequency? 45. What is the figure of merit of an amplifier circuit? 46. What are the advantages of RC coupled amplifier? 47. Why a 3db point is taken to calculate Bandwidth? 48. What is semilog graph sheet? Why it is used to plot frequency response? 49. How do you test a diode, transistor, FET? 50. How do you identify the tenninals of Diode, Transistor& FET? Mention the type number of the devices used in your lab. Department of Electronics & Communication Engg. CMRIT 66
51. Describe the operation ofNPN transistor. Define reverse saturation current. 52. Explain Doping w.r.t. Three regions of transistor 53. Explain the terms hie/hib, hoelhob, hre/hrb, hre/hfb. 54. Explain thermal run.taway. How it can'be prevented. 55. Define FET parameters and write the relation between them. 56. What are Drain Characteristics and transfer characteristics? 57. Explain the construction and working of FET 58. What is feedback? Name different types. 59. What is the effect of negative feedback on the characteristics of an amplifier? 60. Why common collector amplifier is known as emitter follower circuit? 61. What is the application of emitter follower ckt? 62. What is cascading and cascoding? Why do you cascade the amplifier ckts.? 63. How do you determine the value of capacitor? 64. Write down the diode current equation. 65. Write symbols of various passive and active components 66. How do you determine th~value of resistor by colour code method? 67. What is tolerance and power rating of resistor? 68. Name different types of resistors. 69. How do you c1assify resistors? 70. Name different types of capacitors.. 71. What are clipping circuits? Classify them. 72. Mention the application of clipping circuits. 73. What are clamping circuits? Classify them 74. What is the other name of clamping circuits? 75. Mention the applications of clamping circuits. 76. 'What is Darlington emitter follower circuit? 77. Can we increase the number of transistors in Darlington emitter follower circuit? Justify your answer. 78. What is the different between Darlington emitter follower circuit & Voltage follower circuit using OpAmp. Which is better. 79. Name different types of Emitter follower circuits. 80. What is an Oscillator? Classify them. 81. What ar~ The Blocks, which fonns an Oscillator circuits? 82. What are damped & Undamped Oscillations? 83. What are Barkhausen's criteria? 84. What type of oscillator has got frequency stability? 85. What is the disadvantage of Hartley & Colpiit's Oscillator? 86. Why RC tank Circuit Oscillator is used for AF range? 87. Why LC tank Circuit Oscillator is used for RF range? 88. What type of feedback is used in Oscillator circuit? 89. In a Transistor type No. SL 100 and in Diode BY 127, what does SL and BY stands for 90. Classify Amplifiers based on: operating point selection. 91. What is the efficiency of Class B push pull amplifier? 92. What is the drawback of Class B Push pull Amplifier? How it is eliminated. 93. What is the advantage of having complimentary symmetry push pull amplifier? 94. What is Bootstrapping? What is the advantage of bootstrapping? 95. State Thevenin's Theorem and Max.power transfer theorem. 96. What is the figure of merit of resonance circuit? 97. What is the application of resonant circuit? 98. What is a rectifier? Classify. 99. What is the efficiency of half wave and full wave rectifier? 100. What is the advantage of Bridge rectifier of Centre tapped type FWR Department of Electronics & Communication Engg. CMRIT 67
101. 102. 103. 104. 105. 106. 107. 108. 109. 110. 111.
What is the disadvantage of Bridge rectifier? What is a filter? Name different types of filter ckts. Which type of filter is used in day to day application and why? What is ripple and ripple factor? . What is the theoretical value of ripple for Half Wave and .Full wave rectifier? What is need for rectifier ckts. Why a step down transformer is used at the input of Rectifier ckt. What is TUF? . What is regulation w.r.t rectifier? And how it is calculated? What is figure of merit of Rectifier ckt.
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