RV-VLSI Design Center BE Projects 2012

Digital signature implementation using AES algorithm for secure communication Project Description: A digital signature or digital signature scheme is a mathematical scheme for dem onstrating the authenticity of a digital message or document. A valid digital signature giv es a recipient reason to believe that the message was created by a known sender, and that it wa s not altered in transit. Digital signatures are commonly used for software distribution, fina ncial transactions, and in other cases where it is important to detect forgery or tamp ering. Advanced Encryption Standard (AES) is a specification for the encryption of elec tronic data. It is available in many different encryption packages. AES is based on a design principle known as a Substitution permutation network. It is fast in both software and har dware. Originally called Rijndael, the cipher was developed by two Belgian cryptographe rs, Joan Daemen and Vincent Rijmen, and submitted by them to the AES selection process. AES has a fixed block size of 128 bits and a key size of 128, 192, or 256 bits, whereas Rijndael can be specified with block and key sizes in any multiple of 32 bits, w ith a minimum of 128 bits. The blocksize has a maximum of 256 bits, but the keysize has no the oretical maximum. AES operates on a 44 column-major order matrix of bytes, termed the state (versio ns of Rijndael with a larger block size have additional columns in the state). Most AE S calculations are done in a special finite field. The AES cipher is specified as a number of repetitions of transformation rounds that convert the input plaintext into the final output of ciphertext. Each round consists of several processing steps, including one that depends on the encryption key. A set of rev erse rounds are applied to transform ciphertext back into the original plaintext using the s ame encryption key.

Block diagram : Name Type Description CLK Input Core clock signal EN Input Synchronous enable signal. When LOW the core ignores all its inputs and all its outputs must be ignored. Start Input When goes HIGH, a cryptographic operation is started Load Output Input data request signal Ready Output Output data ready and valid

8-bit Data Interface KEY[7:0] Input Encryption Key PT[7:0] Input Input Plain Text Data CT[7:0]

Output Output Cipher Text Data

Tool Environment: Quartus II, Questa Sim, ALTERA FPGA boards, Cables, PC Scope of Project in Industry/Applications: 1. Communication systems 2. Internet security

Project Stages: 1. 2. 3. 4. 5. Training Algorithm study and development RTL implementation of algorithm and verification Realization on FPGA after RTL is proven. Application for demonstration (depending on time availability)