Beruflich Dokumente
Kultur Dokumente
Design Objectives
Non Overlapping Clock Generator Decoder Shift Registers Signal Driving Circuitry
Verify the functionality of the Circuitry and its ability to program the SRAM. Execute layout techniques that minimize design time and maximize reusability.
Decoders
Decoders
6-Inputs of Decoders
Decoders
6-Inputs by 40 Rows
Drivers
Drivers
40 Rows
Simulation
Simulation
Inputs : 0 0 0 0 0 1
r5 r4 r3 r2 r1 r0 WL1 WL0
WL2
Generate two non overlapping clocks that is imperative to the functionality of the flip flop design being used for the project. Helps in keeping the node voltage stable for correct operation of flip flop
Clock Continued
Propagation delay through both the paths is almost symmetric. This tends to make the rising edge go up later and the falling edge to go down earlier than the opposite clock hence maintaining the property of non overlap. Sizes ( symmetric for both parts).Inverter 1 is before the NAND
Inv 1 Wp 4u Inv 2 8u Inv 3 8u Inv 4 6u NAND 6u
Wn
Length
2u
1u
4u
3u
4u
3u
3u
1.5u
6u
1u
Shift Registers
Used for programming the decoder and selecting the bit line of the SRAM Serial to parallel conversion of the input data. Uses DFF to shift the bits right and Latches to transmit the shifted data in parallel.
DFF
Latch
Simulated with 1aF load first without the driving circuitry to make sure everything was working fine. Tests the non overlapping clock as well. Tests the Shifting action of the registers
Simulation Result
Decoder, Shift registers, Drivers need to drive the decoder ( or bit lines for the SRAM) were all added to the same schematic and connected. Then we said our prayers.
Decoders Layout
Decoders
Drivers
Decoders Layout
Decoder Driver SRAM Cell
NOC Layout
25.5 um X 95.3 um
DFF
Latch
1 SR
TILED SR
QUESTIONS?