Sie sind auf Seite 1von 6

Daniel Roy April 5, 2012 EE 295 007334418 Five Page Research The SDFF Abstract The semi-dynamic flip-flop

p (SDFF) is one of the fastest flip-flops in todays technology based on a hybrid latch theory. Its high-performance and speed make it desirable when designing clock logic. With the SPARC T5 microprocessor in its early stages of development, power dissipation is the main concern. Because clock logic consumes most of a chips power, understanding the SDFF can offer new insight on the design of the SPARC T5. This paper analyzes the power operation of the SDFF in great detail, discusses current research applications, explores a detailed analysis of an existing device, and investigates the ethical issues of the technology.

Introduction The newest microprocessor known as the SPARC T5 is currently being designed to be one of the fastest and highest performing chips in todays technology. Unlike our previous models, the SPARC T5 is being designed with power as the primary design constraint. The clock logic within the chip is the main cause of the power being dissipated. As research suggests, semi-dynamic flip-flops used to drive the clock logic to different areas of the chip can be altered to decrease the power consumption by a fourth [1]. By understanding the operation of the SDFF and the power dissipated, our company can effectively design a method to alter the clock logic that will allow the SPARC T5 to use as little power as possible.

-1-

Experienced engineers have realized the fact that hybrid based flip-flops dissipate too much power and have implemented and tested different methods to fix this problem. One issue is associated with the clock transitions from high-to-low and low-to-high, which produce static hazards. Different strategies suggest adding delay blocks to the design to avoid such glitches [2]. Another concern is the semi-dynamic flip-flop needs to overpower two keepers in order to change the state of the SDFF, using unnecessary power. Engineers propose to modify the keeper nearest to the output [3]. Finally, many methods focus on reducing power consumption that results from unnecessary transitions in the entire circuit. This is done by employing a feedback path that uses the state of the circuit to prevent precharging of the internal node when it is redundant and reduces power consumption associated with the pre-charge phase [4]. Even with certain power issues, the SDFF can be found in applications such as microprocessors and sensors. Research has been done and continues to grow because devices are becoming smaller and require low power. Exploring the power operation of the SDFF in great detail allows us to better understand where power can be saved.

State of the Art SDFF Operation With the predominance of mobile devices, power consumption has become a major concern for design engineers. Power consumption within hybrid based flip-flops has emerged as one of the most exciting research areas due largely because of their high performance and speed. By improving the power, these flip-flops are ideal for any design using clock logic. With the semi-dynamic flip-flop, detailed research has been done to understand where the most power is lost during operation.

-2-

SDFF operation falls into the category of a pulsed hybrid latch. To begin, the locking mechanism is a small window of time where the clock edge can become active and a change in the state of the SDFF is allowed [5]. If the input is at a high logic level during this period, the internal signal nearest to the NAND gate will fall, which forces the output to a high level. However, if the flip-flop input is low during this window, the internal signal will remain at a low level and force the output to a low. Although this feature ensures a small delay, a static-one hazard will occur at the output if both the input and output are at a logic high level [6]. This glitch results in unnecessary additional power consumption. Another important issue is the use of the keepers. The keeper is used to hold the state of the SDFF if no change occurs on the input. The problem with power occurs when the value of the keeper needs to be altered. In order to change the state of the SDFF, two keepers have to be overpowered. With pass-transistor logic, the flip-flop has to have certain minimal driving capability. Two keepers are used to ensure this specification is met. The keepers consume a large portion of power in order to change the output of the SDFF [6]. However, many researchers have investigated a topology where two keepers are not needed. In this design, the output keeper remains the same and the internal keeper is removed. The output keeper should turn on only when the clock is on low level, which is accomplished by proper selection of delayed clock signals for a tri-state control of the keeper [7]. Although the use of this topology eliminates the problem of overpowering two keepers, a possible hazardous situation should be noted. After the clock makes a transition to a low logic level, it is not clear which of the control signals of the second stage will change first, resulting in a race condition and sending the output to ground for a short

-3-

period of time [8]. Even though there is only a small window of uncertainty, the second topology discussed should be used when power is of main concern and reliability is not as important. Explicit presence of the transparency window mentioned earlier gives rise to another issue known as soft-clock edge property. The transparency window allows the use of a simpler latch structure in the second stage and gives the circuit robustness in exchange for uncertainty of the clock arrival [9]. One of the main reasons for this is high internal activity of the circuit even when input activity is small. These unnecessary transitions that occur internally contribute a large amount to the total power dissipation because static power is lost when the transistors are constantly switching their outputs to different values.

Current SDFF Research Applications Because of its speed, the semi-dynamic flip-flop can be found in many applications that focus entirely on delay. Some of these applications include microprocessors, highspeed sensors, frequency dividers, and comparators [10]. The advantage of the SDFF design is that it provides a way to incorporate a stage of dynamic logic into an otherwise fully-static design. It can also be extended to add additional dynamic logic stages after the first stage. This solves many issues related to clock logic. It makes routing the clock to the entire chip easier and more effective while keeping the integrity of the entire circuit [11]. Research of the SDFF has allowed engineers to alter the design to meet specific power needs for smaller devices. This allows for completely new technology. For example, companies can now build smaller devices with faster microprocessors than before, while keeping the performance of the device nearly the same. Problems with speed and

-4-

performance of the clock logic in smaller technologies can be fixed with a low-power SDFF. Sensors in smart phones react faster without dissipating too much heat from being overpowered. Microprocessors are as fast as before, but require less cooling equipment. Our interest, on the other hand, lends itself to mobile devices. Sun Microsystems produces one of the fastest microprocessors in todays market, but these chips are only usable in high end computers, such as supercomputers. Research shows that by changing our design of the SDFF in the new SPARC T5 microprocessor, the chip can be used in mobile devices, which include smart phones and laptops. To ensure the highest quality, reliability, and system performance, future designs will use an increasingly sophisticated collection of special features for test, debug, and chip optimization. Tomorrows latch and flip-flop designers will need to consider not only the usual speed and performance aspects of their solutions, but will also need to design for enhanced robustness and low power dissipation. Because clock logic consumes most of the power within a chip, the SDFF becomes of great concern when dealing with low power constraints. This makes research highly valuable in order to create a design that maintains the advantages of the SDFF, but also improves the power issues.

References [1] C. Tsai, P. Huang, W. Hwang. Low Power Pulsed Edge-Triggered Latches Design, Department of Electronics Engineering and Institute of Electronics. 2006.

-5-

[2] N. Nedovic, V. Oklobdzija. Hybrid Latch Flip-Flop with Improved Power Efficiency, Department of Electrical and Computer Engineering: UC Davis. 2004. [3] N. Nedovic, V. Oklobdzija. Dynamic Flip-Flop with Improved Power, Department of Electrical and Computer Engineering: UC Davis. 2006. [4] S. Rasouli, A. Kusha, A. Zadeh, M. Nourani. Double Edge Triggered Modified Hybrid Latch Flip-Flop (DMHLFF), Iran Telecommunication Research Center (ITRC). vol. 34, pp. 536-548, Apr. 2007. [5] B. Diniz, D. Guedes, W. Meira, R. Bianchini. Limiting the Power Consumption of Main Memory, Federal University of Minas Gerais, Brazil; Rutgers University. 2002. [6] A. Seyedi, A. Amirabadi. Double Edge Triggered Feedback Flip-Flop in Sub 100NM Technology, Nanoelectronics Center of Excellence. 2001. [7] C. Chin. Hybrid Techniques Reduce Dynamic Power Consumption, Synopsys, Inc. July 2010. [8] F. Klass. Semi-Dynamic and Dynamic Flip-Flops with Embedded Logic, Digest of Technical Papers. June 2008. [9] H. Partovi. Flow-through latch and edge-triggered flip-flop hybrid elements, IEEE International Solid-State Circuits Conference Digest of Technical Papers. Feb. 2006. [10] K. Cheng. Y. Lin. A Dual-Pulse-Clock Double Edge Triggered Flip-Flop For Low Voltage and High Speed Application, ISCAS. pp. 425-428 vol. 5. June 2010. [11] E. Napoli. D. Caro. A. Strollo. New Clock Gating Techniques for Low-Power FlipFlops, ISLPED. 2000.

-6-