IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO.

1, JANUARY 2011

29

Interleaved Active-Clamping Converter With ZVS/ZCS Features

Tsun-Hsiao Hsia, Hsien-Yi Tsai, Dan Chen, Fellow, IEEE, Martin Lee, and Chun-Shih Huang, Student Member, IEEE

AbstractIn this paper, an interleaved soft-switching dc-to-dc converter conguration is proposed. It consists of two parts: the primary side is a constant-frequency asymmetrical converter with active-clamp feature and the secondary side is a series-resonant tank circuit. The active-clamp circuit recycles the energy stored in the magnetizing inductance of transformer to allow main/auxiliary switches turn-ON at zero-voltage switching and clamps the voltage stress of the main switches. Series-resonant tank circuit employs the transformer leakage inductance and secondary resonant capacitance to achieve zero-current switching of the output diodes. The circuit features constant-frequency operation and soft switching for both the transistors and the diodes. Interleaving operation of this conguration combines the aforementioned benets and small output capacitor. Theoretical analysis and computer simulation of the converter were given. An 80-KHz 500-W experimental circuit of the proposed converter was demonstrated. Index TermsActive-clamping converter, interleave, zerocurrent switching (ZCS), zero-voltage switching (ZVS).

Fig. 1.

ZVS/ZCS active-clamping converter.

I. INTRODUCTION

HE REQUIREMENTS for power supplies of plasma display panels (PDPs) are high-power density, high efciency, and low electromagnetic interference (EMI) [1], [2]. To meet the requirements, a high-frequency converter with soft-switching technology is often necessary [3][5]. For such an application, the power level often ranges from 200 to 500 W. Therefore, two-transistor power converters with soft-switching capabilities are normally considered, sometimes along with paralleling or interleaving arrangement. A conventional active-clamped forward converter belongs to this type of converter [2], [6]. By utilizing transformers leakage inductor and magnetizing inductance, zero-voltage switching (ZVS) can be achieved for the MOSFET switches in the primary side of the converter. But the reverse-recovery problem of output diodes still exists in this topology. A conventional active-clamped yback converter falls

into similar category and performances [7], [8]. More recently, LLC type of converter was reported in which soft switching can be achieved for the switches in both sides of the transformer, ZVS for the MOSFETs in the primary side and zero-current switching (ZCS) for the output diodes in the secondary side [9], [10]. However, variable switching frequency is necessary to achieve output voltage regulation in this type of converter. In this paper, an active-clamped converter with ZVS/ZCS features is proposed. Similar to an LLC converter, the proposed conguration features ZVS for the MOSFET switches and ZCS for the output diodes, but the output voltage regulation can be achieved by constant switching-frequency control. In this paper, a description of the circuit will be rst given along with a qualitative comparison with other comparable converter types. A description of the circuit operation and the waveform will then be given for both the noninterleaved and the interleaved operations. Then, design equations and considerations will be given. Experimental results will then be presented for a 500-W experimental circuit.

II. ACTIVE-CLAMPED CONVERTER WITH ZVS/ZCS FEATURES Fig. 1 shows the circuit diagram of the proposed ZVS/ZCS active-clamped converter (ACZVS/ZCS) conguration, where Lm is the magnetizing inductor of the transformer, Cc is the clamp capacitor, Lr is the leakage inductor of the transformer, and Cr is the resonant capacitor. The clamp capacitor Cc and auxiliary switch S1A form the active-clamp circuit that accomplishes ZVS switching of the main/auxiliary switches S1 and S1A at turn-ON and clamps the voltage of S1 . Leakage inductor Lr and resonant capacitor Cr form the resonant circuit that causes ZCS turn-OFF of the output diodes. This avoids the problem of diode reverse recovery. Table I summarizes a qualitative performance comparison of the proposed ACZVS/ZCS conguration with other twotransistor soft-switching converter congurations.

Manuscript received November 27, 2009; revised March 13, 2010 and April 23, 2010; accepted May 15, 2010. Date of current version December 27, 2010. This work was supported by the Taiwans National Science Council Research Grant to Taiwan University under Grant NSC-98-2221-E-002-191-MY2. This paper was presented in part at the International Power Electronics Conference (IPEC), Sapporo Japan, July 2124, 2010. Recommended for publication by Associate Editor M. Vitelli. T.-H. Hsia, H.-Y. Tsai, D. Chen, and C.-S. Huang are with the Department of Electrical Engineering, National Taiwan University, Taipei 106, Taiwan (e-mail: d93921011@ntu.edu.tw; d94921011@ntu.edu.tw; chend@cc.ee.ntu.edu.tw; f93921145@ntu.edu.tw). M. Lee is with the Chicony Power Technology Corporation, Ltd., Taipei 248, Taiwan (e-mail: martin_lee@chiconypower.com.tw). Color versions of one or more of the gures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identier 10.1109/TPEL.2010.2051456

0885-8993/$26.00 2010 IEEE

30

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 1, JANUARY 2011

TABLE I SIMPLE PERFORMANCE COMPARISON

Fig. 2.

Interleaved active-clamping converter with ZVS/ZCS circuit.

In all the four congurations, ZVS switching can be achieved for the MOSFET switches in the primary side, but only LLC converter and the proposed ACZVS/ZCS conguration can also achieve ZCS operation of the diodes in the secondary side. Because there is no output lter inductor in the circuit plus the fact that the resonant inductor can be built as the leakage inductance of the transformer, both ACZVS/ZCS and LLC have an overall size advantage. But also because of no lter inductor used, large output capacitance is often needed to reduce the output voltage ripple in a noninterleaved conguration. Therefore, interleaving these two congurations makes good sense because this combines the earlier mentioned benets while keeping the capacitor ripple current small, which often means small capacitor requirement. Between the LLC and the ACZVS/ZCS, however, the latter has the advantage of constant-frequency operation for the same output voltage regulation. Therefore, an interleaved ACZVS/ZCS converter conguration was proposed and is the focus of this paper. Fig. 2 shows the circuit diagram of such a converter. A. Principle of Operation In this section, a description of the detailed operation of the basic noninterleaved ACZVS/ZCS converter will be given rst.

An interleaved operation will then be described. To simplify the analysis process, assumptions made in the analysis are listed, which are as follows. 1) The switching-frequency ripple is much smaller than the dc value of the output capacitor. 2) All components are ideal with the exception of the transformer and the MOSFETs. The transformer has a nite magnetizing inductance Lm and leakage inductance Lr , and the MOSFETs have nonzero parasitic drain-to-source capacitances (Cos1 and Cos1A ) and body diodes (DS 1 and DS 1 A ). 3) There is a dead time between the turn-ON signal of the main switch and the auxiliary switch. 4) The switching frequency is much higher than the resonant frequency of the tank circuit consisting of magnetizing inductor Lm and the clamp capacitor Cc . Therefore, the clamp-capacitor voltage VC c is a constant value. 1) Description of Basic Noninterleaved ACZVS/ZCS Converter: Based on the switching state of the main/auxiliary switch and the output diodes, the operation of ACZVS/ZCS converter can be separated into six stages in one complete period. The equivalent circuits and the waveforms of key components are shown in Figs. 3 and 4, respectively. In the description and the equations to follow, the capital-case variables are dc values and the lower-case variables are instantaneous values. Stage 1 [t0 t1 ]: Auxiliary switch S1A is OFF, output diode D1 is ON, output diode D2 is OFF, and the direction of primary current iP 1 and main switch current ids1 are negative at the time t0 . Therefore, main switch S1 can be turned on with zero-voltage switching. The resonant circuit of inductor Lr and capacitor Cr start working and Cr is charged. The variation of iP 1 is larger than the change of magnetizing inductor current iL m by resonant current iL r . Input power will transfer to output side through transformer, Lr and Cr . The current of magnetizing inductor will increase linearly and the function is shown as follows: Lm diL m (t) Vin = Vin iL m (t) = iL m (t = t0 ) + (t t0 ). dt Lm (1)

HSIA et al.: INTERLEAVED ACTIVE-CLAMPING CONVERTER WITH ZVS/ZCS FEATURES

31

Fig. 3. Operating stages of noninterleaved operation. (a) Stage 1 [t0 t1 ]. (b) Stage 2 [t1 t2 ]. (c) Stage 3 [t2 t3 ]. (d) Stage 4 [t3 t4 ]. (e) Stage 5 [t4 t5 ]. (f) Stage 6 [t5 t0 ].

The inductor Lr current and capacitor Cr voltage are as follows: n Vin Vo VC r (t = t0 ) sin(r (t t0 )) (2) iL r (t) = Lr /Cr vC r (t) = (Vo n Vin + VC r (t = t0 )) cos(r (t t0 )) (3) where the resonant frequency is r = 1 Lr Cr . The resonant current iL r declines to zero during resonant period, which cause D1 turning off with ZVS. When D1 turns off at the time t1 , the operation enters next stage. Stage 2 [t1 t2 ]: Because output diodes are OFF, no current ows at secondary side of transformer. The main transformer transfers no power to the output side, so the transformer works like an inductor Lm . The magnetizing inductor current iL m increases with the same slope as in Stage 1 iL m (t) = iL m (t = t1 ) + Vin (t t1 ). Lm (4) + (n Vin Vo )

body diode DS 1 A of auxiliary switch conducts at time t3 . Then, S1A can be turned on with ZVS after the body diode turn on. The value of iL m is the decisive factor of auxiliary-switch soft switching at this stage. Stage 4 [t3 t4 ]: When DS 1 A and S1A turn on at zerovoltage switching, D2 conducts and the secondary-side resonant tank (Lr and Cr ) starts working again. Because the resonant frequency of Lm and Cc is smaller than the switching frequency, the voltage on Lm is the clamp-capacitor voltage and this makes iL m to decrease linearly iL m (t) = iL m (t = t3 ) VC c (t t3 ). Lm (5)

The clamp capacitor Cc discharges to reach voltage balance and make iL r to be negative. As the same reason in Stage 1, the value of iL r will be a sine wave to reach zero. Relationship of resonant tank at this stage is listed as follows: iL r (t) = n VC c VC r (t = t3 ) Lr /Cr sin(r (t t3 )) (6)

The length of this stage time affects efciency. The efciency becomes worse if the time length of the stage is longer. When S1 turns off at t2 , the operation goes into Stage 3. Stage 3 [t2 t3 ]: When S1 is OFF, iL m charges the parasitic capacitors Cos1 of the main switch. The voltage summation of clamp capacitor Cc and parasitic capacitors of main/auxiliary switch is equal to the input voltage. The parasitic capacitor Cos1A of auxiliary switch discharges and the clamp-capacitor voltage charges, because the voltage stress of S1 is increased. Compared with the variation of the main/auxiliary switch voltage stress, the change of clamp-capacitor voltage is very small. Therefore, the clamp-capacitor voltage could be set to a constant value at this stage. When the voltage of S1 increases to the sum of the clamp-capacitor voltage and the input voltage, the

vC r (t) = (VC r (t = t3 ) n VC c ) cos(r (t t3 )) + n VC c (7) D2 will turn off at zero-current switching at iL r to reach zero at the time t4 . And then, the circuit operation goes into Stage 5 at D2 turn-OFF. Stage 5 [t4 t5 ]: S1A is still ON. The voltage on Lm is still negative and it is equal to the clamp-capacitor voltage. The magnetizing inductor current iL m is still declining to reach magnetic ux balance. The function of iL m is shown, in (8), as follows: iL m (t) = iL m (t = t5 ) VC c (t t5 ). Lm (8)

32

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 1, JANUARY 2011

Fig. 4.

Key waveform of ACZVS/ZCS converter without interleaved model.

S1A turns off at time instant t5 and operation enters Stage 6. Stage 6 [t5 t6 ]: When S1A is turned off at time t5 , iL m starts to charge Cos1A and discharges Cc and Cos1 . The voltage relationships are shown, in (9), as follows: Cds1 dvds1 (t)/dt Cds1A dvds1A (t)/dt iL m (t = t5 ) v (t) + vds1A (t) Vin + VC c (t = t5 ) = V1 ds1 Vds1 (t = t5 ) = V1 , Vds1A (t = t5 ) = 0. (9) The voltage of parasitic capacitors of main switch declines to zero, and then, the body diode DS 1 of the main switch turns on. Therefore, D1 will be ON and resonance starts in the secondary side. S1 can be turned on with zero-voltage switching because DS 1 is at ON-state. When S1 turns on at time instant t6 , the operation enters Stage 1 and repeats the cycle. 2) Description of Interleaved ACZVS/ZCS Converter: In the operation analysis of ACZVS/ZCS converter, the voltage

and ripple current at output side will be larger because input power only transfers energy to output side at Stage 1. This problem could be solved by interleaved model. Interleaved active-clamping converter with ZVS/ZCS circuit includes two ACZVS/ZCS converters and the interleaved model is operated by an asymmetrical pulsewidth modulation (PWM) method with phase shift. Based on the operation analysis of ACZVS/ZCS converter, the operation of ACZVS/ZCS converter with interleaved model can be separated into 12 stages in one period and the simple operation analysis will be provided, as next. The stage circuits and the waveforms of key components of interleaved active-clamping converter with ZVS/ZCS circuit are shown in Figs. 5 and 6. Stage 1 [t0 t1 ]: Main switch S1 is turned on with ZVS. The input power is transferred to the output side through the transformer, resonant inductor Lr 1 , and resonant capacitor Cr 1 of the top converter. The operation then goes to the next stage when output diode D4 cuts off with ZCS at time t1 . Stage 2 [t1 t2 ]: Both S1 and auxiliary switch S2A are ON. The input power is still transferred to the output side by the top converter. The operation enters next stage when D1 cuts off with ZCS at time t2 . Stage 3 [t2 t3 ]: Because all output diodes are OFF, no power is transferred to output side and the operation goes into Stage 4 when S1 turns off. Stage 4 [t3 t4 ]: When S1 is turned off at time t3 , the clamp capacitor Cc1 , parasitic capacitors Cos1 and Cos1A , and main inductor Lm 1 cause a resonance to force the conduction of the body diodes of auxiliary switch S1A so that ZVS turn-ON can be achieved. When S1A is turned on at time t4 , resonance in the secondary side starts and the operation enters next stage. Stage 5 [t4 t5 ]: When S1A is turned on at the time t4 , Lr 1 and Cr 1 cause a resonance to force D2 turn-ON. When S2A is turned off at time t5 , the operation enters Stage 6. Stage 6 [t5 t6 ]: When S2A is turned off at time t5 , the clamp capacitor Cc2 , parasitic capacitors Cos2 and Cos2A , and main inductor Lm 2 cause a resonance to force the conduction of the body diodes of main switch S2 so that ZVS turn-ON can be achieved and makes output diode D3 turn-ON. When S2 is turned on at time t6 , the operation enters next stage. Stage 7 [t6 t7 ]: S2 is turned on with ZVS. The input power is transferred to output side through the transformer, resonant inductor Lr 2 , and resonant capacitor Cr 2 of the bottom converter. The operation then enters next stage when D2 cuts off with ZCS at time t7 . Stage 8 [t7 t8 ]: S2 and S1 A are both ON. The input power is still transferred to the output side by the bottom converter. The operation enters next stage when output diode D3 cuts off with ZCS at time t8 . Stage 9 [t8 t9 ]: Because all output diodes are OFF, no power is transferred to output side and the operation enters Stage 10 when S2 is turned on. Stage 10 [t9 t10 ]: When S2 is turned off at t9 , Cc2 , Cos2 , Cos2A , and Lm 2 cause a resonance to force the conduction of the body diodes of S2A so that ZVS turn-ON can be achieved. When S2A is turned on at time t10 , resonance in the secondary side starts and the operation enters next stage.

HSIA et al.: INTERLEAVED ACTIVE-CLAMPING CONVERTER WITH ZVS/ZCS FEATURES

33

Fig. 6.

Key waveform of interleaved ACZVS/ZCS converter.

force the conduction of the body diodes of S1 so that ZVS turnON can be achieved and forces D1 ON. When S1 is turned on at t12 , the operation enters Stage 1 again and repeats. In the interleaved operation, the total output power is provided twice a cycle, by each one converter separately. This can be seen clearly from the diode sum current isum waveform in Fig. 6. It is a full-wave rectied waveform, while the counterpart of the noninterleaved operation is a half-wave rectied waveform. For the same output power level, the interleaved operation gives signicantly smaller capacitor ripple rms current and the output ripple voltage. III. DESIGN CONSIDERATIONS A. Steady-State Relationship
Fig. 5. Operating stages of interleaved operation. (a) Stage 1 [t0 t1 ]. (b) Stage 2 [t1 t2 ]. (c) Stage 3 [t2 t3 ]. (d) Stage 4 [t3 t4 ]. (e) Stage 5 [t4 t5 ]. (f) Stage 6 [t5 t6 ]. (g) Stage 7 [t6 t7 ]. (h) Stage 8 [t7 t8 ]. (i) Stage 9 [t8 t9 ]. (j) Stage 10 [t9 t1 0 ]. (k) Stage 11 [t1 0 t1 1 ]. (l) Stage 12 [t1 1 t1 2 ].

Because the PWM switching frequency fS is sufciently larger than resonant frequency of magnetizing inductor Lm and the clamp capacitor Cc , the average voltage of Cc in one switching period can be calculated by magnetic ux balance of magnetizing inductor Vin (t2 t0 ) VC c (t5 t3 ) = 0 Vin DTS VC c (1 D) (10) VC c = DVin 1D (11)

Stage 11 [t10 t11 ]: When S2A is turned on at time t10 , Lr 2 and Cr 2 cause a resonance to force D4 ON. When S1A is turned off at time t11 , the operation enters Stage 12. Stage 12 [t11 t12 ]: When S1A is turned off at t11 , the three capacitances Cc 1 , Cos1 , Cos 1A , and Lm 1 cause a resonance to

34

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 1, JANUARY 2011

where D is the duty cycle of the main switch S1 and TS is the switching period. At secondary side point of view, the average voltage of the resonant capacitor Cr can be calculated by magnetic ux balance of main transformer VC r
avg

TABLE II PARAMETERS OF EXPERIMENTAL CIRCUIT

DnVin n2 Lm + Lr . (1 D) n2 Lm

(12)

In the average mode of ACZVS/ZCS converter, the relationship between the input voltage and the output voltage can be found as follows: Vo = nVin n2 Lm + Lr (1 D) n2 Lm . (13)

Because the average currents of resonant inductor Lr and auxiliary switch S1A are zero in one switching period based on the law of the conservation of energy, the average current of magnetizing inductor Lm is equal to input average current Iin as follows: IL m = n2 Lm + Lr (Io /N ) nLm (1 D) (14)

where N is the number of interleaved phase. B. Magnetizing Inductor Design To meet the ZVS condition of the main switch S1 , (15) must be met. This is obtained from energy consideration iL m o n > 2IL m and (15) 1 2 1 L i2 m L m ,m in > Cos vds,m ax 2 2 where iL m on is the magnetizing inductor ripple current. From (14) and the relationship between inductor ripple current and voltage, (16) can be obtained Lm < DVin (1 D) Lr 2. 2nfS (Io /N ) n (16)

C. Selection of Clamp Capacitor (Cc ) Value The switching frequency should be much larger than the resonant frequency of Lm and Cc in order to maintain a constant VC c for proper clamping action fS 1 Cc Lm Cc 1 . Lm (fS )2 (17)
Fig. 7. (a) Simulation result. (b) Measurement result. CH1: driver signal v g s 1 , CH2: voltage stress v d s 1 , CH3: driver signal v g s 1 A , and CH4: voltage stress vd s 1 A .

dened as follows: (Io /N ) 2fS k3 VC r avg (19) where k3 can be set according to the allowable ripple voltage to dc-voltage percentage of Cr . Based on (18) and (19), the value of Lr could be found. vC r =
avg

D. Secondary Resonant Tank (Lr , Cr ) Design The half period of resonant tank should be less than the time of S1 at ON-stage because output diodes need to reach zerocurrent switch. Relationship could be shown as follows: Lr Cr D fS
2

(Io /N ) TS k3 VC r 2Cr

Cr

(18)

IV. EXPERIMENT RESULTS A prototype of the proposed interleaved ACZVS/ZCS converter was built. A PWM IC (UCC3895) was used as the controller to provide constant-frequency gate-drive signals to all switches to regulate the output voltage. The circuit

The voltage of Cr will affect the ripple voltage of output side. Therefore, the value of resonant tank will be designed by peakto-peak voltage of Cr . From (12), the limitation of Cr could be

HSIA et al.: INTERLEAVED ACTIVE-CLAMPING CONVERTER WITH ZVS/ZCS FEATURES

35

Fig. 8. (a) Simulation result. (b) Measurement result. CH1: driver signal v g s 1 , CH2: switch current id s 1 , CH3: driver signal v g s 1 A , and CH4: switch current id s 1 A .

Fig. 10. (a) Simulation result. (b) Measurement result. CH1: driver signal v g s 1 , CH2: diode current iD 1 , CH3: diode current iD 3 , and CH4: resultant diode current isu m .

Fig. 9. (a) Simulation result. (b) Measurement result. CH1: driver signal v g s 1 , CH2: resonant current iL r 1 , CH3: diode current iD 2 , and CH4: diode current iD 1 .

parameters and the operating conditions are listed in Table II. Figs. 7(b) and 8(b) show the measured waveforms of drain-tosource voltage (vds1 , vds1A ) and drain current (ids1 , ids1A ) of the main/auxiliary switches. Simulated waveforms were also included for comparison. Fig. 9 shows both the measured and simulated waveforms of the resonant current iL r 1 and the output diode current (iD 2 , iD 1 ). Fig. 10 shows the waveforms of gate voltage vg s1 , diode currents iD 1 , iD 3 and the resultant diode summation current isum at full load. From the waveforms of Figs. 7 and 10, one can see that the switch current ows through the body diode of the main/auxiliary switch before the gate turn-ON signal is applied, and therefore, achieving zerovoltage switching. And the output diodes are turned off with zero-current switching. Fig. 11 shows the measured efciency curve of the prototype. The efciency was measured by using a digital power meter (WT210/YOKOGAWA). Comparisons were made between interleaved operation and paralleled operation of the same power circuit prototype. Some results obtained were based on measurements and some were based on simulations. From the waveform comparison shown in Figs. 710, one can see that simulation waveforms were close to measurement waveforms that give condence of simulation results. The measurement results indicated that interleaving improves the efciency, compared to paralleling operation, by about 0.2% to 0.3% point under full-load condition of

36

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 1, JANUARY 2011

be seen from Fig. 12(c), the capacitor size needs to be doubled in the paralleled operation to match the output ripple voltage performance of the interleaved operation. V. CONCLUSION A novel interleaved ACZVS/ZCS converter conguration was proposed and demonstrated. It features soft switching for both the MOSFETs and the output rectier diodes and can be operated at constant switching frequency to achieve output voltage regulation. It is believed that this conguration is particularly useful for applications where efciency, EMI, and size are important concerns. For future research, synchronous rectiers can be considered for the output rectiers to further improve the efciency. ACKNOWLEDGMENT The authors would like to thank SIMPLIS Technologies, Inc., for supplying SIMPLIS simulation tool, Prof. B.-R. Lin of National Yunlin University of Science and Technology for his insightful suggestion, and Chicony Power Technology, Taiwan, for supplying parts and fabricating experimental prototype. REFERENCES
[1] W.-J. Lee, S.-W. Choi, C.-E. Kim, and G.-W. Moon, A new PWMcontrolled quasi-resonant converter for a high efciency PDP sustaining power module, IEEE Trans. Power Electron., vol. 23, no. 4, pp. 1782 1790, Jul. 2008. [2] S.-K. Han, T.-S. Kim, G.-W. Moon, and M.-J. Youn, High efciency active clamp forward converter for sustaining power module of plasma display panel, IEEE Trans. Ind. Electron., vol. 55, no. 4, pp. 18741876, Apr. 2008. [3] B.-R. Lin and C.-H. Tseng, Analysis of parallel-connected asymmetrical soft-switching converter, IEEE Trans. Ind. Electron., vol. 54, no. 3, pp. 16421653, Jun. 2007. [4] P. K. Jain, A. St-Martin, and G. Edwards, Asymmetrical pulse-width modulated resonant dc/dc converter topologies, IEEE Trans. Power Electron., vol. 11, no. 3, pp. 413422, May 1996. [5] H. Mao, J. Abu-Qahouq, S. Luo, and I. Batarseh, Zero-voltageswitching half-bridge DC-DC converter with modied PWM control method, IEEE Trans. Power Electron., vol. 19, no. 4, pp. 947958, Jul. 2004. [6] Q. M. Li and F. C. Lee, Design consideration of the active-clamp forward converter with current mode control during large-signal transient, IEEE Trans. Power Electron., vol. 18, no. 4, pp. 958965, Jul. 2003. [7] R. Watson, F. C. Lee, and G. C. Hua, Utilization of an active-clamp circuit to achieve soft switching in yback converters, IEEE Trans. Power Electron., vol. 11, no. 1, pp. 162169, Jan. 1996. [8] Y.-K. Lo and J.-Y. Lin, Active-clamping ZVS yback converter employing two transformers, IEEE Trans. Power Electron., vol. 22, no. 6, pp. 24162423, Nov. 2007. [9] X. Xie, J. Zhang, C. Zhao, Z. Zhao, and Z. Qian, Analysis and optimization of LLC resonant converter with a novel over-current protection circuit, IEEE Trans. Power Electron., vol. 22, no. 2, pp. 435443, Mar. 2007. [10] H. D. Groot, E. Janssen, R. Pagano, and K. Schetters, Design of a 1-MHz LLC resonant converter based on a DSP-driven SOI half-bridge power MOS module, IEEE Trans. Power Electron., vol. 22, no. 6, pp. 2307 2320, Nov. 2007. [11] J.-J. Lee, J.-M. Kwon, E.-H. Kim, and B.-H. Kwon, Dual series-resonant active-clamp converter, IEEE Trans. Ind. Electron., vol. 55, no. 2, pp. 699710, Feb. 2008. [12] B.-R. Lin and C.-L. Huang, Interleaved ZVS converter with ripple-current cancellation, IEEE Trans. Ind. Electron., vol. 55, no. 4, pp. 15761585, Apr. 2008.

Fig. 11. circuit.

Efciency of interleaved active-clamping converter with ZVS/ZCS

Fig. 12. Simulation results of output voltage ripple. (a) Interleaved mode with 1000 F and ESR = 90 m: V rip p le = 595 mV. (b) Noninterleaved mode with 1000 F and ESR = 90 m: V rip p le = 1.19 V. (c) Noninterleaved mode with 2000 F and ESR = 45 m: V rip p le = 598 mV. Blue waveformoutput voltage ripple and red waveformthe resultant diode current isu m .

500 W. The difference is small, similar to the results reported in [3] and [12]. Output capacitor equivalent-series resistance (ESR) losses make the main difference. In this case, ESR is about 90 m and the copper trace on printed circuit board is about 5 m. The rms value of capacitor ripple current is about 3.9 A for interleaved operation and about 5.7 A for the paralleled operation. It should be pointed out that the selection of output capacitor depends not only on the capacitor ripple current requirement, but also on output voltage ripple specication. Both the capacitance value and the ESR value affect output ripple voltage. Fig. 12(a) and (b) shows the waveforms of output ripple voltage and the diode summation current isum for both the interleaved and the paralleled operations, respectively. It is noted that the dc part of isum is the load current and the ac part is basically the capacitor ripple current. It can be seen that the output ripple voltage is reduced by half from 1.19 to 0.595 V by interleaving. As can

HSIA et al.: INTERLEAVED ACTIVE-CLAMPING CONVERTER WITH ZVS/ZCS FEATURES

37

[13] M. T. Zhang, M. M. Jovanovic, and F. C. Lee, Analysis and evaluation of interleaving techniques in forward converters, IEEE Trans. Power Electron., vol. 13, no. 4, pp. 690698, Aug. 1998. [14] S.-Y. Tseng, C.-T. Hsieh, and H.-C. Lin, Active clamp interleaved yback converter with single-capacitor turn-off snubber for stunning poultry applications, in Proc. IEEE PEDS, 2007, pp. 14011408. [15] E. Orietti, P. Mattavelli, G. Spiazzi, C. Adragna, and G. Gattavari, Twophase interleaved LLC resonant converter with current-controlled inductor, in Proc. IEEE COBEP, 2009, pp. 298304.

Martin Lee received the B.S. degree in electrical engineering from the National Taiwan University of Science and Technology, Taipei, Taiwan, in 1999, and the M.S. and Ph.D. degrees in electrical engineering at the National Taiwan University, Taipei, in 2003 and 2008, respectively. Since 2008, he has been at Chicony Power Technology Corporation, Taipei. His current research interests include design and modeling of backlight inverters, control of resonant converters, ballasts, and voltage regulator.

Tsun-Hsiao Hsia was born in Ilan, Taiwan, in 1978. He received the B.S. degree in engineering science from the National Cheng Kung University, Tainan, Taiwan, in 2001. He is currently working toward the Ph.D. degree in electrical engineering at the National Taiwan University, Taipei, Taiwan. His current research interests include system control, sliding-mode control, and power electronics system design.

Chun-Shih Huang (S09) was born in Kaohsiung, Taiwan, in 1982. He received the B.S. degree in electrical engineering from the National Chung Cheng University, Chiayi, Taiwan, in 2005. He is currently working toward the Ph.D. degree in electrical engineering at the National Taiwan University, Taipei, Taiwan. His current research interests include modeling and control of switching dcdc converters and electromagnetic interference in switching power supplies.

Hsien-Yi Tsai was born in Taiwan, in 1975. He received the M.S. degree in electrical engineering from the National Tsing Hua University, Hsinchu, Taiwan, in 2001. He is currently working toward the Ph.D. degree at the National Taiwan University, Taipei, Taiwan. His current interests include circuit topology innovation of power converter and control methodology.

Dan Chen (S72M75SM83F02) received the B.S.E.E. degree from the National Chiao Tung University, Hsinchu, Taiwan, in 1969, and the Ph.D. degree in electrical engineering from Duke University, Durham, NC, in 1975. From 1975 to 1979, he was with the GE Corporate Research Center, Schecnectady, NY, where he was involved in research on power electronic applications, including electric car and electronic ballast applications. From 1979 to 2003, he was in the Department of Electrical Engineering, Virginia Polytechnic Institute and State University, Blacksburg, and was a core Professor at the National Science Foundations Center for Power Electronic Systems. In 1986, he was the Co-Founder of the Motion Control System, Inc., Dublin, VA, a company dedicated to brushless dc motor and control, where he was the Company Chief Consultant until 2003. Since September 2003, he has been a Professor in the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan. He is a Co-Editor of an IEEE Press book on Power Transistors and their Applications in 1984. He has authored or coauthored numerous papers. He holds nine US patents. His current research interests include power-conversion systems, power semiconductor device characterization, electromagnetic interference in switching circuits, and more recently power, integrated circuits. Prof. Chen was the co-recipient of the IEEE Aerospace Society Barry Carlton Award in 1975, the National Aeronautics and Space Administration Invention Award in 1986, and the IEEE Power Electronics Society Best Paper Award in 1998.