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net

A framework for Software Defined Radio and Communication Peripherals

RECOMS
Reconfigurable Embedded Communication System
Michel Starkier V1.0

RECOMS Project history and context

Developped with a research fund from the University of Applied Sciences Western Switzerland (HES-SO) A team from the School of Business and Engineering HEIG-VD Yverdon-les-Bains Vaud REDS institute, Reconfigurable & Embedded Digital Systems (7 professors / 18 engineers)

2 years development Supported by Armasuisse (DDPS/VBS)

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Embedded communication system

Traditional approach:

processor + memory

Radio

Wlan
802.11a/b/g

communication peripherals

GSM / GPRS

Bluetooth
(802.15.1)

Processor

Memory

Software radio approach

Reconfigurable hardware
Programmable

component

FPGA

Virtual

peripheral

code

Processor

Memory

service
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Hardware Embedded Platform

FPGA : Xilinx Virtex-5

2 x 1Gbit DDR2 memory 2 x ADC -2 x DAC Analog RF frontend : Ettus Research

50MHz to 6 GHz

Processor : ARM9 Xscale / Linux OS LCD touch screen, Ethernet, USB, audio

RECOMS : an original and innovative approach

Up to 4096 communication chanels
VHDL

Verilog

Matlab Simulink Blockset

QT
framework

RECOMS
API

VFS

Interface Generator

Linux
C/C++

toolchain

Reconfiguration

HARDWARE

SOFTWARE

RECOMS framework objectives

Develop an hardware interface layer (FPGA)

Develop a software layer (Linux )

code
FPGA

RECOMS Simulink Library : FPGA interface Blockset

Interface

RECOMS Software Framework : Driver, reconfiguration, API, ...

Driver,

Processor
service or application

Memory

RECOMS architecture
Applications
User Application X User Application Y User Application Z Specific Peripheral User Interface

S O F T W A R E

Specific Peripheral Service Virtual Peripheral Framework

FPGA Bitstream

Data Processing

Peripheral Settings

FPGA Reconfiguration Function

Streaming & Packet Transfer Function Set

Control Register Access Function Set

Event Manager

Core Virtualizer

FPGA Driver Generic Drivers

Bitstream Download Bus Interface Communication State Machine (De)packetizer

LCD Driver
Display & Touch Control Management

H A R D W A R E

FPGA
RECOMS Interface & Control Blockset ADC/DAC Analog Stage Interfaces Bus Interface

Communication State Machine (De)packetizer

LCD
Xilinx System Generator Blockset Radio Digital Signal Processing Display & Touch Control

Memory interface

Register Bank

Recoms architecture
Applications Applications
User User Application X Application X User User Application Y Application Y User User Application Z Application Z Specific Specific Peripheral Peripheral User Interface User Interface

S S O O F F T T W W A A R R E E

Specific Specific Peripheral Peripheral Service Service Virtual Virtual Peripheral Peripheral Framework Framework

FPGA FPGA Bitstream Bitstream

Data Data Processing Processing

Peripheral Peripheral Settings Settings

FPGA FPGA Reconfiguration Reconfiguration Function Function

Streaming & Streaming & Packet Transfer Packet Transfer Function Set Function Set

Control Register Control Register Access Access Function Set Function Set

Event Manager Event Manager

Core Virtualizer Core Virtualizer

FPGA Driver FPGA Driver Generic Generic Drivers Drivers

Bitstream Bitstream Download Download Bus Interface Bus Interface Communication Communication State Machine State Machine (De)packetizer (De)packetizer

LCD Driver LCD Driver

Display & Display & Touch Control Touch Control Management Management

H H A A R R D D W W A A R R E E

FPGA FPGA
RECOMS Interface RECOMS Interface & Control Blockset & Control Blockset ADC/DAC ADC/DAC Analog Stage Analog Stage Interfaces Interfaces Bus Interface Bus Interface

Communication Communication State Machine State Machine (De)packetizer (De)packetizer

LCD LCD
Xilinx System Xilinx System Generator Blockset Generator Blockset Radio Radio Digital Signal Processing Digital Signal Processing Display Display & & Touch Touch Control Control

Memory Memory interface interface

Register Bank Register Bank

Recoms architecture
Applications Applications
User User Application X Application X User User Application Y Application Y User User Application Z Application Z Specific Specific Peripheral Peripheral User Interface User Interface

S S O O F F T T W W A A R R E E

Specific Specific Peripheral Peripheral Service Service Virtual Virtual Peripheral Peripheral Framework Framework

FPGA FPGA Bitstream Bitstream

Data Data Processing Processing

Peripheral Peripheral Settings Settings

FPGA FPGA Reconfiguration Reconfiguration Function Function

Shell / API

Streaming & Streaming & Packet Transfer Packet Transfer Function Set Function Set

Control Register Control Register Access Access Function Set Function Set

Event Manager Event Manager

Core Virtualizer Core Virtualizer

FPGA Driver FPGA Driver Generic Generic Drivers Drivers

LCD Driver LCD Driver

Bus Interface Bus Interface Communication Communication State Machine State Machine (De)packetizer (De)packetizer Display & Display & Touch Control Touch Control Management Management

VIRTUAL FILE SYSTEM

Bitstream Bitstream Download Download

H H A A R R D D W W A A R R E E

FPGA FPGA

RECOMS Interface RECOMS Interface & Control Blockset & Control Blockset ADC/DAC ADC/DAC Analog Stage Analog Stage Interfaces Interfaces

AUTOMATICALLY GENERATED INTERFACE

Bus Interface Bus Interface Memory Memory interface interface

Communication Communication State Machine State Machine (De)packetizer (De)packetizer

LCD LCD
Xilinx System Xilinx System Generator Blockset Generator Blockset Radio Radio Digital Signal Processing Digital Signal Processing Display Display & & Touch Touch Control Control

Register Bank Register Bank

RECOMS co-design method

Starting from signal processing design .....

Matlab Simulink

Xilinx System Generator (FPGA)

....to application or service development

Shell script

Linux C/C++ programs

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RECOMS Blockset (Matlab Simulink)

FPGA Interfaces

DAC, ADC, Buttons, Leds, DDR FPGA IO

Debug connector

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Blockset RECOMS (Matlab Simulink)

Transfer data from/to processor => up to 4096

Data movers

Register blocks (R/W) supporting fixed point data, signed or unsigned Probes Scope functions (trig ...)
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Design example

RECOMS ADC block

Dmover "Register" type

Dmover "Probe" type

Linux Kernel

Linux User Space

FPGA
Bitstream

RECOMS

Drivers

Application

Matlab Simulink Design

Service
XML file
SYSFS virtual files

RECOMS API

Hardware

Software

Linux Kernel

Linux User Space

Bitstream Bitstream Bitstream

FPGA FPGA FPGA

RECOMS

Drivers

Service Service Application

Matlab Simulink Design

Service Service Service FPGA XML FPGA file

Bitstream Bitstream

SYSFS virtual files

RECOMS API

Hardware

Software

Example : Gain control

"Gain_signal" Dmover Register Block Signed, 16 bits, binary point 12

Shell command >$ recoms write Gain_signal 3.456 API (C) recoms_dmover_write_single_data("Gain_signal", 3.456); API (C++): DMover dm("Gain_signal"); dm.data().setSingleData(3.456);

Gain_signal

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Graphical User Interface

Popular QT cross-platform framework

Linux, Windows, Mac OS code

Local (LCD) or remote (network PC) Examples of QT interfaces :

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Debug tool : 4 channel oscilloscope

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RECONFIGURATION

Global reconfiguration < 500ms No shut-down, no reboot

Hardware : High speed download of bitstream

Linux : Virtual File System dynamic configuration

Software : Launch of a new application and a new user interface

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Complete Reference Design

DQPSK radio
(Differential Quadrature Phase Shift Keying)

including :

Up and down converters DDS (Direct Digital Synthetizers) Costas loop Modulator / demodulator In development : OFDM radio (Armasuisse)
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CONCLUSION

Applications : any signal processing embedded system design

Software Designed Radio

Cognitive Radio R&D prototyping
VH DL Verilog

Matlab Simulink

QT
framework

Test and measurement

RECOMS
Blocks et Interface
Generato r

VFS
API

Linux
C/C++

toolchai n

Recoms key features :

Reconfiguration

Virtual Peripheral Framework Make easy the co-design of reconfigurable system Global and efficient reconfiguration mecanism
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Swiss T.net

Questions ?

We invite you to visit our institute and watch a demonstration

Michel Starkier V1.0