process variation aware FINFET based sram cell

Ashvinikumar Dongre sumit patel

16 April,2012

Contents

Contents:
1. Introduction 2. Need for Novel devices 3. FinFET models 4. Classification of process variation
What is NBTI/PBTI

5. Variations on stability of 6T FinFET SRAM cells with various surface orientations due to NBTI/PBTI 6. Work progress 7. Reference

Introduction

Introduction
As dimensions of MOS devices have been scaled down, new reliability problems are coming into eect. One of these emerging reliability issues is aging eects which result in device performance degradation over time. NBTI (Negative Bias Temperature Instability) and PBTI (Positive Bias Temperature Instability) are well known aging eects which cause the threshold voltage degradation of PMOS and NMOS transistors over time. Thus NBTI (for PFET) and PBTI (for NFET)) have become major long-term reliability concerns as they weaken MOSFETs over time, thus resulting in temporal degradation in the stability of the SRAM cells.

Why there is a need to switch over from cmos to novel devices.

Why there is a need to switch over from cmos to novel devices.

Bulk CMOS vs SOI CMOS
1. In a bulk CMOS device, each transistor is isolated by reversebiased pn junctions in a well structure. On the other hand, in a SOI CMOS device, each transistor is completely isolated by the Oxide insulator. Thus, parasitic eects in a SOI device are very small.

FDSOI

FDSOI
There are two kinds of SOI devices; Partially Depleted (PD)-SOI and Fully Depleted (FD)SOI. The PD-SOI has a relatively thick SOI Si thickness (100-200 nm),while in the FD SOI the SOI thickness is less than 50 nm in the FD-SOI the SOI thickness is less than 50 nm. In PD-SOI, there remains a neutral region in the body. In FD-SOI, the whole body under the gate will deplete.

Scaling challenges

Scaling challenges
At the device gate length (L) less than 100nm, further, reduction in L has yielded limited improvements in performance due to velocity saturation and source velocity limit. As the physical thickness of the SiO2 gate dielectric (Tox ) is scaled beyond 1.2nm, quantum mechanical tunneling current from the gate into the channel becomes signicant. Further reduction in Tox will result in large static leakage current and large power consumption even when the device is turned o.

Scaling challenges contd...

A new approach is needed to allow future reduction of channel length. The multigate structure is a promising approach.

Multigate advantages

Multigate advantages
The main advantage of the multigate devices is the improved short channel eects . Since the channel is controlled electrostatically by the gate from multiple sides, the channel is better controlled by the gate than in the conventional transistor structure. Unwanted leakage components are reduced. Improved gate control also provides lower output conductance. The second advantage is improved on state drive current (Ion)and therefore faster circuit speed.

Multigate advantages(contd...)

Multigate advantages(contd...)

The FinFET, provides a larger channel width with a small footprint in area. This raises Ion , which is handy for driving a large capacitive load such as long interconnect.

The third advantage is the reduced manufacturing variation. In the absence of channel dopants, the eect of random dopant uctuation (RDF) is minimized.

FinFET Variants

FinFET Variants

FinFET models

FinFET models
Multi gate MOSFETs are divided in two main categories:
1. independent multigate (IMG) 2. common multi gate (CMG) MOSFETs.

BSIM IMG
1. IMG refers to independent doublegate MOSFETs with two separate gates. 2. The front and back gate stacks are allowed to have deferent gate workfunctions, biases, dielectric thicknesses and materials. 3. Independentgate FinFET and the planar doublegate SOI belong to this category.

FinFET models(contd...)

FinFET models(contd...)

BSIMCMG
1. CMG refers to a special case where the gates are connected together. 2. The gate stacks of CMG MOSFETs have identical gate workfunction, bias and dielectric thickness and material. 3. Regular FinFETs and all around gate MOSFETs fall into to this category.

Small signal model for FinFET(contd...)

Small signal model for FinFET(contd...)

Small signal model for FinFET

Small signal model for FinFET

Small signal model for FinFET(contd...)

Small signal model for FinFET(contd...)

Classification on process variation

Classification on process variation

NBTI Mechanism and modelling

NBTI Mechanism and modelling

NBTI is caused by broken Si-H bonds, which are induced by positive holes from the channel. Then H, in a neutral form, diuses away; positive interface traps (N it ) (i.e., from Si + ) are left, which cause the increase of V th.

the change in vth due to NBTI can be modelled as ....(1) and Nit is positive interface trap which can be expressed as ....(2)

NBTI Modelling contd...

NBTI Modelling contd...

K is the generation rate of Nit and found to be linearly proportional to the hole density and exponentially dependent on temperature (T) and the electric eld (Eox)Therefore, for V ds =0: ....(3) The dependence of K on Vds can be derived from Eq. (3) as: ....(4)

NBTI Modelling contd...

NBTI modelling contd...

In Phase II, when Vg=VDD (i.e., V gs =0), holes are not present in the channel and thus,no new interface traps are generated; instead, H diuses back and anneals the broken Si-H. As a result, the number of interface traps is reduced during this stage and the NBTI degradation is recovered. Assuming the recovery happens at t=t 0 with Nit=Nit0 , the ....(5) change of Nit can then be modeled as following gure explains the behaviour of NBTI in more detail

Effects of NBTI/PBTI on SRAM

Effects of NBTI/PBTI on SRAM

As we can see the PU(pull up)transistors are eected by NBTI and PD(pull down)PG(pass gate)transistors are aected by PBTI.

These are the eect of NBTI/PBTI on Vth at 32nm node.

Effects of NBTI/PBTI on SRAM

Effects of NBTI/PBTI on SRAM

Surprising we see that SNM increases in presence of NBTI/PBTI.

But at the same time decrease in Iread may cause read failure.

Techniques to mitigate effects of NBTI/PBTI

Techniques to mitigate effects of NBTI/PBTI

From above discussion we can conclude that NBTI/PBTI depends on Process parameters : Vth,Tox Design parameters : VDD,Vds,Duty cycle Keeping these points in mind the techniques available to mitigate the eect of NBTI can be stated as
1. An optimal VDD exists to minimise the degradation 2. PMOS sizing 3. Reducing the duty cycle

WHY FinFET in SRAM..???

WHY FinFet in SRAM..???

FinFet based SRAM is found to be more immune to mismatch induced by process variation. A FinFet uses an intrinsic body,it greatly suppresses the device-performance variability caused by uctuations in number of dopant ions. FinFet is suitable for future nano scale memory circuits design due to its reduced short channel eects. FinFet cell oers superior noise margins and switching speeds as well. An added advantage of the FinFet is that it can be easily fabricated along dierent channel planes in a single die,whereas Fabrication of conventional planar MOSFETs along any plane other than (100) is dicult due to increased process variations and interface traps

Oriented FinFETs

Oriented FinFets
With the advent of FinFETs, fabrication of transistors along the (110) plane has become feasible, leading to design of circuits using dierently oriented transistors.

Electron mobility is highest in the (100) plane and the hole mobility along the (110) plane. Thus, logic gates consisting of p-type FinFETs implemented in the (110) plane and n-type FinFETs in the (100) plane will be the fastest.

Effect of NBTI/PBTI on FinFET with different orientation

Effect of NBTI/PBTI on FinFET with different orientation

The variability of RSNM due to NBTI/PBTI can be shown as

The variability of WSNM due to NBTI/PBTI can be shown as

Effect of NBTI/PBTI on FinFET with different orientation

Effect of NBTI/PBTI on FinFET with different orientation

The entire analysis can be summarised as

Work progress

Work progress
Tools used
1. SILVACO-ICCAD(GATEWAY,SMARTSPICE) 2. SILVACO-TCAD(ATHENA, ATLAS,DevEdit3D)

We found two ways to implement Finfet based SRAM

1. Take the model les and work on circuit level. 2. Start work from device level and then use that device at circuit level.

We started from device level We went through the device and process simulation steps and tried to modied the example of FinFET according to our requirement. Still working on how to use BSIM-CMG 106.0.0(latest model released on 15th march 2012) for Finfet simulation

Reference

Reference
Vita Pi-Ho Hu, Ming-Long Fan, Chien-Yu Hsieh, Pin Su and Ching-Te Chuang,FinFET SRAM Cell Optimization Considering Temporal Variability due to NBTI/PBTI and Surface Orientation , SISPAD 2010 Rakesh Vattikonda,Wenping Wang,Yu Cao,Modeling and Minimization of PMOS NBTI Eect for Robust Nanometer Design,DAC 2006, San Francisco, California, USA. Harwinder Singh,San Francisco State University, California,Thesis on ANALYSIS OF SRAM RELIABILITY UNDER COMBINED EFFECT OF TRANSISTOR AGING,PROCESS AND TEMPERATURE VARIATIONS IN NANO-SCALE CMOS.