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CHAPTER 9: ASYNCHRONOUS SEQUENTIAL CIRCUITS

Chapter Objectives
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Sequential circuits that are not synchronized by a clock Asynchronous circuits Analysis of Asynchronous circuits Synthesis of Asynchronous circuits Hazards that cause incorrect behavior of a circuit

Asynchronous sequential circuits

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Synchronous sequential circuits

state variables : F/Fs controlled by a clock operate in pulse mode

Asynchronous sequential circuits

do not operate in pulse mode do not use F/Fs to represent state variables Changes in state are dependent on whether each of inputs to the circuit has the logic level 0 or 1 at any given time

To achieve reliable operation (focus on the simplest case)

the inputs to the circuit must change one at a time there must be sufficient time between the changes in input signals to allow the circuit to reach a stable state A circuit that adheres to these constraints is said to operate in the

fundamental mode

Asynchronous behavior
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R S Y

y Q

(a) Circuit with modeled gate delay Next state SR = 00 Y 0 1 01 Y 0 0 10 Y 1 1 11 Y 0 0

two NOR gate delay

Present

Y = (y + S) + R

state y 0 1

stable state

(b) State-assigned table

FSM model for the SR latch

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Present state A B

Next state

SR = 00
A B

01 A A

10 B B

11 A A

Output Q 0 1

(a) State table

Moore-type FSM

SR 10 00 01 11 A0 01 11 B1 00 10

(b) State diagram

Synthesis of an asynchronous circuit

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Nextstate Present state SR = 00 01 10 A A A B B B A B

11 A A

Output Q 0 1

Y = R (S + y) = R (S + y) = ( R + ( S + y )) = ( R + ( S + y )) z=y

(a) State table

Nextstate Present state SR = 00 01 10 y Y Y Y 0 1 (b) 0 1 0 0 1 1

11 Y 0 0
R S Y y Q

State-assigned table

Mealy representation of the SR latch

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Next state Present state SR = 00 01 10 A B A B A A B B

Output, Q 11 A A 00 0 1 01 0 10 1 11 0
there is little to be gained in trying to make output Q go to 1 a little sooner

(a) State table

SR/Q 10/ 00/0 01/0 11/0 A 01 11 B 00/1 10/1

Y = R (S + y) = R (S + y) = ( R + ( S + y )) = ( R + ( S + y )) Q= y

(b) State diagram

Terminology
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Asynchronous circuits
state table -> flow table state-assigned table -> transition table or excitation table

We will use the term flow table and excitation

table

Analysis of Asynchronous Circuits

Analysis of Asynchronous circuits

10 D Y y Q C Present P state y 0 1 Next state CD = 00 Y 0 1 01 Y 0 1 10 Y 0 0 11 Y 1 1 Q 0 1

(b) Excitation table (a)gated D latch Next state CD = 00 A B 01 A B 10 A A 11 B B Q 0 1

Y = (C D) ((C D ) y ) = (C D) + ((C D ) y ) = CD + ((C + D) y ) = CD + C y + Dy = CD + C y

redundant d d term to solve a hazard

Present state A B

CD 0x x0

( ) (c) Flow table 11 A0 10 (d) State diagram B1 0x x1

Analysis of the circuit in example 9 3 9.3

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Y1 w1 w2 Y2

y1

y2

Y1 = y1 y2 + w1 y2 + w1w2 y1 Y2 = y1 y2 + w1 y2 + w2 + w1w2 y1 z = y1 y2

Excitation and flow tables for the circuit in example 9.3

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Nextstate Ne tstate Present state w2 w1 = 00 01 10 y 2 y1 Y2 Y1 Y2 Y1 Y2 Y1 00 01 10 11 00 11 00 11 01 01 10 10 10 11 10 10

11 Y2 Y1 11 11 10 10

Output z 0 0 1 0

(a) Excitation table

Nextstate Present state w2 w1 = 00 01 10 A B C D A D A D B B C C C D C C

11 D D C C

Output z 0 0 1 0

(b) Flow table

Modified flow table for Example 9 3 9.3.

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Next state Present state w2 w1 = 00 01 10 A B C D A D A D B B C C C

Output p 11

z
0 0 1 0

D C C

C C

State table for Example 9 3 9.3

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w2w1

00

A/0

01

B/0

01

10

00

00 11

1x x1

C/1

1x x1

D/0

00

Flow table for a simple vending machine

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Next state Present state w2 w1 = 00 01 10 A B C D A D A D w2 dime B B C C C

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Output z 0 0 1 0

C C

w 1 nickel

Steps in the Analysis Process

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Each feedback E h f db k path i cut h is

A delay element is inserted at the point where the cut is made A cut can be made anywhere in a particular loop formed by feedback connection, as long as there is only one cut per (state variable) loop

Next-state Next state and output expressions are derived from the circuit The excitation table is derived A flow table is obtained A corresponding state diagram is derived from the flow table if desired

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Synthesis of Asynchronous Circuits

Synthesis of Asynchronous Circuits

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the same basic steps used to synthesize the synchronous circuits

Devise a state diagram for an FSM Derive the fl D i th flow t bl and reduce th number of states if table d d the b f t t possible Perform the state assignment and derive the excitation table Obtain the next-state and output expressions Construct a circuit that implements these expressions

Example: serial parity generator

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Serial parity generator

input w : pulses are applied to w output z z=1 if the number of previously applied pulses is odd
w z
0

1
A/0 1

0
B/1 0 1 C/1 0

0 1 D/0

(a) State diagram

Parity generating Parity-generating asynchronous FSM

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A/0

B/1

0 D/0 1

C/1

(a) State diagram

Nextstate Present State w = 0 w = 1 A B C D A C C A B B D D Output z 0 1 1 0

(b) Flow table

State assignment
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Present P t state y 2y 1 00 01 10 11 00 10 10 00 Next state w= 0 w= 1 Output z 01 01 11 11 0 1 1 0

State assignment (a) has a major flaw

state D =11 : w=0 -> state A y2y1=11 -> y2y1=00 the values of the next-state variables determined by the networks of logic gates with varying delays suppose y1 changes fi t h first y2y1=10 -> state C(10) state C is stable when w=0 suppose y2 changes first y2y1=01-> state B (01) try to change to y2y1=10 when w=0 if y1 changes first, y2y1=00

Y 2Y 1

(a) Poor state assignment

Present state y 2y 1 00 01 11 10

Next state w= 0 w= 1 Output z 01 01 10 10 0 1 1 0

Y 2Y 1 00 11 11 00

race condition occurs

(b) Good state assignment

Circuit that implements the FSM

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Y1 = wy2 + w y1 + y1 y2 Y2 = wy2 + w y1 + y1 y2 z = y1
w y1 z

y2

D w

Q Q

Synchronous solution

Asynchronous solution

Circuit that implements a paritygenerating asynchronous FSM

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The asynchronous implementation is more complex than the synchronous one? It s negative-edge-triggered Its a negative edge triggered master/slave F/F
With the complement of its output connected to its D input

Master slave Master-slave D F/F(example 9 2) 9.2)

Analyze synchronous circuit as if it were an A l h i it asynchronous circuit.
Actually all circuits are asynchronous y y

Y = CD + C y + Dy in the previous example of gated D - Latch g Ym = CD + C ym + Dym Ys = C ym + Cy s + ym y s

D C

Master D Q ym

Slave D Q ys Q Q

Clk Q

Clk Q

Circuit for the master-slave D flip-flop.

Excitation table for example 9 2 9.2

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Present state ym ys 00 01 10 11

CD

Next state = 00 01 10 Ym Ys 00 00 11 11 00 00 11 11 00 01 00 01 table

11 10 11 10 11

Output Q 0 1 0 1

(a) Excitation

Flow tables for Example 9 2 9.2

Present state S1 S2 S3 S4 Next state CD = 00 S1 S1 S4 S4 01 S1 S1 S4 S4 10 S1 S2 S1 S2 table Output Q 0 1 0 1 11 S3 S4 S3 S4 Output Q 0 1 0 1

(b) Flow Present state S1 S2 S3 S4

Next state CD = 00 S1 S1 S4 01 S1 S4 S4 10 S1 S2 S1 S2 11 S3 S4 S3 S4

(c) Flow Table with unspecified entries

State diagram for the master-slave D Flip/Flop /

CD 11 0x x0 0 S1 0 10 S3 0 11

0x 11 10 S2 1 10

0x

S4 1

0x x1

Parity generating FSM and Masterslave D F/F /

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Y1 = wy2 + w y1 + y1 y2 Y2 = wy2 + w y1 + y1 y2 z = y1

Y = CD + C y + Dy in the previous example of gated D - Latch Ym = CD + C ym + Dym Ys = C ym + Cy s + ym y s

Master Slave D Q

y1 = ym , y2 = y s w = C , y 2 = D, z = y1 = ym

D
w

y1=z

y2

Q Q

Clk Q

Clk Q

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Hazard and Glitches

Hazards and glitches

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In I asynchronous circuits h i it
undesirable glitches on signals should not occur hazards
the glitches cause by the structure of a given circuit and propagation delays in the circuit

two types of hazards

static the signal undergoes a momentary change in its required value dynamic when a signal is supposed to change from 1 to 0 or from 0 to 1 a change involves a short oscillation before the signal settles into its new level

Definition of hazards
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1 0 11 (a) Static hazard 1 0 10 (b) Dynamic hazard 01 00

Hazards and glitches

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Usual solutions
wait until signals are stable by using a clock
preferable easiest to design when there is a clock synchronous circuits

design hazard-free circuits

sometimes necessary asynchronous design

Static hazards
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x2 x1

p f q (a) Ci it ith hazard ( ) Circuit with a h d x1 x2 00 0 1 1 1 01 11 1 1 10

f = x1 x2 + x1 x3

f = x1 x2 + x1 x3 + x2 x3
x2 x1

x3

x3

x3

(b) Karnaugh map

(c) Hazard-free circuit

hazard free hazard-free if more than one bit of inputs change simultaneously ?

Two-level implementation of master-slave D flip-flop

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Present state ym ys 00 01 10 11

CD

Next state = 00 01 10 Ym Ys 00 00 11 11 00 00 11 11 00 01 00 01 table

CD

11 10 11 10 11

Output Q 0 1 0 1

(a) Excitation
CD ymys 00 01 11 10 1 1 1 1 00 01 11 1 1 1 1 10 ymys

00 00 01 11 10 1 1

01

11

10

Ym = CD + C ym + Dym Ys = C ym + C s + ym y s Cy

1 1 1 1

1 1

(b) Karnaugh maps for Ym and Ys in Figure 9.6a

Two-level implementation of master-slave D flip-flop ( ) (2)

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ym

D ym C

D Ym

Ym Ys C Q Ys Q

ys

(a) Minimum-cost circuit

ys

(c) Hazard-free circuit

Ym = CD + C ym + Dym Ys = C ym + C s + ym y s Cy

Static hazard in a POS circuit (0hazard) )

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x1 x2

p x1 f q (a) Circuit with a hazard x1 x2 00 0 1 0 0 01 0 1 11 0 1 10 1 1 (c) Hazard free circuit Hazard-free x3 f x2

x3

x3

(b) Karnaugh map

dynamic hazards
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there exist multiple paths f a th i t lti l th for given signal change to propagate along neither easy to detect nor easy to deal with using t i two-level h l l hazard-free d f circuits
b x1 x2 x3 x4 (a) Ci it ( ) Circuit a c d f

One gate delay x1 x2, x3, x4 a b c d f

(b) Timing diagram

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CLOCK SYNCHRONIZATION (CHAPTER 10.3)

Clock skew
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the l k i th clock signal arrives at diff l i t different ti t times at t different F/Fs

with or without clock enable circuits wires whose lengths vary appreciably
Data Clock E D Q Q

Data Clock

Q Q

An H tree clock distribution network H-tree

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ff

ff

ff

ff

ff

ff

ff Clock ff

ff

ff

ff

ff

ff

ff

ff

ff

F/F timing parameters

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setup time tsu hold time th register delay or propagation delay trd output delay time tod
required for the change in Q to propagate to an output pin on the chip
t Data
Data

Chip package pin pp g p

A
Clock

B tCl k Clock tod d

Out

A flip-flop in an integrated circuit

F/F timing parameters contd parameters, cont d

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at an output pin
tClock + trd + tod

tco delay : active clock edge -> output change >

Example tClock = 1.5ns, trd=1ns, tod=2ns -> tco =4.5 ns

F/F timing in a chip

tClock=1.5 ns, tData=4.5 ns, tsu=3 ns
Clock 3ns Data aa 4.5ns A 1.5ns 1 5ns B

setup time violation

Metastability and Asynchronous Inputs

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Asynchronous Inputs Are Dangerous!

Since they take effect immediately, glitches can be disastrous Synchronous inputs are greatly preferred! But sometimes, asynchronous inputs cannot be avoided e.g., reset signal, memory wait signal

Metastability and Asynchronous Inputs

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Handling Asynchronous Inputs

Clocked Synchronous System Async Input D Q Q0 Async Input D Q

Synchronizer Q0

Clock D Q Q1 D Q

Clock Q1

Clock

Clock

Never allow asynchronous inputs to be fanned out to more than one FF within the synchronous system

Metastability and Asynchronous Inputs

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What Can Go Wrong Setup time violation! In is asynchronous Fans out to D0 and D1 One FF catches the signal, one does not impossible state might be reached!

In Q0 Q1 Clk

Single FF that receives the asynchronous signal is a synchronizer

Metastability and Asynchronous Inputs

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Synchronizer Failure When FF input changes close to clock edge, the FF may enter the metastable state: neither a logic 0 nor a logic 1 In out
D Q

It may stay in this state an indefinite amount of time, although this is not likely in real circuits
Logic 1

Logic 0

Logic 0

Logic 1

Time

Small, but non-zero probability that the FF output will get stuck in an in-between state

Oscilloscope Traces Demonstrating Synchronizer Failure and Eventual Decay to Steady State

Metastability and Asynchronous Inputs

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Solutions to Synchronizer Failure the probability of failure can never be reduced to 0, but it can be reduced slow down the system clock this gives the synchronizer more time to decay into a steady state synchronizer failure becomes a big problem for very high speed systems use fastest possible logic in the synchronizer this makes for a very sharp "peak" upon which to balance S or AS TTL D-FFs are recommended cascade two synchronizers Synchronized Input Clk Synchronous System

Asynchronous Input