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Memory Built-In Self-Repair Built- Self


Jin-Fu Li
Advanced Reliable S Ad d R li bl Systems (ARES) Lab. L b Department of Electrical Engineering National Central University Jhongli, Taiwan

Introduction Redundancy Organizations Built-In Redundancy Analysis Techniques Built-In Self-Repair Techniques Conclusions

Advanced Reliable Systems (ARES) Lab., EE. NCU

Jin-Fu Li


Embedded Memory–Quality
During manufacture
Yield Exponential yield model Y = e− AD , where A and D denote the area and defect density, respectively

After manufacture

During use
Soft error rate

Advanced Reliable Systems (ARES) Lab., EE. NCU

Jin-Fu Li


An Explosion in Embedded Memories
Hundreds of memory cores in a complex chip is common Memory cores usually represent a significant portion of the chip area ti f th hi




AMD dual-core Opteron™ processor
Advanced Reliable Systems (ARES) Lab., EE. NCU

Intel dual-core Intanium processor (JSSC, 2006)
Jin-Fu Li 4

Memory Repair Repair is one popular technique for memory yield improvement Memory repair consists of three basic steps Test Redundancy analysis Repair delivery Advanced Reliable Systems (ARES) Lab. NCU Jin-Fu Li 5 .. EE.

Expensive 2 E i Advanced Reliable Systems (ARES) Lab. NCU Jin-Fu Li 6 . EE.Conventional Memory Repair Flow Test Error Logging Bitmap Redundancy Analysis Laser Repair Test Requirements: 1. 1 Memory tester 2.. Time consuming 2. Laser repair equipment Disadvantages: 1.

. EE. NCU Jin-Fu Li 7 .Memory BISR Flow Required Circuit BIST BISD BIRA Built-In Self-Test Built-In Self-Diagnosis Built-In Redundancy-Analyzer Reconfiguration Function Test Fault Location Redundancy allocation Swap Defective Cells Advanced Reliable Systems (ARES) Lab.

Typical Memory BISR Architecture
Normal I/Os Reco onfigura ation mechanism s

Test Collar & t





Advanced Reliable Systems (ARES) Lab., EE. NCU

Jin-Fu Li


Typical Memory BIST Architecture
Normal I/Os

Test Controller Tes Collar st r


Test Pattern Generator


Advanced Reliable Systems (ARES) Lab., EE. NCU

Jin-Fu Li


Redundancy Organizations
A memory array with local redundancies

Bank 1 Local S L l Spare Columns Bank B k2 Local Spare p Rows


Jin-Fu Li

EE, National Central University

Redundancy Organizations
A memory array with hybrid redundancies

Bank 1

Bank B k2 Local Spare p Rows

Global (Linked) p Spare Columns
Jin-Fu Li EE, National Central University


Redundancy Organizations A memory array with hybrid redundancies Bank 1 Bank 2 Bank 2 Global (Linked) ( ) Spare Rows Bank B k2 Local p Spare Columns Jin-Fu Li EE. National Central University 12 .

. NCU . EE.Redundancy Scheme Three typical local redundancy schemes Spare rows Spare columns Jin-Fu Li Spare rows and Spare columns 13 Advanced Reliable Systems (ARES) Lab.

NCU . Q0 Q1 Jin-Fu Li Q1 c0c1c2c3 Q6 c0c1c2c3 Q7 c0c1c2c3 Q6 Q7 [ LogicVision] 14 Advanced Reliable Systems (ARES) Lab. EE..Spare Column & Spare IO c0c1c2c3 r0 r1 r2 r3 c0c1c2c3 c0c1c2c3 c0c1c2c3 c0c1c2c3 Spare IO Q0 c0c1c2c3 r0 r1 r2 r3 Spare Col.

. NCU Jin-Fu Li 15 32 columns Spare column Sense Amplifier p . et al. 2002] Advanced Reliable Systems (ARES) Lab. JSSC.. Yarmaoka. EE.Reconfiguration Scheme 32 columns Spare co S olumn Sense Amplifier p Decoder 10-bit 10 bit data Programming Module (Flash) [M.

NCU Jin-Fu Li 16 .Types of Reconfiguration Schemes Three kinds of reconfiguration techniques Soft reconfiguration f fi i By programming FFs to store repair information yp g g p Firm reconfiguration By B programming non-volatile memories to store i l til i t t repair information Hard (permanent) reconfiguration Laser-blown or electrically-blown polysilicon or y p y diffusion fuses Advanced Reliable Systems (ARES) Lab. EE..

. 2 Short repair setup time Disadvantages 1. Multi-time repair 2. Some latent defects cannot be repaired 2. EE. High-voltage programming circuit is required q 1. Low design overhead 1. Multi-time repair 2. Short repair setup time Advanced Reliable Systems (ARES) Lab. NCU Jin-Fu Li 17 .Comparison Advantages Soft 1. Long repair setup time 2 L i t ti 1. Specific technology is required Firm Hard 1. One-time repair 2.

NCU Jin-Fu Li 18 .Memory BISR Techniques Dedicated BISR scheme A RAM has a self-contained BISR circuit self contained Shared BISR scheme Multiple RAMs share a BISR circuit E. processor-based E g processor based BISR scheme and IP based IP-based BISR scheme BISR classification according to the capability l ifi ti di t th bilit of redundancy analysis BISR with redundancy analysis capability BISR without redundancy analysis capability Advanced Reliable Systems (ARES) Lab. EE...g.

BISR Strategies Types of BISR Off-line BISR On-line BISR Off line Off-line BISR without BIRA ability BIST + reconfiguration mechanism Off-line Off line BISR with BIRA ability BIST + BIRA + reconfiguration mechanism On-line O li BISR 19 Jin-Fu Li EE. National Central University .

National Central University .Examples of BISR Design NEC BISR design without BIRA (JSSC92) 5 32 26 21 32 I/O Buffer I/O 64 Mb Memory Array 21 21 Spare p Memory M 16wx32b 16 32b 32 32 CAM 16wx21b BISR Block ROM 20 TPG Comparator C Jin-Fu Li Fail BIST Block EE.

National Central University .Examples of BISR Design A BISR design (ITC98) Data Input Bus Main Memory Spare Memory Column Decoder Redundancy Analysis Algorithm Information 21 Reconfiguration Control Unit Jin-Fu Li EE.

ITC01] Advanced Reliable Systems (ARES) Lab. NCU Jin-Fu Li 22 . EE. et. Schober.. Control BIST Mux Fuse Box Redundancy Logic RAM Mux [ V. al.RAM BISR Using Redundant Words Address. Data Input.

Redundancy Wrapper Logic The redundancy logic consists of two basic components Spare memory words Logic to program the address decoding The address comparison is done in the redundancy logic The address is compared to the addresses that are stored in the redundancy word lines An overflow bit identifies that there are more failing addresses than possible repair cells The programming of the faulty addresses is done during the memory BIST or from the f h f h fuse b d i memory box during setup Advanced Reliable Systems (ARES) Lab. EE.. NCU Jin-Fu Li 23 .

Control RAM RAM Data Data Data Data Word Redundancy Overflow Advanced Reliable Systems (ARES) Lab. NCU TDO Jin-Fu Li Data out [V. Data Input.. ITC01] 24 . et. Schober.An Array of Redundant Word Lines MBIST Address F Fail TDI fail FA FA FA FO Control Address Fail Address Address Address Address Write Data Expected Data Address. EE. al.

completion Then the fuse box is blo n f se bo blown accordingly in the last step of the test This is called here hard repair s s o y done wafer eve es This is normally do e at w e level test Furthermore.. NCU Jin-Fu Li 25 . EE.Applications of Redundancy Logic Faulty addresses can be streamed out after test completion. the application can be started immediately after the memory BIST passes i di t l ft th This is called here soft repair Advanced Reliable Systems (ARES) Lab.

Schober. DO [V. al. EE. et.Redundancy Word Line Fail Fail_address _ A R W DI Expected_data p _ TDI FA Address Data TDO Comparator & & Read Fail Fail_address Expected_data. ITC01] Advanced Reliable Systems (ARES) Lab.. NCU Jin-Fu Li 26 .

al. ITC01] 27 . et.. Schober. EE.One-Bit Fuse Box One-bit f O bi fuse box contains a fuse bit and a scan flip flop b i f bi d fli fl for controlling and observing the fuse data Test_Update=0: the chain of inverters is closed (The value is latched) Test_Update=1: i is possible to set the internal node from TDO T U d 1 it i ibl h i l d f The ports TDI and TDO are activated at scan mode Test_Update TDI Scan FF TDO FRest FRead FGND Fout Reset cycle to read out the fuse information Fuse Bit (FB) Advanced Reliable Systems (ARES) Lab. NCU Jin-Fu Li FRest FRead FGND Fuse 1 0 t [V.

ITC01] Advanced Reliable Systems (ARES) Lab. EE. NCU Jin-Fu Li 28 .Fuse Boxes The fuse box can be connected to a scan register to stream in and out data during test and redundancy g y configuration Update Reset Fuse Box FB FB FB TDI Scan FF Scan FF Scan FF TDO Fail A[0] A[N-1] [V. et. Schober. al..

EE. al.. Schober.Parallel Access of the Fuse Information Fuse Box Fuse activation Address to be fuse BIST FA Fuse Address FA Fuse Address FA Address Register g FA Fuse Address FA Address Register g FA Address Register g Redundancy Logic [V. ITC01] Advanced Reliable Systems (ARES) Lab. NCU Jin-Fu Li 29 . et.

et. NCU Jin-Fu Li 30 . ITC01] Advanced Reliable Systems (ARES) Lab..Serial Access of the Fuse Information Fuse Box Fuse activation TDI Address to be fuse BIST FA Fuse Address FA Fuse Address FA Address Register FA Fuse Address FA Address Register FA Address Register Redundancy Logic TDO [ V. Schober. EE. al.

et. EE. ITC01] Advanced Reliable Systems (ARES) Lab. NCU Jin-Fu Li 31 . Schober.Test Flow to Activate the Redundancy Initialization of the BIST Load faulty addresses Increment address Access memory No Yes Test finished? No Fail? Yes No Fuse to be blown? Yes No Free eg ste register? Yes Stream out faulty addresses Soft repair Hard repair Unrepairable Write expected data p Write address Write Fail flag [ V.. al.

NCU Jin-Fu Li 32 .. EE.Redundancy Analysis A repairable memory with 1D redundancy Redundancy allocation is straightforward A repairable memory with 2D redundancy i bl ih d d Redundancy analysis (redundancy allocation) is needed Redundancy analysis problem Choose the minimum number of spare rows and columns that cover all the faulty cells 2 1 1 2 3 4 5 6 Advanced Reliable Systems (ARES) Lab.

Redundancy Analysis Using ATE Create a fault map which size is the same as the memory under test y 0 2 4 1 2 2 0 1 Column Counters 1 0 1 1 0 1 1 2 2 1 0 0 1 1 0 Row Counters Execute software-based redundancy analysis using computer in ATE t i 33 Jin-Fu Li EE. National Central University .

Redundancy Analysis Using ATE Hardware necessary to execute the redundancy d h d d analysis A device image memory (or fault memory) The size is the same as the memory under test Counters that indicate the number of faults that occur in a row. or a column Apparently. National Central University . the conventional software-based A l h i l f b d redundancy analysis algorithms are not adapted to be realized with hardware and be embedded into the li d i h h d db b dd d i h SOCs Hardware overhead is too large Efficient built-in redundancy-analysis (BIRA) algorithms are required to be developed 34 Jin-Fu Li EE.

then all possible repair solutions (Cs) R-R-C-C (Solution 1) R-C-R-C R C R C (Solution 2) R-C-C-R (Solution 3) C-R-R-C (Solution C R R C (S l ti 4) C-R-C-R (Solution 5) C-C-R-R (Solution C C R R (S l ti 6) Solution 1 (R-R-C-C) [ T. NCU Jin-Fu Li 35 . ITC00] Advanced Reliable Systems (ARES) Lab. EE. Kawagoe . al.BIRA Algorithm – CRESTA Comprehensive Real-time Exhaustive Search Test and Analysis Assume that a memory has 2 spare rows (Rs) & 2 spare columns (Cs).. et.

Kawagoe .CRESTA Flow Chart Start Test Fail ? Yes No S1 S2 S3 S6 Finish ? Yes No Result Output End Advanced Reliable Systems (ARES) Lab.. ITC00] 36 . NCU Jin-Fu Li [T. EE. et. al.

Basic Idea and Limitation of CRESTA Assume that there are m spare rows and n spare columns in a memory. CRESTA will need C(4.. 2)=6 sub-analyzers Each sub-analyzer analyzes in-coming row/column y y g addresses of faulty memory cells in parallel in a different repair strategy p gy Because CRESTA tries all the possible repair strategies of spare resources it guarantees finding a solution for a resources.g. p p . repairable memory 37 Jin-Fu Li EE. National Central University . g. if 2 spare rows and 2 spare columns are available. m) sub-analyzers E. Then a CRESTA repair analyzer y p y contains C(m+n.

Basic Idea and Limitation of CRESTA Since CRESTA needs row address and column address of a faulty memory cell in order to check if the current y y faulty memory cell can be repaired by previously allocated spare resources p It is unable to handle at-speed multiple-bit failure occurring in a word-oriented memory Determine the number of spare columns needed for all failure bits in a word cannot be achieved in one cycle In an at-speed BISR design. National Central University . a column repair vector (CRV) is used to store column failure information for solving this problem CRV is a column repair vector of the same size as the word width 38 Jin-Fu Li EE.

National Central University .At-Speed BIRA Example of redundancy allocation CCRR (Unrepairable) RSV C C R R BIST Read Cycle 0 1 2 3 4 Fail_ Map 00000 10001 01110 01110 00000 Current Spare C1 C1 C2 R1 R1 Allocated Rows -----CRV 00000 10001 11111 11111 11111 0 0 1 2 3 4 1 1 2 3 4 1 2 3 2 3 2 3 CRRC RSV C R R C BIST Read Cycle 0 1 2 3 4 39 Fail_ Map 00000 10001 01110 01110 00000 Current Spare C1 C1 R1 R2 C2 Allocated Rows --R1 R1R2 R1R2 CRV 00000 10001 10001 10001 10001 Jin-Fu Li EE.

update the repair strategy if the current repair strategy fails and then re-run BIST and try the th next repair strategy t i t t 40 Jin-Fu Li EE.At-Speed BIRA Implementation Restart BIST Controller Fail/Success Memory Under Test BISRA Controller Repair Data Repairable In the BISRA. National Central University . m) analysis engines or just one engine can be implemented In one engine scheme. all C(m+n.

m) controller ith C(m+n engines BISRA cont olle with one controller ith engine 41 Jin-Fu Li EE. National Central University .At-Speed BIRA Implementation Fail Map Address SRA CAR A B I T E R Fail Map Address SRA CAR BISRA Engine BISRA Engine g SRA CAR Restart BISRA Engine RSR BISRA cont olle with C(m+n.

CRV to BISRA controller Repair Strategy Reconfiguration (RSR) block: updates the repair strategy and sends a “restart” signal to BIST controller restart 42 Jin-Fu Li EE. such as faulty row addresses and CRV.At-Speed BIRA Implementation Spare Resource Allocation (SRA): allocates either a spare row or a spare column according to its repair strategy Control and Report (CAR): checks if this repair strategy fails If not. it will report the repair data. National Central University .

. NCU Jin-Fu Li 43 .Heuristic BIRA Algorithms Most of heuristic BIRA algorithms need a local bitmap for storing the information of faulty cells detected by the BIST circuit An A example of 4 × 5 local bitmap l f l l bi Address R1 R2 R3 R4 RAR C1 1 0 0 0 C1 0 1 0 0 C1 0 0 1 0 C1 0 1 0 0 C1 CAR 0 0 1 0 Advanced Reliable Systems (ARES) Lab. EE.

EE. NCU 44 .A BIRA Flow for Performing Heuristic RAs START BIST No Fail? Yes Local Bitmap Update p Bitmap Full? Yes Y Redundancy Allocation Jin-Fu Li No Advanced Reliable Systems (ARES) Lab..

Redundancy Allocation Rules Typical redundancy analysis algorithms Two-phase Two phase redundancy allocation procedure: must mustrepair phase and final-repair phase Must-repair phase M t i h Row-must repair (column-must repair): a repair solution forced by a failure pattern with >SC (>SR) defective cells in a single row (column).g. repair-most rule Advanced Reliable Systems (ARES) Lab. where SC and SR denote the number of available spare columns and spare rows b f il bl l d Final-repair phase Heuristic algorithms are usually used. NCU Jin-Fu Li 45 . EE.. e..

SEG: Segment 46 Jin-Fu Li SCG0 EE. National Central University SCG1 . SCG: Spare Column Group.NTHU/ADMtek BISR Scheme Redundancy organization R d d i i SEG0 SEG1 SR0 SR1 SR: Spare Row.

POR: power-on reset 47 Jin-Fu Li EE.Dedicated BISR: NTHU/ADMtek BISR Scheme BISR block diagram Q D A Wrap pper Main Memory y MAO BIRA POR BIST Spare Memory MAO: mask address output. National Central University .

48 Jin-Fu Li University .BISR Flow Power-on BISR procedure Power On Error information BIST Test Spare Row & Column BIRA Continue C i BIST Test Main Memory Error information BIRA Masked address BIRA Reduced address space Address Remapping Address National Central EE.

National Central University . then the pointers are updated to invalidate the block The system still works if a smaller buffer is allowed 49 Jin-Fu Li EE. assume that a memory with multiple blocks i bl k is used for buffering and the blocks are d f b ff i d h bl k chained by pointers If some block is faulty and should be masked. operated at down-graded mode The i Th size of the memory is reduced f th i d d For example.Degraded Performance Down-graded operation mode If the spare rows are exhausted the memory is exhausted.

National Central University .Definitions Definition Subword A subword is consecutive bits of a word Its length is the same as the group size Example: a 32x16 RAM with 3-bit row address and 2-bit column address A word with 4 subwords 50 A subword with 4 bits Jin-Fu Li EE.

we use two row repair rules complexity row-repair A row has multiple faulty subwords Multiple faulty subwords with the same column address and different row addresses Examples: subword subword Jin-Fu Li EE.BIRA Algorithm Row-repair rules To reduce the complexity. National Central University 51 .

National Central University .BIRA Procedure BIRA procedure Run BIST Detects a fault Done Stop Check Row-Repair Rules Not met Met M t Repair-Most Rules Check Available Spare Rows No available spare row Export Faulty Row Address 52 Jin-Fu Li EE.

MTDT.. et al. National Central University . 2002] Industrial case: SRAM size: 8Kx64 # of injected random faults: 1 10 1~10 # of memory samples: 534 RA algorithms: proposed and exhaustive search algorithms 53 Jin-Fu Li EE.Analysis of Repair Rate Repair rate analysis Repair rate The ratio of the number of repaired memories to the number of defective memories A simulator has been implemented to estimate the repair rate of the proposed BISR scheme [Huang.

81% 100% 100% 1MA 2MA 3MA 4MA 5MA >5MA 99 38 5 1 192 36 3 0 0 7 1 0 73 4 0 0 44 1 0 0 191 40 7 1 2 16 1 0 75 5 0 0 44 3 0 0 18 0 0 0 4 35 12 1 71 12 0 0 43 4 0 0 18 0 0 0 7 0 0 0 Jin-Fu Li RR (Best) 18.36% 98.69% 100% 100% 85.01% 100% 100% 55.14% 99.26% 36.52% 100% 100% 85. National Central University 0 4 8 12 0 4 8 12 0 4 8 12 0 4 8 12 0 4 8 12 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 69 16 1 1 46 3 0 0 18 3 0 0 8 0 0 0 6 0 0 0 45 9 3 0 18 8 0 0 7 2 0 0 5 0 0 0 1 0 0 0 32 7 2 0 13 0 0 0 7 0 0 0 1 0 0 0 0 0 0 0 .90% 99.55% 36 55% 86.81% 100% 72.38% 100% 100% 71.37% 8.81% 100% 37.91% 98.26% 100% 72.77% 99.54% 8.37% 73.09% 99.81% 100% 100% EE.17% 96.5 % 86.43% 99.10% 94.Results of Repair Rate Simulation results NSR NSC NSCG 1 1 1 1 2 2 2 2 3 3 3 3 4 4 4 4 5 5 5 5 54 RR 18.06% 97.08% 37 08% 94.10% 99.

6% HObisr: 4.5 mm2 BISR area : 0. National Central University .3 mm2 Spare area : 0 3 mm2 S 0.6% Repair rate: 100% (if # random faults is no more than 10) Redundancy: 4 spare rows and 2 spare column groups Group size: 4 G i 55 Jin-Fu Li EE.25um 0 25um SRAM area: 6.3 HOspare: 4.Test Chip Layout view of the repairable SRAM Technology: 0.

then the area cost of the BISR circuit can drastically be reduced Shared BISR techniques h d h i Reconfigurable BISR or IP-based BISR technique Advanced Reliable Systems (ARES) Lab. NCU Jin-Fu Li 56 .Shared BISR Techniques A complex SOC usually has many RAMs with different sizes Each repairable RAM has a dedicated BISR circuit Area cost is high g If a BISR circuit can be shared by multiple RAMs.. EE.

NCU/FTC BISR Scheme Reconfigurable BISR scheme for multiple RAMs RAM 1 Wrapper RAM 2 Wrapper RAM N-1 Wrapper BIST RSO ReBIRA Shift_en Register Fuse Jin-Fu Li ReBISR TDI LD Advanced Reliable Systems (ARES) Lab. al. et. ITC06] 57 . NCU TDO p Fuse Group [T. W. EE.. Tseng.

.Repair Process Test & Repair BIST BIRA Load Repair Signatures into the Fuse Group Pre-Fuse Testing Program Fuse Normal Operation Power-On Repair Signature Setup Normal Access Advanced Reliable Systems (ARES) Lab. EE. NCU Jin-Fu Li 58 .

NCU Jin-Fu Li 59 . EE..Test and Repair Mode RAM 1 Wrapper RAM 2 Wrapper RAM N 1 N-1 Wrapper BIST RSO ReBIRA Shift_en Register Fuse ReBISR TDI LD TDO Fuse Group Advanced Reliable Systems (ARES) Lab.

EE.Normal Mode RAM 1 Wrapper RAM 2 Wrapper RAM N 1 N-1 Wrapper BIST RSO ReBIRA Shift_en Register Fuse ReBISR TDI LD TDO Fuse Group Advanced Reliable Systems (ARES) Lab. NCU Jin-Fu Li 60 ..

W.. NCU Jin-Fu Li 61 . al. et. ITC06] Advanced Reliable Systems (ARES) Lab. Tseng.NCU/FTC BISR Scheme Reconfigurable BIRA architecture BIRA_en Syndrome n Multi-faults Multi faults Detector Fail_h _ FSM Syndrome Encoder Test_done Hold_l Unrepairable Shift_en k Bitmap IO_Col Address Ar+Ac Address Masker Remapping registers TDI [T. EE.

Evaluation of Repair Efficiency Repair rate The ratio of the number of defective memories to the number of repaired memories A simulator was implemented to simulate the i l t i l t d t i l t th repair rate [R.-F. IEEE D&T. Huang. EE. NCU Jin-Fu Li 62 .. 2005 (accepted) Simulation setup Simulated memory size: 4096x128 Simulated memory samples: 500 Poisson defect distribution is assumed Original yield is about 60% g y Advanced Reliable Systems (ARES) Lab. et. al.

6 99.4 67.4) (4.0) (3.6 93.0) (4.6 96.2 93 2 99.0) (1.2 83.C) (R C) 63 Advanced Reliable Systems (ARES) Lab.2) (0.2) (4.2) (2.4) (1.6 12.4 44.6 67.8 29.Repair Rate Case 1: 100% single-cell faults Repair Rate (%) p ( ) 100 90 80 70 60 50 40 29 8 29.2 57.4 62.0 44.0 83.0 87.4 87.4) (2.4 97.8 30 20 10 0 (0.8 93. 12.4 93.2 99.6 (R.2 87.4 62.4 96.4) (3.2 97.2) (1.0 RCFA Opt. NCU . EE.4) Jin-Fu Li 81.0 57.0) (2.2) (3..

2 61.4 (0.2) (1.0 44 0 96.8 61 8 44.Repair Rate Case 2: 50% single-cell faults. 20% faulty columns.2 28.2) (0.0) (2.0) (1.4) (3.0 67. and 10% column twin-bit faults Repair Rate (%) 100 90 80 70 60 50 40 30 20 10 0 81.2) (3.0) (3.. EE. NCU Jin-Fu Li .2 12.8 98. 20% faulty rows.2 85.8 99.8 98 8 94.6 96 6 98.C) 64 Advanced Reliable Systems (ARES) Lab.2 96.8 RCFA Opt.6 86.4) (R.4 12.4) (1.2) (4.4 57 4 57.0 92.6 57.8 89.8 82.0 44.4) (2.8 86.4) (4.0) (4.4 92.4 93.8 67. 28.8 61.0 82.2) (2.

13um standard cell library is used Three cases are simulated Case 1 Core 0 Core 1 C Core 2 Core 3 64x2x8 128x4x16 128 4 16 256x8x32 512x16x64 Case 2 64x2x16 128x4x32 128 4 32 256x8x64 512x8x128 Case 3 64x2x32 128x2x64 128 2 64 256x4x128 512x4x256 Advanced Reliable Systems (ARES) Lab.ReBISR Implementations FTC 0.. NCU Jin-Fu Li 65 . EE.

6 1497561 6 1528848 ReBIRA Area (um2) 18766 20303 23255 Ratio (%) 1.3 83.5 2. NCU .06 0..5 BIRA time overhead w.6 82.25 66 Advanced Reliable Systems (ARES) Lab.13 0.36 1 36 1.r. EE.Simulation Results Delay d D l and area overhead h d ReBIRA Parameter 512x16x64 512x8x128 512 8 128 512x4x256 Memory Area (um2) 1496258.8 ReBIRA Cycles 29952 30698 30404 Jin-Fu Li BIST Cycles 47939584 23605658 12013568 Ratio (%) 0. a 14N March test with solid i h d M h i h lid data background ReBIRA Parameter 512x16x64 512x8x128 512x4x256 Repair Rate (%) 83.52 Delay (ns) 2.4 1497561.25 1.t.5 25 2.

NCU/FTC BISR Scheme Layout view for an experimental case SPA ARE ROW 2 2 MEMORY 2 Advanced Reliable Systems (ARES) Lab.. EE. NCU BISR MEMORY 0 C0 C1 SPAR ROW 0 RE MEMORY 1 SPARE ROW 1 E E SPARE ROW 3 MEMORY 3 C2 C3 Jin-Fu Li 67 .

infrastructure IP cores do not add to the main functionality of the chip. and fault tolerance IP Advanced Reliable Systems (ARES) Lab.. Rather.Infrastructure IP What is Infrastructure IP Unlike the functional IP cores used in SOCs the SOCs. they are intended to chip Rather ensure the manufacturability of the SOC and to achieve lifetime reliability Examples of such infrastructure IPs Process monitoring IP. timing measurement IP. NCU Jin-Fu Li 68 . diagnosis IP. EE. test & repair IP.

IW Mem. EE. NCU Jin-Fu Li 69 . IW Mem.Infrastructure IP – STAR STAR IIP Mem. Zorian. IW STAR Processor 1 P1500 1149. ITC02] Advanced Reliable Systems (ARES) Lab.1 1 STAR Processor 2 Mem. IW Fuse Box Mem.. IW [Y.

a fuse box.Infrastructure IP – STAR The infrastructure IP is comprised of a number of hardware components. registers.. EE. and intelligent wrappers (IWs) The STAR Processor Performs all appropriate test & repair coordination of a STAR memory It is programmed by a set of instructions to control the operation of the internal modules The Intelligent Wrapper Address counters. data comparators and Add t it d t t d multiplexers Advanced Reliable Systems (ARES) Lab. NCU Jin-Fu Li 70 . including p . g A STAR processor.

Infrastructure IP – Repair Strategies Hard Repair unrepaired i d repaired Soft Repair repaired i d Powered up unrepaired Combinational Repair Powered d P d down Cumulative Repair unrepaired Hard failures repaired repaired Reliability failure p yf Powered down progressively repaired unrepaired 71 progressively repaired repaired Jin-Fu Li EE. National Central University .

J. EE.. Tseng.-W.-F. Huang.Infrastructure IP – ProTaR ProTaR [C. 2007 (accepted)] Processor for Test and Repair of RAMs The infrastructure IP is comprised of a number of hardware components.-D. IEEE TVLSI. including A P T R processor ProTaR A wrapper Features Parallel test and diagnosis Serial repair Support multiple redundancy analysis algorithms Advanced Reliable Systems (ARES) Lab. NCU Jin-Fu Li 72 . and T. Li.

and T.. 2007 (accepted)] Advanced Reliable Systems (ARES) Lab.-D. EE. Tseng. NCU Jin-Fu Li 73 . IEEE TVLSI. Huang.-W.-F.Architecture of the Proposed IIP TM_sel 2 Scan_en Scan en Scan_out Unrepair U i Done ProTaR Controller OP TM_sel Scan_en Scan_out CNT Wr rapper ERR0 TGO0 RAM 0 Global BIRA Instruction Memory ERR TGO ERRN-2 TGON-2 Shift_en Wrappe er Instr_in Clk Rst RAM N-1 [C. J. Li.

. Then the global BIRA module performs the final-repair phase of the redundancy analysis algorithm l ih Advanced Reliable Systems (ARES) Lab. EE.Multiple Redundancy Analysis Algorithms Support In the IIP. the ProTaR has one global BIRA IIP module and each wrapper has one local BIRA module mod le The local BIRA module performs the mustrepair phase of a redundancy analysis algorithm Then. NCU Jin-Fu Li 74 .

and T. alg Advanced Reliable Systems (ARES) Lab. ROW FIRST COL FIRST} . 2007 (accepted)] Jin-Fu Li 75 Global bitmap c0 1 0 0 0 c1 0 1 1 0 c2 0 0 0 1 c3 CID 0 1 0 0 R0 R1 R2 R3 RAR RA algorithm Local repair-most (LRM) alg. COL_FIRST} E ti l i ti l {FHFR. IEEE TVLSI. Li. J. EE. ROW FIRST} {COL FIRST ROW_FIRST} [C. Huang.. Tseng.Global/Local Bitmaps and RA Instructions Local bitmap C0 1 0 0 0 C1 0 1 1 0 C2 0 0 0 1 C3 CAR 0 1 0 0 r0 r1 r2 r3 RID Instructions LRM {ROW_FIRST.-D. {FHFR ROW_FIRST.-W. Column first alg. COL_FIRST} {COL_FIRST. Row first alg.-F. NCU Essential spare pivoting (ESP) alg.

Li. J. 2007 (accepted)] Jin-Fu Li 76 .Block Diagram of the ProTaR Done Shift_en Instr_in TM_sel Clk Rst CNT ERR PC CTR_P Instruction Memory BIRA OP Unrepair Scan_out Scan_en ERR Bitmap FSM Scan_out Shift_out Shift t Advanced Reliable Systems (ARES) Lab.. and T. Huang. NCU [C.-F.-W. Tseng. EE.-D. IEEE TVLSI.

-D.-F. Li..-W. IEEE TVLSI.Block Diagram of the Wrapper TGOi-1 OP TM_sel CNT Scan_en S Scan_out ERRi-1 Address Generator Data Generator CTR_W CTR W Comparator Addr_t DI_t DO_M CEN_t WEN_t Bitmap Addr DI DO TGOi ERRi Address Remapping Register DO_S DO S Advanced Reliable Systems (ARES) Lab. 2007 (accepted)] Jin-Fu Li 77 . J. NCU [C. and T. Huang. Tseng. EE.

NCU Wrapper Area 3944 gates 4825 gates 6501 gates Jin-Fu Li Area Overhead 4.1% 7 1% 78 .3% 2.6% 5.Area Cost of the Wrapper Area overhead of the Wrapper is defined as the ratio of the area of the wrapper to the area of the corresponding memory p y Experimental results for an 8Kx64-bit memory Redundancy Configuration 2R2C 2R3C 3R3C Wrapper Area 6739 gates 7342 gates 8317 gates Area Overhead 2. EE.5% 2.8% 7.8% Area cost of Wrappers for different memory sizes Memory Configuration 8K x 16 4K x 32 2K x 64 Advanced Reliable Systems (ARES) Lab..

Mem1. . (2x2). and (2x2). Mem0 Mem1 Mem2 8Kx64 8Kx64.Area Cost of the IIP An IIP for four memories is implemented The size of Mem0. Mem1. and 2Kx32.56% Advanced Reliable Systems (ARES) Lab. respectively The redundancy configurations of the Mem0. Mem2. 4Kx14.. th Th the area overhead of the IIP i only about h d f th is l b t 4. y g . (2x2). EE. and Mem3 are (3x3). and Mem3 are 8Kx64. respectively The area of the four memories is 6798472um2 The area of all the redundancies is about 896060um2 The area of the IIP is only about 309893um2 Thus. Mem2. NCU Jin-Fu Li 79 .

EE. and T. Tseng.-W. NCU [C. J.-D.. 2007 (accepted)] Jin-Fu Li 80 . Li.Layout View of the IIP Layout view of the proposed IIP for four RAMs Advanced Reliable Systems (ARES) Lab. IEEE TVLSI. Huang.-F.

.Conclusions Embedded memories represent more and more area of system-on-chip (SOC) designs f t hi d i The yield of memory cores dominates the yield of chips Various BIRA techniques have been presented Different BISR techniques for memories in SOCs have b h been presented t d Advanced Reliable Systems (ARES) Lab. EE. NCU Jin-Fu Li 81 .

M. d d i l l S. Li. Chow. 2002. d E. Wu. 5. 7. Tsai. (ITC). Li. 2003. A. (ITC). 1-8. EE. Paul.. Chen. Huang. 14. 742-745. 393-402. J. 6. Huang. Int’l Test Conf. Y. vol. pp 1135 1143 Oct 2007. “Embedded memory test & repair: Infrastructure IP for SOC yield. 10. vol.-C. 52. R. IEEE Int. Li and C. and H.”ProTaR: an infrastructure IP for repairing RAMs in SOCs. Wu. pp.-K. no 10 pp.”Built-in redundancy analysis for memory yield improvement. and C. Hsu. pp.-F. pp.” IEEE Trans. Hidaka.”A built-in self-repair design for RAMs with 2-D redundancies. Hamada. Li C. no.15. Pao. vol. and T. 2007 R.-C. Chiu. pp.13. J. 8 9. “A built-in self-repair analyzer (CRESTA) for embedded DRAMs. 4. and E. 2003.-T. T. Int’l Test Conf. J. vol. pp. R.-F. Baltimore.” IEEE Trans. Wang. (ITC).” in Proc.10.” IEEE Design and Test of Computers. C. C.-W.” IEEE Trans. (Santa Clara). (ITC). Picot. fi bl built-in lf i scheme for multiple self-repairable RAMs in SOCs. NCU Jin-Fu Li 82 .24. K. Very Large Scale Integration Systems vol 15 no. “Efficient built-in redundancy analysis for embedded memories with 2-D redundancy.-C.-W." in Proc. T. Trans Systems.-F. 8. 2006. Huang.”RAISIN: a tool for evaluating redundancy analysis schemes in repairable embedded memories. S. Huang. 386-399.349. pp.”A built-in self-repair scheme for semiconductor memories with 2-D redundancies. Ohtani. 2. Hsu.-F. K. vol.6. T T W Tseng. Niiro.-W. Wu. Kawagoe. V. Lu. J. Int’l Test Conf. 3. 386396. 2001.” IEEE Trans. Oct.-C. 2006. P. no. A. Li. and C. 567.574. 2000.” in Proc. Jan. 995-1001. C C Hsu. Sept. Ooishi. Test Conf. no.-Y. T. 2005.-H. J. Baltmore. and O. Y. Yeh. Dec. J. M. J.-H.-C. 4. no.References 1.-W. pp.-F. pp. and C. June. Very Large Scale Integration Systems. Tseng.4. Li. J. Oct. 34–42. Reliability.-F. C. Paper 30.-W. Oct. “Memory built-in self-repair using redundant words. (Charlotte). on VLSI Systems. 1.” in Proc. (ITC).-F.” in Proc. Huang. Schober. 1135-1143. Oct. pp. IEEE Int.2. Yeh.-F.-F.-W. Wu. Test Conf. Wu. Wu. C.-W. 340.-D. Tsai. H A P K Chi and E Ch "A reconfigurable b il i self-repair J F Li.-F. J. J. Advanced Reliable Systems (ARES) Lab. Yeh. C. Zorian. July-August 2007.