VERILOG SYNTHESIS USING SYNOPSYS (Sreenath Thoka, sree@iastate.

edu)

Section 1: Introduction to Synopsys Design Compiler Synopsys Design Compiler is a widely used Logic Synthesis and Optimization tool. Logic synthesis translates textual circuit descriptions into gate-level representations. Optimization minimizes the area of the synthesized design and improves the design's performance. VerilogHDL, with a few exceptions, can be synthesized into gate-level netlists composed of instantiations of standard cells. The following steps are involved in synthesis: Create a functional Verilog description (also called RTL description) of the block and verify its functionality using Verilog-XL Synthesize the functional Verilog description into a gate-level netlist composed of standard cells. This is done using Design Analyzer, the GUI for Synopsys Design Compiler. You will provide timing and area constraints to drive the synthesis. Verify functionality of the synthesized design by simulating in Verilog-XL again. Perform Timing Analysis to determine whether the design met its timing goals. If not, the design may have to be synthesized again using different constraints or the Verilog description may have to be rewritten if there are major violations in timing.

The subsequent steps consist of Automatic Place & Route (APR) and importing to Cadence for back annotation.

Section 2: Environment Setup and Preparation for Synthesis 1. The .software file in your home directory should have a synopsys entry. If its already entered, you may go to step 2 directly. If it is not, modify the .software by adding the line synopsys. Now, logout and log back in to start using Synopsys. 2. Create and change to a working directory. cd mkdir project cd project 3. Run the following from the current directory (Caution: If you run this command from your home directory, it can cause problems with the already existing cadence directory) cp $CDS_SITE/lib/pnr/pnr.tar.gz . tar xvzf pnr.tar.gz

This will create the following sub directories in the current directory cadence synopsys se verilog 4. Change to synopsys directory. You will invoke Design Analyzer from here. So your current working directory should be /home/<username>/project/synopsys Create the following sub-directories under the synopsys directory, to organize your work in a better way. mkdir sourcefiles contains source files (Verilog RTL code) mkdir netlists contains Verilog gate-level netlists generated by Synopsys mkdir db the synthesized design database (netlists in .db format) 5. Open the file named .synopsys_dc.setup in your current working directory. This is the Design Compiler setup (initialization) file. You can change the designer field if you wish to. There is one more change that you need to make. Scroll down till you find, edifout_designs_library_name = test and replace test with the name of the library in Cadence that has the behavioral view of your design.

Section 3: Synthesizing a Design Now you are ready to synthesize a design. Make sure you have the Verilog description of your design in the synopsys/sourcefiles directory. Run the following command from the synopsys directory. design_analyzer&

The Design Analyzer window appears as shown below:

1. Start by verifying the defaults in .synopsys_dc.setup file. Go to Setup Defaults. Defaults window appears. Verify the information that is pre-filled. Close the window by hitting Cancel.

Next step is to analyze the source file that contains the Verilog description of your design. But before proceeding, open the Command Window by choosing Setup Command Window. Command Window is where all warnings and errors incurred during synthesis are displayed. All information displayed by various reports and menu windows is reflected in the Command Window. Most importantly all commands entered via the menus of Design Analyzer are echoed, in proper Synopsys syntax, which means the same action can be performed by either using the pull-down menus or by typing appropriate commands in the Command Window (see, for example, Appendix B for a set of commands that can be used to set synthesis constraints). Pay attention to the information displayed in the Command Window at all times.

2. Analyze Design Choose File Analyze Go to the sourcefiles directory and select the design that you want to synthesize. Below, you will choose WORK as the library. Click OK.

The Analyze command checks Verilog syntax and Synopsys rule checking (Is the code synthesizable? If there are errors or warnings of this nature, refer to Appendix A). The intermediate files will be saved to the design library (the work directory). Click Cancel to dismiss the Analyze window. 3. Elaborate Design File Elaborate The following window appears. Scroll down the top half of the window and select WORK. Choose below, the design that you have just analyzed. Click OK.

The Elaborate command reads the intermediate files created by Analyze. Click Cancel to dismiss the Elaborate window. The Design Analyzer now displays the icon for the elaborated block. The following figure displays the view buttons that can be used to select different views for a design. (viz., hierarchy, symbol, schematic etc.)

Clicking on one of the view buttons changes the current view on the bottom right corner as shown above. Note: The Analyze & Elaborate commands can be performed in a single step by the Read command (File Read), although the Read command is more general in the sense that it can be used to read all formats (.v,.db,.edif,)

4. Optimize Design During optimization, the Design Compiler maps the elaborated design obtained from the previous step to a target cell library based on certain constraints. The design has to be constrained in terms of area and timing although timing is critical in many cases. In what follows, we shall discuss how to set up timing constraints for combinational and sequential designs. Combinational Design For circuits with combinational logic, the maximum allowable delay from inputs to outputs is specified. Do the following:

Switch to the symbol view of your design. Select the input port by clicking on it. Select the output port by clicking on it while holding the shift key (Hint: If your delay requirement from any input port to any output port is the same, you can set the constraint in one step by selecting all the input ports and all the output ports using the shift key). The lower left corner of the Design Analyzer window displays all the ports that are selected. Go to Attributes Optimization Constraints Timing Constraints. The Timing Constraints window opens.

The From sub-window shows all the input ports selected and the To sub-window displays all the output ports selected. Check the Same Rise and Fall box below. Enter the value of Maximum Delay in the space provided (the unit is nano seconds). Click Apply and then Cancel. Sequential Design For circuits with synchronous logic, you first need to define the clock. In the symbol view, select the clock input port in your design. Then, select Attributes Clocks Specify.

The Clock Name and the Port Name are shown. Set the period in the appropriate box (unit is again nano seconds). You can also change the duty cycle by dragging the falling edge of the waveform to the left or right using the mouse. Click Apply to create clock. Click Cancel to dismiss the window. Creating a clock constrains timing paths between registers within the design to be synthesized. But the paths between the input ports and the registers within the design as well as the paths between the registers within the design and the output ports are yet to be constrained. To constrain the input paths, we assume that the inputs come from an external logic triggered by the previous edge (called the launch edge) of the same clock and specify the maximum delay with respect to the launch edge (see figure below). The time left until the

current edge (called the capture edge) will then include delay through the input path (due to any combinational logic) and the set up time of the flip-flop.

Launch Edge

Capture Edge

Te Ti Te is the delay of external logic. Ti is the time left for internal logic. Ti = Tpath + Tsetup As mentioned earlier, Tpath is due to the logic, if any, between the input port and the flipflop within your design. To set the constraint on Te based on the path delay and the setup time requirement, select the input port in the symbol view and then select Attribute Operating Environment Input Delay.

Note that you have to perform this step after defining your clock. Then make your selections in the above window, enter the value for Te under Max Rise and click Apply. This defines input delay for the port selected. Repeat for all data and control inputs. Click Cancel to dismiss the window. Note: Min Rise parameter can be used to set the constraint on hold time. It is not discussed in this tutorial how this can be done. To constrain the output paths, we assume that the outputs go to external logic where a flipflop captures it on the next edge of the same clock (called the capture edge in this case). The flip-flop within your design launches the output data on the current edge (called the launch edge).

Launch Edge

Capture Edge

Ti

Te

Ti = Tclk-q + Tpath Tclk-q is the delay of the flip-flop with respect to the clock and Tpath is due to the logic, if any, between the flip-flop within your design and the output port. The constraint has to be set on Te, based on your estimate of Ti. To do this, select the output port in the symbol view and then select Attribute Operating Environment Output Delay. A window similar to the one shown above, appears where the output port is displayed on top. Select the clk from the list below, select rising/falling edge and enter the value for Te under Max Rise, click Apply. Repeat for all outputs. Click Cancel to dismiss the window.

There is an easy way to check you have everything in place before optimizing your design. The report and check commands can be used for this purpose as explained below. To verify that clocks have been defined: Select Analysis Reports. In the Report window, click Clear Choices. Under Attribute Reports, select Clocks. Click Apply. A window appears that displays information about the clocks defined in your design.

To check values specified for: set_input_delay, set_output_delay Select Analysis Reports. In the Report window, click Clear Choices. Under Attribute Reports, select Ports, then click Set Options. Select Verbose in the Constraints Options. Click OK, click Apply. A window appears that displays the input and output ports and the delay parameters that are setup for each. To check the design for consistency (e.g. multiple instantiations, unconnected pins) and to obtain information about possible timing problems in the current design (e.g. unconstrained ports/paths, unmapped cells) Select Analysis Check Design. Select Check Timing in the window that appears and click OK. A new window appears. Look out for any warnings and try to fix them before procedding with the next step.

Having set the constraints, the next step is to optimize or compile your design. Select your design and do Tools Design Optimization. The Design Optimization window appears. Use the default options and click OK. Browse the Compile Log. When you are done, click Cancel to dismiss the window. The Design Analyzer generates and displays the schematic. Use Schematic View to see the schematic. Do Analysis Report and select Area in the window. Click Apply to get feedback on the circuits area. Click Cancel when you are done. Next step is to generate the report on timing and to analyze the report to determine if all the constraints are met. If you want to save the design at this stage to simulate in VerilogXL, follow the steps given at the end of this section.

5. Timing Analysis Combinational Designs Recall how the constraints are set for a combinational design. To check if any constraints are violated, do Analysis Report. In the Report window, select Clear Choices and then select Constraints. Click Set Options and select All Violations under the Constraint Options. Click OK and then Apply. A new window (see below) displays a detailed timing report for the paths that violated the constraint. You may have to modify the constraints and re-optimize your design. Careful analysis of the individual contributions to the delay helps to modify the constraints or the optimization settings or in some cases the Verilog description of your design, to obtain better performance.

To see the timing report for the path between any input port to any output port select the input and the output ports in the Symbol or Schematic view and select Point Timing in the Report window and deselect all other choices. Click Set Options. Select Maximum under the Path Delay Type, Entire Path under the Report Points, deselect both the options under Timing to and enter 1 in the next two boxes. Click OK and click Apply. The report will be generated.

Sequential Designs We have to check if the setup time requirements are met for all data and control inputs and if the delay requirements are met for all outputs. The same procedure as explained above can be used to check if there are any constraints that are violated in which case you will have to modify your constraints. To obtain the timing report for all paths, do the following: Analysis Report. In the Report window, click Clear Choices. Select Timing. Click Set Options. In the new window, under the Path Delay Type, select Maximum and under the Report Points select Entire Path.. Select both All Register Data Pins and All Outputs. Enter a value greater than the sum of the number of all the input and output paths in your design, that are constrained. For example, for a D-flip-flop, you could constrain three paths (D,Q,QBAR). So enter 3, or any value greater than 3. If you are unsure, enter a relatively large number, such as 10. Click OK and then Apply to generate the report.

The next section discusses how to compile a hierarchical design. If you want to quit Design Analyzer, save the synthesized design before doing so. To save as a verilog netlist file, select the design and do File Save. In the new window, select netlists/ as the directory, enter the file name with .v extension, choose the file format as Verilog and click OK. To save as a database file, select the design and do File Save. In the new window, select db/ as the directory, enter the file name with .db extension, choose the file format as DB and click OK. Quit Design Analyzer by selecting Quit from the File menu. After this, you may want to browse the Verilog netlist file in synopsys/netlists/ directory.

Section 4: Compiling a Hierarchical Design Two approaches can be used to compile a hierarchical design. Top-Down Approach Typically used for smaller designs, where each sub-design is small in terms of circuit complexity and isnt aggressive with respect to timing. For example, for a design, that uses bit-slice approach (multiple instantiations of one cell), top-down approach is ideal. The general procedure is: i. ii. iii. iv. v. Read in the entire design. Resolve multiple instances Apply top-level constraints Compile Analyze results

These steps are illustrated below, using MUX41 (4 to 1 Mux) as example. It is recommended that you work through this simple example. MUX41 uses multiple instantiations of MUX21 (2 to 1 Mux). MUX41 is modeled in Verilog using the structural method. Once your have the source files for MUX21 and MUX41 in the ./sourcefiles directory, start Design Analyzer and analyze MUX21 first. If you miss this step, then when you elaborate MUX41, the Design Compiler will not be able to resolve MUX21 that is used in MUX41. After analyzing MUX21, analyze and elaborate MUX41. You will now see the elaborated blocks for MUX21 and MUX41 in the Design Analyzer window. Now, MUX41 has to be optimized using top-level constraints. Refer to the previous section for information on setting up the constraints. First, multiple instantiations of MUX21 have to be resolved. Select MUX41 and do Edit Uniquify Hierarchy. You will now see the instances of MUX21 numbered _0, _1, _2 in the Designs view. During optimization, the hierarchy can be either retained or suppressed. If you retain hierarchy, the Design Compiler will optimize each sub-design individually and combine all of them structurally to generate the actual design. Instead if you suppress the hierarchy, the design is optimized as a whole (flat design) and any redundant logic is eliminated. We shall use our MUX41 example to understand the differences. To optimize while retaining hierarchy, select MUX41 and do Tools Design Optimization and click OK. After closing the Compile Log, select an instance and switch the Schematic view to see the optimized logic for that instance. To see the schematic for the whole design, select MUX41 and go to its Schematic view. In this view, select all the instances and do Edit Ungroup. Click OK in the new window. The schematic will be displayed.

To optimize with suppressed hierarchy, we have to do Ungroup before optimizing. After elaborating MUX41, go to the Schematic view (Uniquify command is not necessary), select all the instances and do Edit Ungroup, OK. Now select Tools Design Optimization. The design is now optimized with suppressed hierarchy. It is also possible to suppress hierarchy of part of the design.

Bottom-up Approach Used for much more complex designs that are built from instances of nonidentical sub-designs, especially when each sub-design has aggressive timing. The procedure is: i. ii. iii. iv. Constrain and compile sub-designs independently Make sure all sub-designs meet their initial constraints Read in the entire compiled design and apply top-level constraints Analyze results

Appendix A: Verilog Synthesis Constructs The constructs are classified as follows: 1. Fully Supported Constructs module instantiation, with named and positional notations> integer data types, with all bases identifiers subranges and slices on right-hand side of assignment continuous assignments >>, << , ? : {} assign (procedural and declarative), begin, end, case, casex, casez, endcase default, disable function, endfunction if, else, else if input, output, inout wire, wand, wor, tri integer, reg macromodule, module parameter supply0, supply1 task, endtask

2. Partially Supported Constructs Constructs supported with restrictions on them

Construct *,/,% Always For posedge, negedge Primitive, endprimitive, table,endtable <= and, nand, or, nor, xor, xnor, buf, not, buif0, bufif1,notif0, notif1

Constraints When both operands are constants or 2nd operand power of 2 Only edge-triggered events Bounded by static variables: only use + or to index Only with always @ Combinational and edge sensitive user defined primitive are often supported Limitations on usage with blocking assignments Gate types supported without X or Z constructs

!, &&, ||, ~, &, |, ^, ^~, ~^, ~&, ~|, +, - , <, >, <=, >=, ==, !=

Operators supported without X or Z constructs

3. Ignored Constructs Constructs that are ignored by the synthesis tool <intra-assignment timing controls> <delay specifications> scalared, vectored small, large, medium specify time (some tools treat these as integers) weak1, weak0, highz0, highz1, pull0, pull1 $keyword (some tools use these to set synthesis constraints) wait (some tools support wait with a bounded condition)

4. Unsupported Constructs Constructs which if used, may cause the synthesis tool to not accept theVerilog input or may cause different results between synthesis and simulation.

<assignment with variable used as bit select on LHS of assignment> <global variables> = = =, != = cmos, nmos, rcmos, rnmos, pmos, rpmos deassign defparam event force fork, join forever, while initial pullup, pulldown release repeat rtran, tran, tranif0, tranif1, rtranif0, rtranif1 table, endtable, primitive, endprimitive

Appendix B: Basic Commands to set synthesis constraint 1. Adding an optimization constraint for asynchronous singals set_max_delay <delay> -from {input nodes} to {output nodes} The optimizer will try to optimize the paths between the input nodes given and the output ones. The unit is nano seconds. Example: set_max_delay 3 from {a b c} to {s u}

2. Adding a constraint on a clock : define the clock period create_clock <clk_name> -period time Example: create_clock clk period 10

3. Report on the area report_area

4. Report on the timing Report_timing to all_registers(-data_pins) + all_outputs() It analyzes the delays to all the registers and output. The default would only be to outputs. 5. Suppression of the hierarchy ungroup flatten -all Flatten all the design. The command ungroup can be used more specifically to suppress the hierarchy of part of the design. It can be very useful to change the hierarchy for optimization purposes.