Lab3

Lab3:NestedCircuitsinVerilog Components:Adder,multiplexer
Whatwewilldointhislab
Inthislab,wewillbuilda4bitfulladderandan8to1multiplexerinVerilogusingthenestedcircuit method.First,wewillwriteaVerilogcodethatmodelsa1bitfulladder.Then,wewillusefour instancesofthiscodetobuilda4bitfulladder.Inthesecondpartofthislab,wewilluseasimilar methodtobuildan8to1multiplexer.First,wewillgettheVerilogcodeforthe2to1multiplexerthat wehadinLab1.Then,wewillmakemultipleinstancesofthiscodetobuildan8to1multiplexerin Verilog.ThislabwillshowushowwecanbuildasmallcircuitinVerilogandthenuseitlatertobuild largercircuit(s)inVerilog.Thesearecallednestedcircuitssincethelargercircuit(4bitadderor8to1 mux)usesinstancesofthesmallercircuit(1bitfulladderor2to1mux).

StartingXilinxISE
StartXilinxISE.ClickonFileNewProject.Whenthefirstwindowpopsup,selectyourlabsfolderand writeLab3fortheprojectname.UnderTopLevelSourceType,selectHDL(HardwareDescription Language)becausewewilluseVerilog.Foryourreference,thesearethesettingsthatyouneedtouse onthenextscreen. Productcategory:All Family:Virtex2P Device:XC2VP30 Package:FF896 Speed:7 TopLevelSourceType:Usuallythisissettowhatyouselectedonthepreviouspage (SchematicorHDL). SynthesisTool:XST(VHDL/Verilog) Simulator:ISESimulator(VHDL/Verilog) PreferredLanguage:Verilog EnableEnhancedDesignSummary:Checkthebox Leavetheothertwocheckboxesattheirdefaultvalues.ClickNext.

Onthenextscreen,clickonNewSource,thenclickonVerilogModuleandgivethefilenameas myfa1b_vl(MyFullAdder1bitVerilog).Then,specifytheinputsignalsx,yandcin.Eachinputis 1bit.Also,specifytwooutputsignalssandcout.

Lab3

Xilinxhassomeoccasionalglitches.Sometimes,youmayrunyoursimulationbut,forsome reason,itdoesntshowtheresult.Ifyoufindthereissomemalfunctionintheprogramthats hardtoexplain,dothefollowing.Fromthefilemenu,clickonProjectCleanupProjectFiles. ThiswilldeleteallthefilesthatXilinxhasgenerated,butyourdesignandtestbenchwaveformfiles wontbedeleted.Youthenneedtosynthesizeagain.Thisfeaturesometimessolvestheproblem.

1bitFullAdder
The1bitfulladderaddstwobitsxandyandalsoconsidersacarryinbit,cin.Itproducesthe sum,s,andthecarryoutbit,cout.Thetruthtableofthe1bitfulladderisshownbelow.

cin 0 0 0 0 1 1 1 1

x 0 0 1 1 0 0 1 1

Y 0 1 0 1 0 1 0 1

s 0 1 1 0 1 0 0 1

cout 0 0 0 1 0 1 1 1

Truthtableforthe1bitfulladder. Thesearethelogicexpressionsfortheoutputssandcout.

s=cinxorxxory cout=x.y+cin.x+cin.y
WritetheVerilogcodethatmodelsthe1bitfulladder.Usethelogicmodeltypeofcode.Refertothe logicmodelfromLab1toseethesyntaxyouneedtouse. Inthecodeyourewriting,youneedtousethexorgate.ThisisitssymbolinVerilog:^(Shift+6).For example,inVerilog,a^b^cisusedtomodeltheexpressionaxorbxorc. Synthesizeyourmodelandcreateatestbenchfileforit.Callthefilemyfa1b_vl_test.Rememberto selecttheCombinationalclockoptionandyoumaykeepthetimeofthesimulationas1000nssincewe onlyhave8casesforthiscircuit.Makethetestbenchcasesinthesameorderasofthetruthtable.Your resultshouldlooklikethis.

Lab3

Simulationresultofthe1bitfulladder(schematic).

Submitinyourreport(Part1)
TheVerilogcodeofthe1bitfulladder Thetestbenchwaveform Thesimulationresults

A4bitadder
Closethesimulationresultscreenandthetestbenchwaveform.ClickonProjectNewSourceand,on thenextscreen,selectVerilogModule.Givethefilenameasmyfa4b_vl.Onthenextscreen,specify theinputandoutputports.Specifyaninputxthatisabusof4bits(MSB=3,LSB=0);Specifyanother intputythatisabusof4bits.Specifyaninputcinthatis1bit.Fortheoutputs,youneedtohave oneoutputbussof4bitsandanoutputcoutof1bit. IntheSourceswindow,makesureyouareintheSynthesis/Implementationmode.Rightclickon myfa4b_vlandselectSetasTopModule. Thefigurebelowshowstheblockdiagramofthe4bitadder.Noticethatwereusingxandyasthe inputs,whilethefigureusesaandb.Otherthanthat,thefigureshowsthedesignthatwewill implement.

4bitadder(Modifiedfrom:http://www.csee.umbc.edu/~squire/images/add4a.jpg)

Lab3

Now,wewillstarttowritetheVerilogcodethatimplementsthe4bitadder.Ourcodewillusethe1bit fulladderVerilogcodethatwedid,calledmyfa1b_vl.Sincethe1bitfulladderisinthesameproject folder,the4bitaddercodethatwerewritingnowcanaccessthecodeofthe1bitfulladder. ThestylethatwewillusehereistheVerilogstructuralmodelthatweusedinLab1.Inthestructural model,welookatthediagramofthecircuit(figureabove)andwecreateinstancesofthepartsthatwe see.Weusewires,ifnecessary,tomaketheconnections.Inthefigureabove,weseethatweneedfour 1bitfulladders. Tousethe1bitfulladdercodethatwehave,weneedfirsttoknowthelistoftheinputandoutput portsinorder.OpentheVerilogcodeofthe1bitfulladder.Thefirstlineofthecodethatdeclaresthe modulesnameshouldhavetheportorderasyouseebelow.Ifyouhaveadifferentorder,thenyou needtofollowtheorderyouhaveinthenextpart. // Syntax: myfa1b_vl(x, y, cin, s, cout) Now,wecancreatefourinstancesofthe1bitfulladderthroughthis: myfa1b_vl myfa1b_vl myfa1b_vl myfa1b_vl adder0 adder1 adder2 adder3 (.........); (.........); (.........); (.........);

ThissyntaxissimilartotheVerilogstructuralmodelofLab1.Here,Verilogrecognizesourcircuit myfa1b_vlandcreatesoneinstancesofitadder0.ItslikedeclaringavariableinCbyusingintx;. Thetypeisintandthevariablenameisx.Herethetypeismyfa1b_vlandthevariablenamesare adder0,adder1,adder2andadder3. Bylookingatthefigureabove,youwillnoticethatweneed3wirestousethemasthecarryoutsignal ofoneadderthatsconnectedasthecarryinsignaloftheadjacentadder.IntheVerilogcode,right underthelineoutputcout;,declarethefollowingwires: wire [2:0] w; Now,weneedtofilltheinputandoutputportsofthefourinstancesofthe1bitfulladderthatwe created.Therightmostadderwillbeadder0.Thisaddertakesasinputsx[0],y[0]andcinandproduces theoutputss[0]anditscoutwillbecomew[0].Accordingly,thecodeofadder0is: // Syntax: myfa1b_vl(x, y, cin, s, cout) myfa1b_vl adder0 (x[0], y[0], cin, s[0], w[0]); Theinputandoutputportsshouldbeinthesameorderastheyweredeclaredinthe1bitfulladder Verilogcode.Youmightnoticeweputtheheaderofthe1bitfulladderincommenttoremindusofthe portsorder. 4

Lab3

Filltheinputandoutputportsoftheremainingthreeadders.Synthesizethedesign.ClickonProject NewSource,selectTestBenchWaveFormandgivethefilenameasmyfa4b_vl_test.Onthenext screen,makesureitsassignedtomyfa4b_vl.Onthenextscreen,selectCombinational(orinternal clock)fortheclocksetting.Underthat,maketheInitialLengthofTestBenchas2000ns. Youcanchangethelengthofthetestbenchwaveformafterthefilehasbeencreatedbyclicking, fromthemenu,onTestBenchSetEndofTestBench. Now,weneedtogivevaluestotheinput.First,rightclickoneachofthethreebusesandselectDecimal (Unsigned). Openthebusthatcorrespondstoxbyclickingonit.Doubleclickontheleftmostbluesquareinit.A windowliketheonebelow(leftside)willopenup.ClickonPatternWizardandthewindowlikeinthe figurebelow(rightside)opensup.Weneedtogetthesequencefrom0to15(inbinaryfrom0000to 1111)ontheinputx.InPatternType,selectCountUp.GivetheNumberofCyclesas16,asthefigure belowshow,andclickOK. Settingtheinputofthewaveform. Openupthebusyandgiveitthesamepattern,from0to15.Youtestbenchwaveformshouldlook likethefigurebelow.

Lab3

Testbenchwaveform. Now,weneedtosimulatethewaveform.IntheSourceswindow,selectBehavioralSimulationfromthe listontop.Then,selectthefilemyfa4b_vl_test.Here,makesureyouareselectingafilewiththe extension(.tbw). IntheProcesseswindow,clickonXilinxISESimulatortoopenupthisitem.RightclickonSimulate BehavioralModel.Whenthewindowopensup,changetheSimulationRunTimeto2000ns.Double clickonSimulateBehavioralModeltorunthesimulation. Whenthesimulationopensup,rightclickontheeachofthethreebusesandclickonDecimal (Unsigned)toseethenumbersindecimal. Tomakesurethatthesimulationisshowingfully,clickonthezoomoutbuttonmultipletimes(shownin thefigurebelow).Otherwise,youcanclickontheZoomtoFullViewbuttononetime.

ZoomoutbuttonandtheZoomtoFullViewbutton Foryourobservation,rightclickonallthebusesandmakethemDecimal(Signed).Thiswillshowthe valuesindecimalconsideringtheyare2scomplementnumbers.Theadditionswillstillbecorrectwhen thereisnooverflow.Ontherightsideofthewaveform,youwillgetthecorrectcases(11=2,etc). Wegetthecorrectanswerbecause2scomplementnumbersareaddedinthesamewayasunsigned numbers.However,theoverflowconditionisdetecteddifferently.Withunsignednumbers,whenthe coutsignalis1,thereisanoverflow,butthisisnotnecessarytruefor2scomplementnumbers.On4 bits,wecanrepresent2scomplementnumberfrom8to+7.Whentheresultisoutofthisrange,there isanoverflow. RevertallthebusestoDecimal(Unsigned)andtakeascreenshotofyoursimulationresults.Compact thebusessotheansweriseasytoread. Inaddition,createanothertestforthiscircuit,calledmyfa4b_vl_test2.Run16casesofadditionsin thissimulation.Selecttheinputofyourchoice.Makesurethatsomeofthemhaveaconditionofcout=1 whileotherhavecout=0.PresentyourresultalsoasDecimal(Unsigned).

Lab3

Submitinyourreport(Part2)
TheVerilogcodeofthe4bitadder Thetestbenchwaveformthatwerequested(x=0to15andy=0to15) Thecorrespondingsimulationresultsofthetestbenchwaveform Thetestbenchwaveformthatyoucameupwith Thecorrespondingsimulationresultsofyourtestbenchwaveform

8to1Multiplexer(NestedStructuralModel)
Inthispart,wewillwritetheVerilogmodelofthe8to1multiplexer.Wewillusethesamewayasthe previous4bitaddersVerilogcode. Weneedtousethe2to1multiplexerVerilogcodethatweusedinLab1.Wewillusethefile mux21_vl1.GotothefolderofLab1andfindthefilemux21_vl1.v.Theextension(.v)isusedfor Verilogcodes.CopythisfileandpasteitintheLab3folder.Now,itsinthefolderofLab3,westillneed toaddittotheLab3project.ClickonProjectAddSourceandselectmux21_vl1.vfromtheLab3 folder. If,forsomereason,youcantlocatethemux21_vl1.vfileyouusedforLab1,thisisitscontent. module mux21_vl1(I, S, Z); input [1:0] I; input S; output Z; assign Z = (~S & I[0]) | (S & I[1]); endmodule Setmux21_vl1astopmoduleandsynthesizeitsowecanuseitinLab3. Next,clickonProjectNewSourceandaddanewVerilogmodulecalledmux81_vl.Specifyforitthe inputiwhichisabusof8bits(MSB=7,LSB=0),anotherinputswhichisabusof3bits(MSB=2, LSB=0).Also,specifyoneoutputof1bitcalledf. Thefigurebelowshowsthedesignwewillusetobuildan8to1multiplexerusingseveral2to1 multiplexers.Noticehowtheselectorlinesareconnected.

Lab3

8to1multiplexerbuiltusing2to1multiplexers. Tocreatethisdesign,youneedtomake7instancesofthemux21_vl1circuit.Youalsoneedwiresto connectthemultiplexers,asshowninthefigureabove.WritetheVerilogcodeinthesimilarstyleaswe didthe4bitaddersearlierinthislab. Rememberthattheheaderofmux21_vl1isthefollowing,whereIisa2bitinputbus,Sisa1bitinput andZisa1bitoutput. module mux21_vl1(I, S, Z); So,whenwemakethefirstinstanceofit,thisishowweshouldpasstheparameterstoit: mux21_vl1 muxl1 (i[7:6], s[0], w[5]);

Lab3

Thefirstportofmax21_vl1isa2bitbus,wecantgivetheinputsasi[7],theni[6],theyneedtobe combinedintoa2bitbus,sowegiveiti[7:6].Similarly,fortherightmostmuxinthefigureabove,you shoulddeclareitas:mux21_vl1muxr0(w[1:0],s[2],f); Synthesizeyourdesignandstartatestbenchwaveformfilethatscalledmux81_vl_test.Youmay keepthesimulationruntimeas1000ns.ConvertthebusesinthetestbenchwaveformtoDecimal (Unsigned).Forthesbus,makeitcountfrom0to7.Fortheibus,giveitthestairsshapelikeinthe figurebelow.Whens=000,onlyi[0]shouldbe1,alltheotherisignalsshouldbe0.Whens=001,only i[1]shouldbe1,alltheotherisignalsshouldbe0.Thetestbenchwaveformshouldlooklikethefigure below.Runthesimulation.Theresultsshouldlooklikethefigurebelow.Noticethattheoutputfis alwaysequalto1.Whenyoupresentyourresultsinthereport,convertthebusestoDecimal (Unsigned)andopenupthebuses.

Inadditiontothistest,comeupwithanotherwaytotestthe8to1multiplexer.Youmaydothe oppositeofthistest,whichisthefollowing.Similartotherequestedtest,makescountfrom0to7. Now,whens=000,makealltheisignals1butonlys[0]=0.So,inthistestthevalueoffshouldbe0 forallthecases.

Submitinyourreport(Part3)
9

Lab3

TheVerilogcodeofthe8to1multiplexer Thetestbenchwaveformthatwerequested Thecorrespondingsimulationresultsofthetestbenchwaveform(resultsshouldbesimilarto thefigureabove) Thetestbenchwaveformthatyoucameupwith Thecorrespondingsimulationresultsofyourtestbenchwaveform

10