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CDMA Mobile Station Modem ASIC

Jurg K. Hinderling, Member, IEEE, Tim Rueth, Ken Easton, Dawn Eagleson, Dan Kindred, Richard Kerr, Member, IEEE, and Jeff Levin, Member, IEEE

Abstract-This paper describes an implementation of a complete modulator/demodulator (modem) for use in portable and mobile cellular telephones implementing code-division multipleaccess (CDMA) digital technology [l],[2]. Key features are high circuit density and complexity, a short design cycle, flexibility, testability, and low power consumption. A universal microprocessor interface allows for efficient control, data transfer, and testability of the ASIC. The chip is fabricated in double-metal 0.8-pn CMOS and implements a mix of custom and synthesized design approaches. The power consumption is less than 350 mW at 5 V.

I. ~NTRODUCTION

S semiconductor device feature size continues to decrease, there is a continuing desire to fit the maximum amount of circuitry in one integrated circuit to make products as small as possible and to minimize power consumption. With the advent of portable cellular telephones, this need has greatly increased. The circuit presented provides the complete digital modem function required to implement the code-division multiple-access (CDMA) technology in a portable or mobile cellular telephone. The Mobile Station Modem (MSM) ASIC is partitioned into three functional subcircuits, each of which was originally designed and fabricated as a separate custom integrated circuit in a 1.2-pm CMOS technology. The layout designs of these three circuits have been integrated into a single layout design, along with some additional circuitry. The resulting circuit has been fabricated in a double-metal 0.8-pm CMOS technology. The MSM ASIC supports full-duplex voice and data communication. The forward link is defined as the one-way communication channel established from a base station to a mobile station. The reverse link is defined as the one-way communication channel established from a mobile station to a base station. The MSM simultaneously demodulates the received forward-link channel waveform and modulates the waveform to be transmitted on the reverse-link channel. The MSM interfaces with a microprocessor for timing, channel, and control information. Transmit data for the reverse link are input to the modulator through this interface as well.
11. CDMA OVERVIEW
A. The CDMA Concept

radio communications and advanced wireless technologies. The approach will solve the near-term capacity concems of major markets and the industrys long-term need for economic, efficient, and truly portable communications. With CDMA each signal consists of a different pseudorandom binary sequence that modulates the carrier, spreading the spectrum of the waveform. A large number of CDMA signals share the same frequency spectrum. If CDMA is viewed in either the frequency or time domain, the multiple-access signals appear to be on top of each other. The signals are separated in the receivers by using a correlator that accepts only signal energy from the selected binary sequence and despreads its spectrum. The other users signals, whose codes do not match, are not despread in bandwidth and as a result, contribute only to the noise and represent a self-interference generated by the system. The increased signal-to-noise ratio for the desired signal is shown in Fig. 1. The signal-to-interference ratio is determined by the ratio of desired signal power to the sum of the power of all the other signals, and is enhanced by the system processing gain or the ratio of spread bandwidth to baseband data rate. The major parameters that determine the CDMA digital cellular system capacity are processing gain, required Eb/No, voice duty cycle, frequency reuse efficiency, and the number of sectors in the cell. The CDMA cellular telephone system achieves a spectral efficiency of up to 20 times the analog FM system efficiency when serving the same area with the same antenna system. This is a capacity of up to one call per 10 kHz of spectrum. In the cellular radio frequency reuse concept, interference is accepted but controlled with the goal of increasing system capacity. CDMA does this effectively because it is inherently an excellent antiinterference waveform. Since all calls use the same frequencies, CDMA frequency reuse efficiency is determined by a small reduction in the signal-to-noise ratio caused by system users in neighboring cells. CDMA frequency reuse efficiency is approximately 213 compared to lr/ for narrow-band FDMA systems. The CDMA system can also be a hybrid of FDMA and CDMA techniques where the total system bandwidth is divided into a set of wide-band channels, each of which contains a large number of CDMA signals.

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B. System OvervieH!
The CDMA system is divided into a base station system and a mobile station system. Fully duplex communication is possible via a forward link (base station to mobile) and a reverse link (mobile to basestation). For the forward link in the mobile, digital processing occurs when data flow from the A/D converter to the demodulator

CDMA is a modulation and multiple-access scheme based on spread-spectrum communication, a well-established technology that has been applied only recently to digital cellular
Manuscript received July 25, 1992; revised November 23, 1992. The authors are with Qualcomm Incorporated, San Diego, CA 92121 IEEE Log Number 920658 1.

0018-9200/93$03.00 0 1993 IEEE

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BACKGROUND NOISE WTERNAL INTERFERENCE OTHER CELL INTERFERENCE (roc) ITHER USER I W E (BC)

Fig. 1. A view of the CDMA concept. The desired signal is selected from four different sources of interference. The dominant source is system self-interference produced by other users of the same cell. This source is controlled by closed-loop power control.

Fig. 2.

Dual-mode CDMA/FM portable block diagram.

where received data are demodulated and multipath combination is performed; then to the deinterleaver to reestablish the original data ordering; then to the convolutional decoder where the symbols are decoded and error corrected; and finally to the vocoder where the QCELP (Qualcomm Codebook Excited Linear Prediction) algorithm decodes voice data. For the reverse link in the mobile, voice data are encoded in the vocoder, sent to the modulator/interleaver where the data are convolutionally encoded, and interleaved for error protection, scrambled, direct-sequence spread, and FIR filtered.

These data are then sent to a DAC and are subsequently RF modulated and transmitted. Fig. 2 shows how the MSM ASIC interconnects with the rest of the mobile system.

111. MODEMARCHITECTURE
A . Forward-Link Demodulation

Forward-link demodulation includes the following func-

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tional blocks: a searcher, three demodulating fingers, a symbol combiner, a frequency error combiner, power control, a deinterleaver, and a Viterbi decoder [3].Each of these circuits is discussed below (refer to Fig. 3). The searcher allows the MSM to detect and lock onto a pilot signal on the forward link, and to continually search for other pilots (from other base stations) that may have better signal levels. The searcher has the ability to step through timing offsets with sufficient resolution to estimate the pilot energies at each time offset hypothesis. Each of these energies is sent back to the microprocessor over a DMA channel for evaluation. From this information, the microprocessor can choose optimal timing offsets for demodulation. Demodulation is performed using a three-finger rake-type receiver. Each of the fingers is capable of demodulating a component of a multiple-path signal, and is comprised of a complete time-tracking loop, data-demodulation, and frequency-tracking circuits. Data demodulation includes pseudorandom sequence despreading, Walsh sequence decovering, and the actual coherent demodulation. The frequency-tracking operation maintains phase coherence between the local oscillator and the pilot. Each of the fingers can track a single pilot by itself and maintains its own timing reference independent of the other fingers. At the output of each finger is a time-deskew buffer that allows each finger to time-track an average of four symbols away from the other fingers without losing data timing alignment. The symbols from each finger are realigned and then combined in the symbol combiner to form soft decision data. This increases the effective signal-to-noise ratio of the receiver because symbol energy from multiple base stations or from multiple paths occurring from a single base station are added together instead of destructively interfering with each other. The symbol combiner also maintains absolute system time and tracks the timing of the finger receiving the earliest arriving multipath component. The frequency error combiner receives an error signal from each finger that is locked onto a pilot. These error signals are combined as a measure of the phase difference of two consecutive pilot samples and reflect the phase incoherence of the local oscillator. The combined error signal biases the frequency of the local oscillator. The MSM uses two methods of transmit power control. With the first method, called open-loop power control, it is assumed that the reverse-link and forward-link channels fade equally. Here, the MSM attempts to estimate the path loss on the forward link. Based on these measurements, it estimates the power level required to transmit on the

reverse link. This method is used to rapidly adjust the mobile transmit power. Since the two links fade independently, a more accurate second method, called closed-loop power control, is used simultaneously. With this method, reverselink power control information is sent in-line, at specified intervals, with the normal symbols being transmitted on the forward link. These power-control symbols correspond to the strength of the last reverse link data received at the base station. The power-control symbols are removed from the symbol stream in the symbol combiner and replaced by erasure symbols. The resulting symbol stream is passed on to a block deinterleaver where the soft decisions are deinterleaved in the same fashion as they were interleaved at the base station according to a bit-reversal algorithm. The deinterleaver spans either 20 or 80 ms, depending upon the rate of information being transmitted on the forward link. Interleaving is standard practice to combat signal degradation due to burst errors on the channel. The deinterleaved symbols are passed on to a decoder where the Viterbi algorithm is used to near optimally decode this synchronized and quantized symbol stream. Here, the addcompare-select (ACS) array processing is performed serially with a single ACS pair in order to reduce the total amount of circuitry required. The decoder produces a high decoding gain approaching the theoretical limit for the rate 1/2, constraint length K = 9. convolutional codes used to create these symbols by the encoder at the base station. The symbols are processed and the results are stored as state metrics in intemal memory. Decisions from the ACS process are stored in an intemal path memory. A chain-back process through the path memory of depth 64 outputs a single data bit. These decoded data bits, along with quality information about the decoding process, are then transferred to the microprocessor. Since the base station sends traffic data at different symbol repetition rates and energy levels (due to voice activity driven algorithm), the decoder processes at various effective code rates (1/2-1/16) without knowledge of the actual repetition rate. Assuming packets of various repeat rates, symbols are added before decoding. Only the symbol stream that was added the correct number of times (reflecting the symbol repetition rate) before decoding will produce correct output. Through reencoding decoded data and comparison with delayed encoded data, the proper data repetition rate can be determined. Fig. 4 shows bit-error-rate curves for the forward and reverse link for the serial Viterbi decoder.

B. Reverse-Link Modulation
The time-tracking loop in the symbol combiner discussed above is responsible for maintaining reverse-link timing, which is synchronized with forward-link timing. Therefore, the symbol combiner triggers the modulation of each frame of data to be transmitted on the reverse link. Prior to each frame boundary, the microprocessor has written a packet of data into the MSM. Modulation of these data includes encoding, interleaving, scrambling, spreading, and filtering. Each of these functions is discussed below (refer to Fig. 5).

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For each 20-ms frame, the microprocessor bursts a data packet into the input buffer of a rate 1/3, constraint length K = 9, convolutional encoder. Since a variable-rate vocoder may be used, the size of the data packet may vary. As described for the forward link, the encoder is programmed by the microprocessor to repeat code symbols for data rates less than 9600 b/s. The packet size, times the symbol repetition rate, times three symbols per bit, always produces the same number of code symbols per frame. The code symbols are then passed through a block interleaver which spans one 20-ms frame. The interleaver memory is organized into rows and columns. Symbols are written into the interleaver's memory in column major and read out in a modified row major. The order of the rows read is a function of the data rate of this packet, and the channel type. The writing operation is done in bursts, which disposes the need for a second block of memory. For rates other than 9600 b/s, data must be grouped into sets of unique (nonrepeated) symbols, followed by one or more identical sets of symbols, depending upon the data rate. Each set of unique symbols is found by selecting the proper set of rows. The interleaved symbol stream is then converted into a set of orthogonal functions. The orthogonal modulation is 64-ary, so each set of six interleaved code symbols, known as a Walsh symbol or modulation symbol, maps to a 64-b Walsh function. This stream of Walsh chips is then scrambled by BPSKspreading it with a pseudorandom sequence of bits produced

by a 42-b pseudonoise (PN) sequence generator operating at 1.2288 MHz. This serves to add privacy to the conversation while spreading the transmit waveform. After the modulated symbol stream is BPSK-spread, it splits to form an I-phase and a Q-phase path for OQPSK signaling. The I - and Q-phase paths are each spread with an independent PN sequence produced by two 15-b PN generators programmed with different polynomials. Both PN generators are presettable to a specified state, upon which they commence to cycle through a full 215 states. The extra PN state was inserted (PN sequence lengths are normally 2" - 1 where n = number of shift registers) so that PN sequence boundaries align with transmit and receive frame boundaries. To reduce the power required to transmit on the reverse link, redundant data (present during data rates slower than 9600 b/s) are not transmitted. Symbols are read from the block interleaver in a fashion which collects redundant data into groups. A data-burst randomizing algorithm uses the 42-b PN generator described above as the source of data to pseudorandomly gate the transmit data stream on and off so no redundant data passes. Two 48-tap finite impulse response (FIR) filters are included in the MSM, one for the I-phase data stream and one for the Qphase data stream. These filters sample at four times the data stream frequency, have symmetrical coefficients, and attain a stopband rejection of -42 dB. The incoming binary data streams are gated with the output of the data-burst randomizer to form ternary values. Products are formed by multiplying FIR filter coefficients with the incoming ternary values. Each product is then added to a delayed sum of products from previous stages. The outputs of the two filters are truncated to 8 b and multiplexed onto a common set of output pins.

IV. DESIGNGOALS The three main modem functions (demodulator, modulatoddeinterleaver, and decoder/encoder) had previously been integrated into three separate CMOS integrated circuits for use in the first-generation CDMA mobile telephone [4]. The MSM ASIC's design goals were broadly stated as follows: 0 Quick integration of existing chip-set and additional signal processing capabilities into a single chip to: 1. lower production cost of CDMA modem function by tracking process technology and adopting a 0.8-pm feature size; 2. allow the rapid design of a handheld portable dualmode FM/CDMA telephone with a minimum of external digital circuitry; 3. minimize overall power consumption by minimizing the number of I/O pads and miscellaneous design optimizations to maximize battery life and increase talk time. 0 Reuse existing logic and layout as much as possible. 0 Stay multifoundry based through broad technology specification and flexible (parameterized) design methodology. This presents a definite business advantage, both technologically and financially.

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0 Maintain testability of the three modem functions as separate blocks. Reuse prior test vectors as much as possible to leverage from previous design efforts. By means of two external test pins the chip can be put into four different test modes redefining the function of certain 1/0 pads. 0 Build and simulate a database that minimizes computer resource needs and allows for quick layout and simulation modification. This means extensive use of functional simulation models and block compilers or layout synthesis.

I ) Layout Design Approaches:


use of a custom design library composed of hand-crafted cells and custom layout-module compilers for the most frequently used and modified components such as I/O registers, I/O pad-ring, accumulators, FIR filters, and various PN and binary counters, schematic-driven place-and-route (standard cell) layout; high-level model-language-driven layout synthesis. For many functional blocks hand-crafted layout showed a distinctive density advantage versus a standard cell implementation with the library available at the time. On the MSM ASIC, a typical standard cell block derived from schematics or through synthesis featured a density of 0.4 mil2 per transistor, whereas custom layout including block routing overhead produced a density of 0.28 mil2 per transistor. As higher density standard-cell libraries and fabrication processes with three or more layers of metallization become available, the synthesis approach will clearly emerge as the most attractive one. Not only is it likely to surpass block-routed custom layout in circuit density, it is also the most desirable approach regarding data base management. 2 ) Clocking Scheme: A simple two-phase nonoverlapping clock was employed [ 5 ] . Feedback routing RC delays from distant circuit nodes are used to insure nonoverlapping clocks. This allows control of the design margin in the clock generators themselves. Two clock lines must be routed; local clock inversion, however, is not necessary and minimizes capacitive loading. To limit clock line capacitances to reasonable numbers, several independent synchronous two-phase clock subsystems derived from the same single-phase clock are implemented inside the MSM ASIC. Signals passing from one subsystem to another are properly pipelined to avoid malfunction due to some inevitable skewing of the same clock edge in different clock subsystems. Fig. 6 shows a block diagram of the clocking circuit. In low power standby mode the system clock is turned off (SYS-CLKINABLE); for debug and scan operations the system clock can also be exercised through the microprocessor interface (USEMICRO-CLOCK, MICRO-CLOCKINPUT). Fig. 7 depicts the clock waveform of a major clock net as simulated with SPICE after a clock tree RC extraction. 3 ) Uniform Storage Element: A standard ratioed latch cell consisting of four transistors was used chip-wide to implement sequential logic as well as static RAMS. Fig. 8 shows the standard latch and RAM cells used. A full latch is composed of two back-to-back half-latches clocked by the nonoverlapping clock phases, whereas RAM cells consisted of six transistors. Optional input buffering avoids malfunction of the latch due to skewed driverhoad resistance ratios. The resistance ratios of the weak feedback inverter were chosen such that an unbuffered latch could tolerate a routing resistivity of up to 20 kR and still function properly. As the modem algorithms described above suggest, there are a variety of frequencies at which circuits in the MSM must operate. Instead of routing many different two-phase clocks at various frequencies throughout the chip, only one two-phase clock was routed,

V. IMPLEMENTATION A . Simulation and Verification


Most system-level verifications were performed by means of C-based simulations. Since our mixed-mode circuit simulator accepts functional models also in a C-based syntax, it was possible to embed system or subsystem level C programs into the circuit modeling and simulation environment. The simulations were driven by a command language file interpreted by the main stimulus module. This provided for a compact user interface with a high-level macro command set. The proper timing sequences for microprocessor readiwrite, scan-iniscanout, or other high-level operations are executed by the macro commands. Hardware netlists and software models of the major architectural blocks were developed in most cases (except for purely synthesized circuits for which the model program code itself is the definition of the simulation netlist) by separate teams. At certain levels the functional pin interfaces were defined and the lower level details were implemented in each domains optimal manner. This dual approach guarantees high probability of functional correctness if these two independent implementations of the same function match. Prior design experience mandated heavy use of functional models to minimize simulation time. For the same reason, only functional simulations were performed at the chip top level. Subsystem circuit netlists were verified one at a time (up to 30 000 transistors), once as a model, once as a transistor layout netlist, and compared. True speed performance of the subsystems with regards to temperature and voltage was verified by running circuit simulations on a lower level. Given the criticality for early system and software tests, an MSM hardware emulator consisting of the three previously designed CDMA ASICs and additional FPGA circuitry was developed. This allowed early actual system tests while the ASIC was still in development. The hardware emulator can be physically mounted onto the prototype tester so that simulation vectors can be compared with the emulator while an ASIC is being developed.

B . Layout Implementation Details


Since the MSM is a device with potential for high volume production, it was important to adopt a conservative and robust circuit design style. The design is fully static and is to be producible on mainstream commercial processes. No exotic circuitry was employed. Four strategic implementation issues are discussed below:

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Fig. 6.

Block diagram of the clocking circuit

Fig. 7. HSPICE simulation of a clock net with a distributed capacitance of 120 pF and a total wire length of 3.9e + 5 j m i . TN/TF' driver transistor widths are 1170/2660 pm. Signal LAT-OUT is the output of a toggle latch clocked with the worst-case clocks PHIIFB/PHI2EB at the end of the clock string. Margin between p h i l f b / p h i 2 A overlap and latch switching level is 870 mV at 135OC.

with a frequency of 9.8304 MHz. All latches are clocked by this system clock, and enabled (via a second in-series pass transistor) by an additional signal which operates at the desired frequency of the specific latch, yet has an active time equal to the width of the system clock. 4 ) SignallPower Routing: Outside hand-crafted leaf cells no manual routing was employed. This allows for quick circuit changes and absolute repeatability over different routing iterations. Most automatic block routers lack a fine level of control, so the route efficiency was very dependent on a good seed placement and power net distribution.

A common asynchronous 8-b microprocessor bus is routed throughout the MSM. Interfacing between the microprocessor and the MSM is achieved through a set of microprocessor registers which are either written with respect to microprocessor timing and read with respect to chip timing, or vice versa. An understanding of when each of these may occur prevents any conflicts. When a microprocessor operation must trigger a chip function, this event is detected on the microprocessor bus and then synchronized to chip timing. Periodically, chip operations must trigger a microprocessor function. This is achieved through the microprocessor interrupt mechanism.

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C . Testability
Through special test pins the MSM device can be put into several test modes which redefine the function of certain I/O pins. This method allows functional testing of subblocks from the device pins to main intemal node points otherwise not accessible. The following test modes are defined: modem (default by intemal pull-up), demodulator, interleaver/deinterleaver, convolutional decoder. Test vector sets are therefore partitioned to test the above specified functions separately. The advantage of this scheme is hierarchical direct testability access to the modems main functional blocks. Disadvantageous is the fact that major parts of the ASIC are idle in each test vector set; concurrent test efficiency is low and this tends to increase the size of the overall test vector set. The total production test vector size for the MSM is just below 512K. Circuit controllability/observability is achieved through the microprocessor interface. Scannable latches have been incorporated into circuits where controllability and/or observability is required to make the device testable. These scan latches are serially linked into one or more scan paths. Upon control of the microprocessor, these scan paths are shifted through a microprocessor register. This allows observability and controllability of the scanned latches. The MSM contains a total of 550 scannable latches in ten scan paths. Fig. 9 depicts a standard 1/0 scan latch structure. Future implementations of the modem will include the IEEE Standard Test Access Port and Boundary-Scan Architecture. Scan paths can be inherently inefficient when it comes to testing RAMs, however. Several of the RAMs in the MSM can be put into a RAM test mode, in which values written from the microprocessor control the RAM data input, address, and

Fig. 10. Mask plot of MSM chip.

control signals such as chip-select and write-enable or readenable. Microprocessor registers can also be read to obtain the data stored in the RAM. The address space has been configured so several RAMs may be written or read simultaneously, greatly decreasing test time. Signature analysis is another method employed within the MSM hardware to verify the functionality of certain building blocks.

VI. ASIC STATISTICS


The MSM contains 450 000 transistors, which includes 28000 bits of static RAM and 70000 gates. The die is 410 mils by 420 mils and is packaged in an aggressive thin quad-flat-pack with pins on 20-mil centers. Maximum power consumption is less than 350 mW at V d d = 5 V. Provisions have been incorporated in the design to allow for 3-V operation with one mask change. The technology used is a 0.8-pm, double-metal, n-well CMOS process. Metal pitches used are 1.2 and 1.8 pm. The approximate number of vectors to test the MSM chip is 512000. Refer to Fig. 10 for a mask plot. The design, layout, and simulation of the original three separate CDMA ASICs were performed by 15 persons in 16 to 18 months. The integration of these circuits into the MSM chip, including the addition of several ancillary circuits and

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simulation of the top-level, was performed by five persons in six months. The ability to perform at this level was due in part to a well-integrated and sophisticated tool set that allowed high-level logic synthesis and the ability to integrate different design philosophies into a common design arena.

Tim Rueth was bom in Jefferson, WI. He received the B.S.E.E and M.S.E E. degrees from the University of Wisconsin, Madison, focusing on computer engineenng and VLSI design. He then worked for Hewlett-Packard for six years before joining Qualcomm Incorporated, San Diego, CA, where he has now worked for three years.

VII. CONCLUSIONS An entire CDMA digital modem circuit for a cellular telephone has been implemented as a single integrated circuit. An efficient design cycle was realized thanks to a wellintegrated tool set that supports differing design philosophies, technology independence, and allows high-level algorithms to be synthesized. Testability overhead was managed by an efficient use of scan paths and a parallel microprocessor interface.
ACKNOWLEDGMENT
The authors wish to acknowledge the superb technical expertise and excellent contributions of all members of the CDMA project team that led to the successful completion of the MSM chip development.

Ken Easton received the B.S. degree in engineering from Harvey Mudd College, Claremont, CA, in 1989 and the M.S. degree in electrical engineering from Stanford University, Stanford, CA, in 1990. Since joining Qualcomm Incorporated, San Diego, CA, in 1990, he has worked as an ASIC designer, primarily for CDMA cellular.

REFERENCES
K. Gilhousen et al., On the capacity of a cellular CDMA system,

IEEE Trans. Veh. Technol., vol. 40, no. 2, pp. 303-312, May 1991.
An overview of the application of code division multiple access to digital cellular systems and personal cellular networks, submissions to the Cellular Telecommunications Industry Association (CTIA) CDMA Technology investigation subcommittee, Qualcomm Inc., San Diego, CA, Apr. 21, 1992. [ 3 ] A. J. Viterbi and J. K. Omura, Principles ofDigitul Communication and Coding. New York McGraw-Hill, 1979. Fitndamenras and L4i S. Lin and D. J Costello, Error Applications. Englewood Cliffs, NJ: Prentice-Hall, 1983. [5] L. Glasser and D. Dobberpuhl, The Design and Analysis of VLSI Circuits. Reading, MA: Addison-Wesley, 1985, pp. 33 1-335. [6] Proposed EIA/TIA Interim Standard, Wideband spread-spectrum digital cellular dual-mode mobile station-base station compatibility standid, Qualcomm Inc., San Diego, CA, Apr. 21, 1992. CDMA Mobile Station ASICs Specification, Qualcomm Inc., San Diego, CA, Aug. 1991. CDMA Mobile Station Modem (MSM) ASIC specification, Qualcomm Inc., San Diego, CA, June 1992.

Dawn Eagleson received the B.S.E.E. degree from the University of Califomia, San Diego, with emphasis on device physics and VLSI design. She worked for Unisys for six years in standard cell library design and development and has worked at Qualcomm Incorporated, San Diego, CA, for three years designing custom ASICs.

Dan Kindred, photograph and biography not available at time of publication,

Richard Kerr (M92) received the B.S. degree in physics and the M.S.E.E. degree in computer system engineering from San Diego State University, San Diego, CA, in 1974 and 1983, respectively. His career spans nine years at Naval Ocean Systems Center (NOSC) San Diego in physics research, four years at Linkabit in systems design and VLSI design, and six years at Qualcomm Incorporated, San Diego, CA, in ASIC design and management.

Jurg K. Hinderling (S77-M79) received the M.S. degree in electrical engineering from Swiss Federal Institute of Technology in Zurich, Switzerland, in 1976 and the M.S. degree in computer science from Union College in Schenectady, NY, in 1979. After working with RCA Laboratories in Zurich, Switzerland (19761978). Burroughs (Unisys) in Danbury, CT (1979-1981), Linkabit Corporation in San Diego, CA (1981-1986), General Instrument in San Diego, CA (19861988), and Landis & Gyr Corporation, Zug, Switzerland (1988-1990) he has been with Qualcomm In(:orporated, San Diego, CA, since 1990 and is involved in ASIC design for Qu;ilcomms CDMA technology.

Jeff Levin (S83-M83) received the B.S.E.E. degree in 1983 from the University of Califomia, San Diego. He worked from nine years at Superset, Inc. in San Diego, CA, designing hardware and software for computer graphics. He has been with Qualcomm Incorporated, San Diego, CA, since 1990, working on hardware, software, and ASIC design for Qualcomms CDMA technology.

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