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Fine-Pitch Capabilities of the Flat Ultra-Thin Chip Packaging (UTCP) Technology

Jonathan Govaerts, Erwin Bosman, Wim Christiaens, and Jan Vaneteren, Member, IEEE
AbstractThis paper describes the ne-pitch interconnection capabilities of the ultra-thin chip packaging (UTCP) technology, a technology under development for embedding thin chips in a exible polyimide (PI) substrate. It allows for fully exible elec, at which tronics, as the rigid chips are thinned down to 2030 point they become truly exible themselves. This way, instead of just a exible substrate with rigid components assembled on top, the entire circuitry can be incorporated inside a 3040 thin chip package. The paper briey introduces the technologys background with a short description of the fabrication process. Building on the developments already achieved, some further optimizations are discussed, and the technology is tested for its ne-pitch interconnection capabilities using test chips with four-point probe and daisy chain patterns, with a pitch down . The possibility to package several chips in the same to 40 substrate is investigated, as well, and nally an outlook on future experiments is briey discussed.

Fig. 1. Process ow for the at UTCP technology used.

Index TermsChip embedding, ne-pitch interconnection, exible polyimide substrates, thin chip packaging.

I. INTRODUCTION HESE DAYS, there is a lot of interest in making electronic devices as light and compact as possible, as the electronics market is rapidly expanding with all sorts of portable devices for everyday use. In this view, exible substrates are often an interesting alternative for rigid printed circuit boards (PCBs) because they are light and conformable, especially an advantage when integrating electronic devices for wearable applications. A light and exible substrate by itself however does not guarantee a light and exible end result. The exibility is often drastically reduced when rigid components are assembled onto the substrate. Thus, considering the current trend of increasing component density, which is of course welcomed for wearable devices, the benet of the exibility of the substrate is more and more overshadowed by the rigidity of the components. An obvious way of tackling this issue is to use smaller and thinner, and consequently also lighter, components.
Manuscript received September 08, 2008; revised February 17, 2009. First published June 12, 2009; current version published February 26, 2010. This work was supported by the European Union through the programs FlexiDis under Contract IST-004354 and SHIFT under Contract IST-507745. This work was recommended for publication by Associate Editor R. Mahajan upon evaluation of the reviewers comments. The authors are with the Centre for Microsystems Technology (CMST), IMEC, B-3001 Leuven, Belgium, and also with the Department of Electronics and Information Systems (ELIS), Ghent University, B-9000 Ghent, Belgium (e-mail: jonathan.govaerts@UGent.be). Color versions of one or more of the gures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identier 10.1109/TADVP.2009.2018134

However, when chips are thinned down to approximately , they are too fragile to be assembled onto a substrate 20 with standard die assembly techniques (at present). Recently, a technology for embedding such thin chips in exible substrates has been developed at IMEC [1]. This technology embeds these fragile ultra-thin chips in spin-on polyimide (PI) substrates, and is therefore called ultra-thin chip packaging (UTCP). It offers the possibility of reducing weight, while at the same time enhancing the mechanical exibility of the electronic circuitry. II. FLAT UTCP TECHNOLOGY DESCRIPTION The technology used here is an enhanced version of IMECs rst UTCP technology with an updated process ow to realize a more symmetrical package. The process ow used is depicted in Fig. 1. The base PI layer is spincoated onto a rigid (glass) carrier substrate and cured. Then, the photodenable PI is spincoated, illuminated through a mask, and developed to dene the chip cavity. After curing, the chip is placed face up, using BCB in the cavity as adhesive. The BCB is cured, and the top layer of PI is spincoated and cured in the same way as the base PI layer (thus creating a symmetrical substrate sandwich). The via holes to the chip contacts are laser drilled and after the metal pattern is realized on top, the substrate can be released from its carrier. The fabrication process for this technology has been described extensively in [2], together with the rst electrical results for the coarser interconnect pitch patterns. III. TEST CHIPS DESCRIPTION The chips used for the embedding trials are thinned-down test chips available at IMEC. They are specied as PTCK chips, which stands for Packaging Test Chip version K, and measure 5 mm 5 mm. There are four different versions of PTCKs, but

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Fig. 4. Optimized UTCP release: formerly by cutting out the middle part (adhesion promoter applied at the sides of the glass carrier, left picture), currently the glass can be reused after release of the UTCP (right picture).

Fig. 2. Layout of the PTCK chips (at the periphery): three pitches 100, 60, and 40  , and a zoomed view of the different interconnection schemes on the right.

V. FABRICATION PROCESS AND OPTIMIZATIONS As said, the fabrication process is thoroughly elaborated in [2]. Some optimizations have already come up in the meantime, however. In the original process, adhesion promoter was used at the sides of the glass carrier to prevent foreseeable curling of the substrate (due to coefcient of thermal expansion (CTE) mismatch). At the end of the process, the middle area was then cut out for release. However, it was found that, in this case, the adhesion promoter is not necessary and the processing can be done on the bare glass carrier without risking a premature release. Moreover, this means the glass carrier is no longer wasted since it might be reusable after cleaning. This is illustrated in Fig. 4. It is also very important to carefully match the chip to the cavity in the PI, for the mechanical robustness (it is preferable in this sense to have smooth layers rather than edges and singularities where stresses are focused), but especially for the metallization afterwards. The matching has to be done both in the lateral dimensions and in thickness. The thickness of the photodenable layer can be reliably adjusted by changing the spinning parameters. For example spinning at 4000 rpm results in a , better 26- -deep cavity, and 4250 rpm corresponds to 24 suiting the 20 thin chips. The spin speed curve, as supplied by HD Microsystems, is given in Fig. 5 and can be used to match cavity depth to chip thickness. The placement of the chip has also changed, from using a complex setup involving a mask aligner equipped with a vacuum holding mask, to a more straightforward manual placement with tweezers under the microscope. The latter technique is easier and faster by far, but it should be mentioned that it is less accurate and somewhat more chips get damaged during handling. As pointed out already in [2], a lot of problems occur at the chip-cavity interface, where any gap causes difculties for the metallization that has to bridge this gap. This issue is evidently more common in the ner pitch patterns. Therefore, this phenomenon at the cavity interface results in limitations to achievable minimum track widths and spacing at the gap crossing. It can be considseems that for the described technology, 40 ered the lower limit for the achievable pitch, as at this point, it becomes a problem, even when optimizing illumination and developing times.

Fig. 3. Interconnection test principle.

all have the same peripheral bond pad layout, which is all that will be used in the tests described in this document. This bond pad layout, and how they are connected, is shown in Fig. 2. As there are different pitches of output pads available, contact measurements can be done from 100 and 60, down to 40 pitch patterns. The metal pattern on the chip allows for daisy chain testing as well as four-point-measurements for contact resistance. These chips have been thinned down at IMEC from about to approximately 20 and are at that point so thin 500 that they become somewhat transparent. The bond pads of the , test chips have been bumped with NiAu, approximately 5 acting as a buffer layer for the laser drilling, to protect the Al contacts. IV. TEST MEASUREMENT SETUP To test the feasibility of the technology a design for the metallization was made based on the layout of the used test chips. The metal on the substrate is to be patterned so that, tting the test chips, a daisy chain (DC) can be measured at several points, as well as contact resistance with a four-point-probe method (4PT). The principle is illustrated in Fig. 3. The peripheral interconnection patterns are designed with ), tting the several pads several pitches (100, 60, and 40 available on the test chips. The bondpads are, respectively, 70 , 40 40 , and 30 30 . 70

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TABLE I 4PT-MEASUREMENTS FOR THE 100 

m PATTERNS

[
]

TABLE II DC-MEASUREMENTS FOR THE 100 m PATTERNS [

]

Fig. 5. Spin speed curve for the photodenable PI HD7012: useful for matching chip thickness and cavity depth.

TABLE III 4PT-MEASUREMENTS FOR THE 60 m PATTERNS [

]

Fig. 6. Laser drilled via holes in the top PI layer: from a single via for each contact (left), to a number of parallel vias, 2 2 and 3 3, to reduce contact resistance (right).

One more remark concerns the laser drilling process, where vias are drilled through the top PI layer to the chips contacts. As the via holes drilled with the YAG laser are very small, 12 on average, there is room for several vias on the larger contacts of the test chips. Therefore, for the different bond pad sizes and using always the same vias and laser settings, the interconnection was optimized by introducing an array of 2 2 and 3 3 vias for the 60- -pitch and 100- -pitch contacts, respectively. This is illustrated by the pictures in Fig. 6.

VI. MEASUREMENT DATA The electrical measurements done on the coarser UTCPs, patterns, can be found in Tables I packaged with the 100 and II. DCx-y in Table II means that the resistance between the contact pads marked with DCx and DCy has been measured. Please note that DC87 is mentioned twice in Table II, and

it should be mentioned that the four-point measurements are uncomfortably close to the lower limit of the range of the used measuring equipment, meaning that it is signicantly below . These measurements are repeated from the previous 10 article [2]. The rst batch contained 15 substrates, of which four failed in the course of processing. Each substrate was patterned with four four-point-probe patterns, and one complete peripheral daisy chain, measurable at eight contacts. The batches used here for characterization still suffered from some problems bridging the gap at the chip-cavity interface, explained in [2]. This means not all patterns on all substrates have been measured, as indicated in the second column of the tables. Table I shows consistent results for the contact resistance of . This represents the contact resistance of nine parallel via holes. Table II learns that the metallization on the UTCP (67- -thick Cu), as measured in DC7-6, DC5-4, and DC3-2, has a somewhat larger resistance value per square, being . Using these gures, and approximately the measurements in Table II, a recalculation results in a value for the on-chip metallization resistance of, again approximately, , which is acceptable for the standard metal (aluminum) layer of the test chips. patterns and Similar measurements were done for the 60 patterns, and the results are listed in Tables IIIVI. the 40 Similarly as above, results for contact resistance, UTCP metallization resistance and on-chip metallization resistance can be deducted from the numbers in the tables. All this is summarized in Table VII. These results in Table VII seem to be consistent. On the one hand, the resistivity of the UTCP and chip metallization is com-

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TABLE IV DC-MEASUREMENTS FOR THE 60 

m PATTERNS

[
]

TABLE V 4PT-MEASUREMENTS FOR THE 40 m PATTERNS [

]

TABLE VI DC-MEASUREMENTS FOR THE 40 m PATTERNS [

]

might be an important enabler for industrial mass-production of UTCPs, where several ultra-thin chips could be embedded using large carrier-substrates. Then further processing is done simultaneously on all embedded devices at once, and nally, the substrate can be separated. This is a common technique similarly practiced in e.g., at-panel display fabrication. In this context of at-panel displays, and especially for exible displays, the UTCP technology could also be applied to embed thinned-down functional driver chips directly in exible (PI) display substrates. This would also require embedding several driver chips in the same substrate, and it is a very attractive possibility, especially considering the fact that this could be developed to be compatible with Philips EPLaR technology (Electronics on Plastics by Laser-assisted Release), where exible displays are being made on an industrial scale with very thin PI backplanes [4]. The idea here is to embed several chips in the same PI substrate sandwich. With the feasibility of the technology proven to , as reported above, work at chip bump pitches down to 40 the alignment possibilities when placing chips needs to be investigated. In this view, the at UTCP technology is interesting in such a way that it offers the possibility of photolithographically dening all the cavities, wherein the chips are to be placed, at the same time in one masked illumination step. If the chip then adequately matches the dimensions of the cavity, the placement error should be small enough to ensure good alignment between the (in the cavity) placed chips, and the chips can be interconnected by the routing layer on top. A. Setup and Design The test has been set up with four chips, again PTCK chips as described earlier, to be embedded and interconnected in the same substrate. The chips are placed in cavities in the four corners and the layout is designed to form two daisy chains on each separate chip. Additionally, a daisy chain runs between each two neighboring chips. The mask designs are shown in Fig. 7. The trials have been designed for the (coarsest) chip pitches of 100 . B. Fabrication The whole fabrication process is evidently very much the same, with one (minor) difference being the plating area, resulting in different plating parameters. Here, the plating area is approximately 1 , and plating at 100 mA for 10 min gave satisfying results of approximately 6- -thick Cu. Another difference is of course the location of the chips: in the single chip setup, the chip was placed in the middle, whereas in the case of multiple chips, they are located outside of the center. This might have implications when spincoating the top PI layer. To minimize the risk on introducing any possible marks degrading the uniformity of the top PI layer during spinning, the PI is applied with a pipette and spread out carefully, making sure all chips are covered before the spinning cycle is initiated. The rst results for embedding multiple chips are promising. A number of problems did arise during processing, such as a substrate table lagging behind during laser drilling, a cavity design not matching the metallization design mask and chip

TABLE VII OVERVIEW OF RESISTANCES IN FLAT UTCP PACKAGING TRIALS

parable for the different pitches.1 On the other hand, the values obtained for the contact resistances of the different pitches, can be recalculated for comparison: while the 40 pitch contacts plated vias, the 60 pitch contacts consist of single 12.5 consist of 4 (a 2 2 array) of the same vias, and similarly the 100 pitch contacts consist of 9 (a 3 3 array) of those vias. Ideally, this would mean that the 4 (respectively 9) parallel vias pitch contacts, should show 4 of the 60 (respectively 100) times (respectively 9 times) less resistance than the single vias. VII. MULTIPLE CHIP ALIGNMENT Apart from the ne-pitch capabilities of UTCP technologies for embedding single chips, it is at least as valuable to know what its alignment capabilities are for integrating several chips within the same substrate [3]. This could be interesting as it
1Fortunately, as these values are independent of the UTCP test design and are only linked to the thickness of the metallization layers.

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Fig. 9. Alignment of the chips at the four corners to the metallization is sufcient for interconnection. Fig. 7. Mask layouts for multiple chip embedding: the cavities (upper left), metallization layer (upper right) and soldermask (below left); additionally the design of the upper left corner is shown more in detail (below right).

100 pitch. The current accuracy is limited by the manual placement of the chips to somewhere in the range of tens of microns: the cavities are necessarily somewhat larger than the chips due to the rounded corners of the cavities, as shown in Fig. 10. Since there is a gap in the range of 2030 in-between chip and cavity wall, the misalignment, worst-case, . Of course, can be as bad as twice this distance, so 60 by checking the result under a microscope and manually adjusting the placement under a microscope, it is easy to prevent such a worst-case scenario, and to reduce misalignment to 30 and lower. Approximative values for the misalignment errors in Fig. 9, clockwise from the upper left, are given in Table VIII. Based on the above reasoning, the accuracy might denitely be enhanced with more advanced (read: more accurate) pick-and-place equipment, with current accuracies easily , even down to submicron accuracies [5]. reaching below 10 Electrical measurements also conrm the feasibility of this technology, although so far only one substrate has been completed and measured. The measurements are given in Table IX. Two daisy chain structures, namely DC1_23 and DC1_34 could not be fully measured due to the fact that a few interconnection tracks were interrupted at the chip cavity interface, due the same phenomenon of gap-bridging difculties as described in [2]. The verication column in Table IX (Theoretical Value column) shows what the expected value is for the resistance, based on earlier results from the UTCP measurements with pitch contacted thin chips, as given higher in Tables I 100 for the contact resistance, and VII. These values are 2 for the resistance of the UTCPs Cu metallization, 3 and 34 for the resistance of the Al metallization on the chip. Comparing the second and last column in Table IX, a good correspondence can be noted between the theoretically expected values and the measured ones.

Fig. 8. Several pictures of the fabricated substrates with embedded chips: a placed chip (top left), 4 embedded chips interconnected by the Cu metallization layer (top right), a close-up (bottom left) and the end result, with soldermask and NiAu nish (bottom right).

breakage during placement, but all these could be overcome. To give an idea of the result, some pictures of the fabrication can be found in Fig. 8. C. Results The result, as claried in Fig. 9, shows that the alignment accuracy of the process is sufcient to interconnect the 100 pitched contacts of the four thin chips embedded in the cavities of the PI substrate. However, closer inspection learns that, with the described technology, it is difcult to achieve interconnection below

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Fig. 10. Picture of a cavity: zooming in illustrates how the rounded corners require the cavities to be larger than the chip.

Fig. 11. Pictures of the rst results of chip thinning and UTCP packaging with functional (driver) chips from ST Microelectronics.

TABLE VIII ERRORS IN THE ALIGNMENT OF THE METALLIZATION PATTERN TO THE CHIPS PADS

TABLE IX ELECTRICAL MEASUREMENTS ON UTCP WITH FOUR CHIPS EMBEDDED

Fig. 12. Material for UTCP assembly tests: dummy UTCPs with thermode head (left), patterned PES/ITO substrates (top right), and PI/Cu substrates ready for etching (bottom right).

VIII. CONCLUSION AND OUTLOOK In this paper the UTCP packaging technology, still under development, is tested for its ne-pitch interconnection capabilities, both for embedding single chips and multiple chips in a exible PI sandwich. It has been proven feasible to successfully , and sevcontact separate test chips down to a pitch of 40 eral (4) test chips in the same substrate with contacts at a pitch . of 100 As for the future, several directions are interesting for this kind of technology. One of the original purposes that it was developed for, encompasses the integration of driver chips into exible displays, either as separate exible packages, or directly

integrated into (one of) the display substrates. First trials with functional driver chips are being processed to investigate the feasibility of this, as illustrated in Fig. 11. Furthermore, tests have been carried out to assemble such kinds of UTCPs onto patterned exible substrates. Example material is shown in the Fig. 12, and includes assembly on standard PES substrates with ITO interconnection, and standard PI substrates with Cu interconnection patterns [6]. ACKNOWLEDGMENT This work was carried out at the Centre for Microsystems Technology (CMST), an IMEC Associated Laboratory, ELIS Department, Ghent University. REFERENCES
[1] W. Christiaens, B. Vandevelde, E. Bosman, and J. Vaneteren, UTCP 60  thick bendable chip package, presented at the Proc. IWLPS, San Jose, CA, Nov. 2006.

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[2] J. Govaerts, W. Christiaens, E. Bosman, and J. Vaneteren, Fabrication processes for embedding thin chips in at exible substrates, IEEE Trans. Adv. Packag., vol. 32, no. 1, pp. 7783, Feb. 2009. [3] J. Govaerts, W. Christiaens, E. Bosman, and J. Vaneteren, Multiple chip integration for at exible electronics, in Proc. 7th IEEE Conf. Polymers Adhesives Microelectron. Photonics (Polytronic 2008), Aug. 2008, pp. 17. [4] E. I. Haskal, I. D. French, H. Lifka, R. Sanders, P. Bouten, T. Kretz, E. Chuiton, G. Gomez, F. Mazel, C. Prat, F. Templier, M. D. Campo, and F. Stahr, Flexible OLED displays made with the EPLaR process, in Proc. EURODISPLAY 2007, Sep. 2007, pp. 3639. [5] Finetech, e.g., Press Release on Fineplacer FEMTO Assembly & Packaging SMT 2008, 2008 [Online]. Available: http://www.netech.de [6] J. Govaerts and J. Vaneteren, Assembly of ultra-thin chip packages (UTCPs) for enhanced exibility of exible displays, in Proc. 2nd Electron. Syst.-Integration Technol. Conf., Sep. 2008, pp. 309314.

Erwin Bosman was born in Asse, Belgium, in 1980. He graduated from Ghent University, Ghent, Belgium, in 2004 as an electrical engineer in telecommunication. He is currently pursuing the Ph.D. degree in electrical engineering at Ghent University. He works in the clean-rooms of the Centre for Microsystems Technology, INTEC Department, University of Ghent. His research was focused on microstructuring for electronic and optical applications by laser ablation techniques. Later, his research shifted towards the fabrication and integration of optical multimode interconnections on exible substrates.

Wim Christiaens was born in Zottegem, Belgium, in 1981. He graduated from Ghent University, Ghent, Belgium, as an electrical engineer with majors in micro- and opto-electronics in 2004. He is currently pursuing the Ph.D. degree in electrical engineering at the Centre for Microsystems Technology, ELIS Department, Ghent University. His research is focused on the embedding of active and passive components in polyimide substrates.

Jonathan Govaerts received the degree in electrical engineering, specializing in micro- and opto-electronics, from Ghent University, Ghent, Belgium, and is currently pursuing the Ph.D. degree at the Centre for Microsystems Technology, a research laboratory afliated with both Interuniversitary Micro-Electronics Centre and Ghent University. His research focuses mainly on the assembly and interconnection of microelectronics on and in exible substrates.

Jan Vaneteren (M01) received the Ph.D. degree in electronic engineering from the University of Ghent, Ghent, Belgium, in 1987. He is currently a Senior Engineer and Project Manager at the Centre for Microsystems Technology, and is involved in the development of novel interconnection, assembly, and substrate technologies, especially in the eld of exible and stretchable electronics. In 2004, he was appointed part-time Professor at Ghent University. He is author or coauthor of over 100 papers in international journals and conferences and holds six patents/patent applications. Dr. Vaneteren is a member of IMAPS.