Beruflich Dokumente
Kultur Dokumente
DR.M.B.SRINIVAS
By A M VENKATESHWARA RAO (200741002) M KRANTHI KUMAR (200741013) M.Tech. (VLSI & Embedded Systems)
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Acknowledgements
We wish to express our thanks to Mr.Ravindra and MR.Srihari for providing us the tools, and the environment required to complete our project.
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Index
1. 2. 3. 4.
Acknowledgements Abstract Outline of Microprocessor. Basic block diagram explanation Instruction fetch Instruction Decoder Execution Block Write Back logic Pipelining Process and Instruction Format Instruction Types Instruction Set Division and Opcodes List of programs coded in VERILOG Sample program for generating Fibonacci series.
3 4 5 6-8
5. 6. 7. 8. 9.
9 10 11-13 14 15
10. Functional
Simulation Waveforms for the above program 16-18 11. Post Layout Simulation Waveforms for the same program 19-23
12.
Synthesis reports
24-25
ALU Instruction Decoder Total Processor 11. Maximum Clock Frequency calculation
26
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12.Synthesis Diagrams
27-29
ABSTRACT
A description of an 8 bit microprocessor is presented in this report. The objective is to design a general purpose 8 bit RISC processor which is pipelined and implement on FPGA. The design has 4 stage pipelined architecture and 38 user instructions to program the processor. The ROM and RAM are used here for only testing purposes. The components like ALU, control Unit, Write Back logic, Register File are al coded in verilog. The target device of the processor is Alteras Cyclone II family FPGA (EP20C484C7). The design is progressed with all the coding of building blocks and finally integration of the whole design. The code is written and compiled in Active HDL 6.3. Synthesis is performed in Altera Quartus II. The synthesized netlist is simulated for timing in Modelsim 6.1.
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Outline of MicroProcessor
8-bit Data Operations ( 8-bit ALU ) Load Store Architecture. Harvard Architecture. Pipelined 4 stage. 10-bit Address bus. 24-bit Uniform instruction Length. 8 General Purpose Registers. 3-bit PSW (Carry, Zero, Parity). 1 Special Register- PC. 38 Instructions are provided for the User.
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Reg File PC
Write Back
Code Mem
Instruction Decoder
PSW
clock
A dd e r + 1
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8-bit Microprocessor Design For a branch instruction the address in the instruction is passed to the mux and the select line is set such that the branch address goes to the ROM. i.e., address_to_ROM=branching address and then the new input to the PC becomes branching address+1; If there is no branching then select line is set such that the regular address goes to the ROM. i.e., address_to_ROM=address_to_ROM+1; The PC Block just passes the input to the output on every positive clock edge.
Instruction Decoder:
It generates the necessary control signals for the ALU, Write back logic, RAM, ROM and the multiplexers for proper data flow. It also checks the dependency ( because this is pipelining)
Dependencies:
EXAMPLE1: add r0,r1 Sub r0,r2
While the first instruction is being executed the second instruction is decoded. The r0 value will be written back in the next clock cycle. The Instruction Decoder gives the register addresses in the instruction for the register file so that the data in the corresponding registers are out and are ready for execution in the next clock cycle. But the r0 value is not yet written back. It takes the older value of r0. This is source dependency. Elimination: In these sources are same in both the instructions. The control unit sets the adpen signal to the mux 8 bit 2x1 to select REGA for the ALU. One input to the mux is from register file. Other input is the output of ALU. So the new value of r0 is fed to the ALU along with r2. So the results are correct. EXAMPLE2: add r0,r1 Sub r2,r0
This is same as above except that source and destination are same. The Instruction Decoder sets bdpen signal to the another mux 8 bit 2x1 to select REGB for the ALU.
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ALU
ALU_out
NOP Instruction:
\ We used NOP instruction before jump instructions. We did not update PSW, did not change the values of the register file and did not change the RAM data.
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T1
T2
T3
T4
T5
T6
T7
T8
Instruction Fetch
Execute
Decode and Fetch Operands
Write Back
Instruction Fetch
Execute
Decode and Fetch Operands
Write Back
Instruction Fetch
Execute
Decode and Fetch Operands
Write Back
Instruction Fetch
Execute
Decode and Fetch Operands
Write Back
Instruction Fetch
Execute
Write Back
Pipelining Process
RegA Address
RegB Address
10bit Address
3bit
3bit
10bit
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MOV, MVI, LOAD, STORE ADD, SUB, MUL, ADDEQ, SUBEQ, ADDC, ADDCS, ADDS, SUBB, SUBS,SUBBS, ADDI, SUBI 13 AND, OR, XOR, NOT, SWN, ANDI, ORI, XORI, SHL, SHR, ROL, ROR, ROLC, RORC
7
Arithmetic Instructions
Logical Instructions
14
Branching Instructions
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In s tr u c ttio n S e to a n d d e s io pco tr
T h e in s tru c tio n s e t c o n s is ts o f 3 8 in s tru c tio n s . T h is s e t is d iv id e d in to fo u r c a te g o rie s o f inosw n c tio nw . a s s h tr u b e lo s D a ta M o v e m e n t in s tr u c tio n s . A r ith m e tic O p e r a tio n in s tru c tio n s . L o g ic a l O p e r a tio n In s tru c tio n s . B r a n c h in g in s tru c tio n s . M n e m o n ic O p c o d e ADD ADDC ADDS ADDCS SUB SUBB SUBS SUBBS 01 02 03 04 05 06 07 08 F o rm a t
A d dR d ,R s A d d c d ,R s R A d d s d ,R s R A d d c R d ,R s s S u bR d ,R s S u b b d ,R s R S u b s d ,R s R S u b b R d ,R s s
D e s c rip tio n
Rd= d+R s R R d = d + R s + C a rry _ fla g R R d = d + R(P S W c h a n g e s ) R s R d = d + R s + c a(Pr y W c h a n g e s ) R r S R d = R-R s d R d = R-R s a rry _ fla g d -C R d = R-R s(P S W c h a n g e s ) d R d = R-R s a rr y (P S W c h a n g e s ) d -c
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Mnemonic MUL AND OR XOR NOT LOAD STORE MOV MVI SHL SHR ROL ROR ROLC RORC ADDI SUBI
Opcode 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19
Format
Mul Rd,Rs And Rd,Rs Or Rd,Rs Xor Rd,Rs Not Rd Load Rd,< addr> Store Rs,<addr> Mov Rd,Rs Mvi Rd,<imd value> Shl Rd,<imdvalue > Shr Rd,<imdvalue > Rol Rd,<imdvalue > Ror Rd,<imdvalue > Rolc Rd,<imdvalue > Rorc Rd,<imdvalue > AddiRd,<imd value> Subi Rd,<imd_value >
Description
Rd=Rd[3:0]*Rs[3:0] Rd=Rd & Rs Rd=Rd | Rs Rd=Rd XOR Rs Rd= ~Rd Rd=Mem[addr ] Mem[addr Rs ]= Rd=Rs Rd=imd value Shift left Rd by imd_valuetimes Shift right Rd by imd_valuetimes rotate left Rd by imd_valuetimes rotate right Rd by imd_valuetimes rotate leftRd,Cby imd_valuetimes rotate rightRd,Cby imd_valuetimes Rd=Rd+<imd_value > Rd=Rd-<imd_value >
F o rm a t
A n d R d ,< d _ v > l i im a O riR d ,< d _ v > l im a X o riR d ,< d _ v > l im a S w nR s J z <a d d> r J c <a d d> r J p <a d d> r J m p<a d d> r J n z<a d d> r J n p<a d d> r J n c<a d d> r A d d e q d ,R s R J m p<a d d> r
D e s c rip tio n
R d =R d& im d _ va l R d =R d| im d _ va l R d =R dX O Rim d _ v a l R s= {R s [3 :0 ],R s [7 :4 ]} P C = (z = = 1 )?d<d> :P C + 1 a r P C = (c = = 1 )?d<d> :P C + 1 a r P C = (p = = 1 )?d<d> :P C + 1 a r P C = a d d> < r P C = (z = = 0 )?d<d> :P C + 1 a r P C = (p = = 0 )?d<d> :P C + 1 a r P C = (c = = 0 )?d<d> :P C + 1 a r R d = (z= = 1 )? (R d + R s):R d R d = (z = = 1 )? (R s ):R d -R d
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PC.v ControlUnit.v ALU.v PSW.v Regfile.v Code_mem.v (for testing) Data_mem.v (for testing) D FlipFlops :
Tools Used
Active HDL for writing the code and performing functional simulation Altera Quartus II for synthesizing theverilog files, generating output netlist file, SDF file, bitstream file. Modelsim to perform postlayoutsimulation.
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Sample Program
Program to generate firstfibonaccin umbers (Result is updated in Reg) 5 R2 org 000 mvi r4,00 mvi r0,01 mov r1,r0 Rept: mov r2,r1 add r2,r0 mov r0,r1 mov r1,r2 addi r3,01 mov r6,r3 subi r6,05 jz Lend jmp Rept Lend: store r2,30 mvi r3,0f Load r3,30 end
;118000 ;110001 ;102000 ;104400 ;014000 ;100400 ;102800 ;186001 ;10cc00 ;19c005 ;1e000d ;210003 ;0f0830 ;1160ff ;0e6030
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PSW
R E G F I L E
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PSW
R E G F I L E
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P o s t L a y o u t S im u la tio n W a v e fo rm s
A L U P ro p a g a tio n D e la y
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P o s t L a y o u t S im u la tio n W a v e fo rm s
T o p L e v e l ic ro p ro c e s s o r w a v e fo rm s M
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P o s t L a yo u t S im u la tio n W a v e fo rm s
T o p L e ve l ic ro p ro c e s s o r w a ve fo rm s M
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S ynthesis R eports S
Total M icroprocessor synthesis R eport
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Control Unit Propagation Delay: 11ns(worst case) ALU Propagation Delay : 20ns(worst case) MicroProcessor : 20ns (worst case)
Max Propagation Delay for the whole Max Clock Frequency :50 MHz.
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