ANALYSIS, COMPARISON AND APPLICATION OF VEDIC MULTIPLIERS

product terms are summed by the array of adders vertically to the get the final result. The first sum result from starting to last but one row of array of adders is considered to be the resultant bit; remaining resultant bits are obtained from the last row of adders. The sum terms in the array Multiplier flows downwards and carrier flows backwards in the design. The number of adder rows in the array Multiplier is equal to number of partial products and the number of adders in each row is equal to one less than multiplicand bit size. The designing of 16-bit Array Multiplier is similar to that of the design of 4-bit Array Multiplier. Black box view of 16-bit Array Multiplier is shown in the Fig.5.3.

A[15:0]

16 x 16 ARRAY
B[15:0]

R[31:0]

MULTIPLIER

Figure 5.3

Black box view of 16-bit Array Multiplier

There are three ports namely, data input A, data input B and data output R. The representation has four ports: 1) A[15:0] : It is the first input of Array Multiplier. 2) B[15:0] : It is the second input of Array Multiplier. 3) R[31:0] : It is the output of Array Multiplier.

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Let inputs A =A[15:0] , B=B[15:0] and result R= R[31:0] Let P0,P1,P2,P3,P4,P5,P6,P7,P8,P9,P10,P11,P12,P13,P14 and P15 be the sixteen partial products of 16-bit size each which are defined as 1. P0= B[0]*A[15:0] 2 . P1=B[1]*A[15:0] 3. P2=B[2]*A[15:0] 4. P3=B[3]*A[15:0] 5. P4=B[4]*A[15:0] 6. P5=B[5]*A[15:0] 7. P6=B[6]*A[15:0] 8. P7= B[7]*A[15:0] 9. P8= B[8]*A[15:0] 10. P9=B[9]*A[15:0] 11. P10=B[10]*A[15:0] 12. P11=B[11]*A[15:0] 13. P12=B[12]*A[15:0] 14. P13=B[13]*A[15:0] 15. P14=B[14]*A[15:0] 16. P15=B[15]*A[15:0]

All these partial product elements are generated by the AND gates and are given as inputs to the sixteen 15 bit Ripple Carry Adders (RCA). Since it is difficult to represent all the sixteen RCA s two RCA s are considered as one block as shown in the Fig. 5.4 (a). It has in total 30 inputs, one carrier output, 15 partial sum outputs with two resultant bits. This block is used repeatedly for the construction of the array multiplier as shown in the Fig 5.4 (b)

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15 Inputs

15 Inputs

RIPPLE CARRY ADDER

RIPPLE CARRY ADDER

17 outputs Outputs For the first RCA in the array Multiplier this inputs will be partial products only ,for the remaining RCA these inputs will be partial products ,partial sums and carry from previous block. Carry from previous Ripple Carry Adder (C)

Partial product element inputs (P) Partial sum flowing from preceding Ripple Carry Adder (S) Resultant bits from the Ripple Carry Adders (R)

(a) Combination of two Ripple Carry Adders as one block

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BLOCK-1:

RCA-1 AND RCA-2

BLOCK-2: 4

RCA-3 AND RCA-

BLOCK-3: 6

RCA-5 AND RCA-

BLOCK-4:

RCA-7 AND RCA-8

BLOCK-5: RCA-9 AND RCA-10

BLOCK-6: RCA-11 AND RCA-12

BLOCK-7: RCA-13 AND RCA-14

BLOCK-8: RCA-15 AND RCA-16

R31...................................................................................................R16............................... ............................R0

(b) 16-bit Array Multiplier Figure 5.4 Design of 16-bit Array Multiplier

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Inputs to every RCA in every block in the array Multiplier is mentioned in the below .The first two terms (C and S)are considered as intermediate outputs to the next stage of RCA expect the least significant bit in the sum terms which is the actual resultant bit. Outputs & Inputs to Block-1 RCA-1 :C1,S1[15:1],P0[15:1],P1[14:0] RCA-2 : C2, S2[15:1],S1[15:2],C1,P1[15],P2[13:0] Outputs & Inputs to Block-2 RCA-3 : C3,S3[15:1],S2[15:2],C2,P2[15:14],P3[12:0] RCA-4 :C4,S4[15:1],S3[15:2],C3,P3[15:13],P4[11:0] Outputs & Inputs to Block-3 RCA-5 : C5,S5[15:1],S4[15:2],C4,P4[15:12],P5[10:0] RCA-6 :C6,S6[15:1],S5[15:2],C5,P5[15:11],P6[9:0] Outputs & Inputs to Block-4 RCA-7 : C7,S7[15:1],S6[15:2],C6,P6[15:10],P7[8:0] RCA-8:C8,S8[15:1],S7[15:2],C7,P7[15:9],P8[7:0] Outputs & Inputs to Block-5 RCA-9 :C9,S9[15:1],S8[15:2],C8,P8[15:6],P9[6:0] RCA-10:C10,S10[15:1],S9[15:2],C9,P9[15:7],P10[5:0] Outputs & Inputs to Block-6 RCA-11:C11,S11[15:1],S10[15:2],C10,P10[15:6],P11[4:0] RCA-12:C12,S12[15:1],S11[15:2],C11,P11[15:5],P12[3:0] R[11]=S11[1] R[12]=S12[1] R[9]=S9[1] R[10]=S10[1] R[7]=S7[1] R[8]=S8[1] R[5]=S5[1] R[6]=S6[1] R[3]=S3[1] R[4]=S4[1] Resultant bits R[1]=S1[1] R[2]=S2[1]

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Outputs & Inputs to Block-7 RCA-13:C13,S13[15:1],S12[15:2],C12,P12[15:4],P13[2:0] R[13]=S13[1]

RCA-14:C14,S14[15:1],S13[15:2],C13,P13[15:3],P14[1:0] R[14]=S14[1] Outputs & Inputs to Block-8 RCA-15 :C15,S15[15:1],S14[15:2],C14,P14[15:2],P15[0] RCA-16:C16,S16[15:1],S15[15:2],C15,P15[15:1] R[15]=S15[1] R[16:30]=S16[15:1] R[31]=C6 The first bit of the result i.e. R[0]=P0[0] is obtained by using the logical AND gate. From the above Fig.5.4 (b) it can be observed that 15 RCA s are used to reduce the partial products and one final RCA to sum up the carrier and sum vectors to achieve the final 32-bit results. 5.3 ATTRIBUTES OF ARRAY MULTIPLIER 1. Array Multiplier is based on Add and shift Algorithm. 2. To generate the partial products logical AND gates are used. 3. For an N-bit Array Multiplier design N RCA s are required to handle the partial products 4. The number of adders in a RCA is equal one less than the size of the partial products. 5. The arrangement of the RCA s is similar to the arrangement of partial products.

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5.4

ALGORITHM OF MODIFIED BOOTH MULTIPLIER

The Modified Booth Multiplier is based the modified Booth algorithm [10]. This algorithm is based on the bit pair recoding. In general for Booth algorithm recoding scheme is given as -1 times the shifted multiplicand is selected when moving from 0 to 1, +1 times the shifted multiplicand is selected when moving from 1 to 0 and in none of the above cases 0 times the shifted multiplicand is selected. By recoding there is possibility of reducing the number of multiplications required because through recoding there is a possibility of reducing the number of ones in the Multiplier which in turn reduces the number of partial products. In order to speed up multiplication Booth algorithm uses bit pair recoding which is known as Modified Booth algorithm. It halfs the maximum number of summands .In this technique boothrecoded Multiplier bits are grouped in pairs. Then each pair is represented by its equivalent single bit Multiplier reducing total number of Multiplier bits to half. For example bit pair (+1 ,-1) is equivalent to (0,+1). That is instead of adding -1 times the shifted multiplicand at position i to +1 times the shifted multiplicand at position i+1 the same result is obtained by adding +1 times the multiplicand at position i. Similarly (+1,0) is equivalent to (0,+2), (-1,+1) is equivalent to (0,-1) and so on. By replacing pairs with their equivalent, bit pair recoded Multiplier is obtained. Eg.1 gives the basic idea about this bit pair recoding Eg.1 0 +1 0 +2 1 0 1 0 0 1 1 0 1 -1 -1 +1 0 -1 +1 1 0

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Note : Underlined zero indicates the reference bit and the common bits between the pairs acts as reference bits to the succeeding bits Modified Booth Algorithm for unsigned numbers at most produces (N/2+1) number of partial products for an N x N-bit multiplication which is given below. Algorithm: (for unsigned numbers) 1. Pad the LSB with one zero.
2. Pad the MSB with 2 zeros if n is even and 1 zero if N is odd. 3. Divide the Multiplier into overlapping groups of 3-bits. 4. Determine partial product scale factor from modified booth encoding

table. 5. Compute the Multiplicand Multiples 6. Sum Partial Products Instead of deriving booth recoded bit pair Multiplier from booth Multiplier the equivalents of the bit pairs can be obtained from the following table5.1. Table 5.1 Booth recoding table i+1 0 0 0 0 1 1 1 1 i 0 0 1 1 0 0 1 1 i-1 0 1 0 1 0 1 0 1 add 0*M 1*M 1*M 2*M -2*M -1*M -1*M 0*M Partial Product P0 P1 P2 P3 P4 P5 P6 P7

5.5

16- BIT MODIFIED BOOTH MULTIPLIER DESIGN

I. Partial Product Generation: For the partial product generation the given multiplicand is changed to a 32 bit data by appending zeros and all the partial products

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are generated from this 32 bit multiplicand following the booth recoded table5.1. For the multiplication which involves negative coefficients 2s compliment is performed. The partial product generator is shown in the below Fig.5.5 32d0 {16d0,A} {15d0,A,1d0}

32 BIT RCA rca S1[31: 0]

1
{S1[31],S1[3 1:1]

P0

P1

P2

P3

P4

P5

P6

P7

Figure 5.5 Partial Product Generator for Modified Booth Multiplier In order to select the partial product according to the triplet of the Multiplier an 8 by 1 multiplexer is used having 8 inputs each of length 32 bit and three selection lines as shown in the Fig. 5.6.

Partial product inputs in order P0-P7

Multiplier bits triplet

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Figure 5.6 II.

Partial Product Selector

Partial Product Reduction & Final Addition

Let P0, P1, P2, P3, P4, P5, P6 & P7 be any partial product obtained from the partial product as mentioned in the table5.1 (the partial product are selected according the Multiplier triplet bits). For a 16 bit Multiplier, total number of partial products will be nine. Each succeeding partial product must be shifted leftward to two positions as each partial product is equivalent to sum of two implicit partial products. Even though actual size of each partial product is 16, because of sign involvement in the partial products, to get the correct results the sign bit must be extend. Partial Product summation is explained below Fig.5.7 and design of Modified Booth is shown in Fig. 5.8. 1. P0= P0 [31:0] 4. P3=P3 [25:0] 7. P6=P6 [19:0] 2. P1=P1[29:0] 3. P2=P2[27:0] 5.P4=P4[23:0] 8. P7=P7[17:0]

6. P5=P5 [21:0] 9 . P8=P8 [15:0]

P0[31]..........................................................................................................................................................P0[1] P0[0] P1[29].........................................................................................................................................P1[1]P1[0] P2[27]........................................................................................................................P2[1]P2[0] P3[25]......................................................................................................P3[1]P3[0] P4[23]....................................................................................P4[1]P4[0] P5[21]..................................................................P5[1]P5[0] P6[19].................................................P6[1]P6[0] P7[17]..............................P7[1]P7[0] P8[15]..........P8[1]P8[0]

+
R[31]...................................................................................................................................................................... R[0]

Figure 5.7

Summation of partial products in Modified Booth Multiplier

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{16d0,A} 00 B15 B11B1 B5B4B3

PP_GE N PP_GE 5
B9B8B

PP_GE N 8
B15B14

N 2
B3B2B

PP_GE N 7
B13B1

PP_GE N 4
B7B6

PP_GE N 1
B1B0 0

PP_GE N 6

PP_GE N 3

PP_GE N 0

32 BIT RCA 27 BIT RCA 25 BIT RCA 23 BIT RCA 21 BIT RCA 19 BIT RCA 17 BIT RCA 16 BIT RCA(FINAL ADDER) R[31:16]....................................R[15]..........................................................

Figure 5.8

16-bit Modified Booth Multiplier Design

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