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74LS163: Synchronous 4-Bit Binary Counters

Prapun Suksompong May 18, 2004

This article summarizes various important properties of the 74163 synchronous binary counter. The author then attempts to give several examples to illustrate how this MSI can be used to generate more complicated sequences.

The following figures show the connection diagrams and logic diagram of the 74LS163 counter:   Its important properties are:

 Synchronous Reset (Clear) input which overrides all other control inputs, but is active only during the rising clock edge. Clear if CLR is asserted (overrides loading and counting). Synchronous Counting and Loading Count if ENP and ENT are both asserted. Load if LD is asserted (overrides counting). RCO is asserted only if ENT is asserted. So, we can set the counter to stop counting at 15 by setting ENP = 0. Then, RCO = ENT.  Example: Count from 0 to 10. Then, repeat. Here, to detect 10 = 1010, we use Q D Q B . Note that we don’t have to care about the value of Q A and Q C because, besides 1010, the numbers that satisfy 1x1x are 1011, 1110, 1111 which are all > 1010, and not in the sequence (i.e., never reached in normal operation.) Example: Count from 5 to 15. Then repeat. Here, to detect 15, we use the RCO. To load 5, we set DCBA = 0101 = 5 10 . Example: Count from 3 to 12. Then repeat. Example: 8-bit binary counter. Example: Count from 0 to 15, skipping 4, 8, 12.

Here, we have to detect 3, 7, 11 which are Q = Q 3 Q 2 Q 1 Q 0 = 0011, 0111, 1011. Hence, we want the LDN to be 1 for these cases and 0 otherwise. Using K-map, (or by

observation), we have LDN =

QQ

32

QQ .

10

Now, when the output is 3, 7, 11, we want to load I = I 3 I 2 I 1 I 0 = 5, 9, 13, respectively. Q 3 Q 2 Q 1 Q 0
I 3 I 2 I 1 I 0
0011
0101
0111
1001
1011
1101
Otherwise
dddd

Note that we don’t care about the value of the when LD is not 1. From the truth table above, we then have 1
Q
I 0
Q
3
3 Q 2
Q
00
01
11
10
1 Q 0
0
0
4
12
8
I 1
00 d
d
d
d
Q
1
5
13
9
I 2
2
01 d
d
d
d
Q
I
Q
Q
0
3
7
15
11
323
11
0
1
d
1
Q
1
2
6
14
10
10
d
d
d
d
Q
2
K-map for I 3
Hence, we have the following design:
74163
LDN
A
NOT
Q2
Q0
NAND3
B
QA
Q1
OR2
13
C
QB
NAND2
Q2
17
Q3
D
QC
Q3
19
QD
ENT
11
ENP
RCO
NOT
OUTPUT
CLRN
14 LD
18
INPUT
OUTPUT
CLK
CLK
10 Q[3 0]
7
VCC
1 COUNTER
8 VCC
GND
12 Example: Count from 0 to 13, then count from 1 to 13, and then from 3 to 13, and then repeat this sequence.

Here, we detect Q = Q 3 Q 2 Q 1 Q 0 = 13 = 1101 at the outputs of the counters. The LD then becomes
QQ QQ
or just QQQ
because 1111 is not in the sequence. The
3210
320
first part of the design is shown below:
74163
LDN
I0
A
I1
Q0
B
QA
NAND3
Q1
C
QB
Q2
D
QC
35
Q3
ENT
QD
ENP
RCO
NOT
OUTPUT
CLRN
14 LD
18
INPUT
OUTPUT
CLK
CLK
10 Q[3 0]
7
VCC
1 COUNTER
OUTPUT
30 I[1 0]
OUTPUT
34 D[1 0]
8 VCC
GND
12

The loaded inputs I = I 3 I 2 I 1 I 0 cycles from 0 1 3. So, I 3 I 2 = 00, and we need to build a state machine (basically a counter), which is triggered by the LD signal, and goes from 00 01 11.

So, we have 3 states: 00, 01, 11. Now, we will consider what would be the value that get loaded into the counter. Note that the LD signal will be high when the counter reach 13 with some small delay. Let t 0 + be the time that the counter output values change to 13, where t 0 is the time of positive clock tick, and is the delay of the counter. Then, it will stay 13 from time t 0 + to t 0 + +T, where T is the period of the clock. The LD, will go high at t 0 + + , where is the small delay of the combinational logic (LD-check logic) that we use to test for 13. (It is safe to assume + < T.) So, LD is high from t 0 + + to t 0 + + +T, i.e., the clock tick that matches LD = 1 is at t 0 +T and not t 0 . If we set the state machine to cycle at the click tick with LD = 1, then it will change at time t 0 +T+ where is the delay introduced by the state machine. So, the value that get loaded into the counter when LD goes high, is the outputs of the state machine at time t 0 +T which is the old state values. FF’s delay
LD check delay
Outputs of the state at
Counter Delay
into the counter

We shall present two solutions here:

1)

Set the outputs of the state machine to be the next state, instead of directly output the current state. This is shown below.

 State = D 1 D 0 * 0 * D D 1 SM’s output I I 1 0 00 01 01 01 11 11 11 00 00 10 dd dd

By observation (or K-map) we then have

*

1

D

I

1

DD

10

*

DID

00

1

,

or D D

1

0

, and

which is implemented below: 21mux
NOT
I0
A
23
B
Y
LD
CLK
S
27 MULTIPLEXER
AS+BS'
AND2
D0
21mux
I1
24
A
B
Y
S
28 MULTIPLEXER
D1

Note that we don’t want to put the LD signal directly into the clocks of the D-FF’s because LD can have glitches (since it is an output from combinational logic with multiple inputs). Here we implement the circuit with the help of 2:1 mux. The D- FF’s grab the outputs of the mux’s every clock tick. When LD is 0, we set the mux to pass the old state, so the FF state remain unchanged. When LD is 1, the state is updated. (So, now we only concern about the values of the LD at the clock ticks, and hence the LD glitch problem is eliminated.)

The combination of mux and the D-FF above is exactly the D-FF with EN. So, another implementation is shown below DFFE
NOT
I0
PRN
D
Q
D0
CLK
23
LD
ENA
CLRN
AND2
36
24
DFFE
I1
PRN
D
Q
D1
ENA
CLRN
37  2)

Another method is to try to get the state machine to update faster. This can be done by feeding the CLK_L into each FF’s clock. The effect of this is to shift the

clock tick corresponding to LD = 1 for the state machine to the time

the counter loads the new values at t 0 +T, the state now get updated before being

t

0

T

2

. Since NOT
CLK
CLK_L
31
DFFE
NOT
PRN
I0
D
Q
CLK_L
23
LD
ENA
CLRN
34
AND2
DFFE
PRN
I1
D
Q
CLK_L
24
ENA
CLRN
35  Example: Count from 0 to 10, then count from 3 to 11, and then from 1 to 10, and then repeat this sequence.

Since we need to deal with three subsequences, we shall define state machine which has three states. Note here that we detect 10 = 1010 2 and 11 = 1011 2 . So, we always

detects

QQQ = 101, and then Q 0 = 0 or 1 depending on what state that counter is in.

321

 State = D D 1 0 Detect D 1 * D * 0 Load = I I 1 0 00 1010 01 3 = 11 01 1011 10 1 = 01 11 dddd dd d = dd 10 1010 00 0 = 00

Observe that the value of the Q 0 that we want to detect is the same as D 0 . It is then obvious that we can use
QQQ
D
Q
to check for 10 and 11. The first part of
321
0
0
the circuit then becomes the following:
74163
LDN
XNOR
I0
A
NAND4
I1
Q0
D0
B
QA
64
Q1
NOT
C
QB
LD
NOT
Q2
D
QC
38
Q3
34
ENT
QD
63
OUTPUT
LD
14
ENP
RCO
OUTPUT
CLRN
10 Q[3 0]
INPUT
OUTPUT
CLK
CLK
30 I[1 0]
7
VCC
1 COUNTER
OUTPUT
41 D[1 0]
8 VCC
GND
12
*
*
Also, by observation (or K-map), we have
the state machine is the following:
D
,
I DD
D
. Hence,
D 1
D 0
, I 0
0
1
10
1 NOT
D1
AND2
I0
58
I1
NOT
D0
59
60
CLK
LD
D0
CLK
D1 Example: Count from 2 to 13, then count from 1 to 13, and then from 3 to 13, and then repeat this sequence.

Here, we detect Q = Q 3 Q 2 Q 1 Q 0 = 13 = 1101 at the outputs of the counters. The LD

then becomes

QQ QQ . The first part of the design is shown below:

3210 74163
LDN
I0
A
I1
Q0
NAND3
B
QA
Q1
C
QB
Q2
46
D
QC
Q3
ENT
QD
ENP
RCO
CLRN
INPUT
CLK
CLK
7
VCC
COUNTER
1
8 VCC
GND
12 NOT
OUTPUT
14 LD
18
OUTPUT
10 Q[3 0]
OUTPUT
39 I[1 0]
OUTPUT
34 D[1 0]

Now, we set the outputs of the state machine to be the next state. State = D 1 D 0
*
*
D D
SM’s output I I
1
0
1
0
00
11
01
01
dd
dd
11
10
11
10
00
10
*
*
By observation (or K-map) we then have
D
,
DIDD
,
D .
D 0
I 1
1
10
1
0
1
NOT
D0
CLK
41
LD
WIRE
D1
I1
CLK
43
XNOR
I0
40
D1 The problem with this design is that when we start the machine, it counts from 0. To solve this, we shall use a reset input. So, when reset goes high, we shall load 2 into the counter. Because we want to set BA = 10 when RESET is high, we have

A I RESET

0

0RESET

I RESET , and

0

B I RESET 1RESET I RESET

1

1

.

Also, we need to modify the input to the load so that it will also load when the reset is high. This can be achieve by just OR the old LD with the RESET. NOT47 RESET_L RESEINPUTVCC44 T
74163
RESET_L
LDN
I0
A
Q0
AND3
QA
B
RESET
Q1
RESET
QB
C
I1
Q2
72
D
QC
Q3
ENT
QD
ENP
RCO
OUTPUT
LD
60
CLRN
OUTPUT
Q[3 0]
INPUT
58
CLK
CLK
70
VCC
OUTPUT
COUNTER
I[1 0]
71
59
OUTPUT
D[1 0]
61
69
VCC
GND
64
NOR2
57 Example: Count from 2 to 10, then count from 1 to 11, and then from 3 to 10, and then repeat this sequence.

 State = D D 1 0 Detect * 0 * D D 1 Load = I I 1 0 00 1010 01 1 = 01 01 1011 10 3 = 11 11 dddd dd d = dd 10 1010 00 2 = 10

Again, observe that the value of the Q 0 that we want to detect is the same as D 0 . It is

then obvious that we can use

QQQ

321

D

0

Q

0

to check for 10 and 11.

We also have (from the table):

Again, we introduce the RESET to start the counter with 2:

D

1

D

*

0

,

DDD

01

0

,

I

0

*

D

1

,

D D .

I

11

0 A I RESET
RESET
0
I RESET
0
0
B I RESET
1 RESET
I
RESET
1
1
NOT
INPUT
RESET
48
VCC
50
AND2
RESET
NOT
D1
I0
49
74163
45
XNOR
OR2
LDN
XOR
NOT
OR2
I1
A
D0
AND4
D0
Q0
58
55
57
B
QA
46
Q1
51
C
QB
LD
NOT
Q2
RESET
D
QC
Q3
34
ENT
QD
59
ENP
RCO
OUTPUT
CLRN
LD
14
INPUT
OUTPUT
CLK
CLK
Q[3 0]
7
VCC
10
COUNTER
1
OUTPUT
I[1 0]
30
NOT
OUTPUT
CLK
CLK_L
D[1 0]
41
8 VCC
31
GND
12 XNOR
CLK
40
LD
CLK
D0
D1 Example: Triangle Counter counts the following sequence (in the left to right, top to bottom order)

0, 1, 2, …, 14, 15

1, 2, …, 14, 15

2, …, 14, 15

13, 14,15

14,15

15

and repeats starting at 0. (note that each time the counter reaches 15, it resets to one more than it reset to the previous time it reset.

Here, it is obvious that we will detect 15, and hence we can directly use the RCO signal. The load sequences consist of 16 state, 0 1 2 15 0. What we

should do is then to construct a state machine that give the sequence 1 2

15 0 1. Note that we start with 1 because the second subsequence starts with 1. Now, this is almost a 4-bit counter. Let’s consider he following circuit Then, at the clock tick that LD = 1, the value of the helper counter still doesn’t change because of the delay in the counter (FF’s). To solve this problem, we just drive this helper counter by CLK_L. (Recall that we have two options, either construct a state machine that give the next state (i.e. for state 0, output 1), or drive it by CLK_L. Here, since we already have the state machine (the counter), it is easier to directly use it.) Note also that we want the helper counter to count when its clock ticks and RCO = 1. The AND is implemented by feeding the RCO into the ENT of the helper counter.  Note that, if somehow, we can grab the inputs to the FFs (i.e. the next state value)
from the helper counter (instead of the current state value), then we don’t need to
feed it by CLK_L:
74163
RCO
LDN
NQ0
A
counter4
CLK
NQ1
Q0
B QA
CLK
Q[3
0]
RCO
NQ[3 0]
NQ2
Q1
C QB
EN
NQ[3
0]
NQ3
Q2
D QC
10
Q3
ENT QD
ENP
RCO
1
CLRN
INPUT
CLK
CLK
4
VCC
2 COUNTER
OUTPUT
5 Q[3 0]
8 VCC
7
NOT

where in the above figure, counter4 has an extra output vector NQ which outputs the next state value.

References :

 Logic 74xxxx Series, http://www.ee.washington.edu/stores/DataSheets/74ls/74ls161.pdf http://ece.rose-hulman.edu/labs/dataSheets/74ls163.pdf http://focus.ti.com/lit/ds/symlink/sn74ls163a.pdf Wes Swartz, ENGRD 230: Introduction to Digital Logic Design, Final exam, Cornell University, Fall 2003. Evan Speight, ENGRD 230: Introduction to Digital Logic Design, Final exam, Cornell University, Fall 2002. Doug Long, ENGRD 230: Introduction to Digital Logic Design, Final exam, Cornell University, Spring 2004. John F. Wakerly, “Digital Design: Principles and Practices,” 3/e, Prentice Hall. M. Morris Mano and Charles R. Kime, “Logic and Computer Design Fundamentals” 2nd Edition.