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2011 IEEE Nuclear Science Symposium Conference Record N16-4

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CICCIUiS
L. Bombelli, R. Quaglia, C. Fiorini, A. Tocchio, R. Alberti, T. Frizzi
Abstract- In this paper we describe a front-end ASIC for the
readout of multi-elements SDDs specifcally designed for high
count-rate X-ray applications. In particular, the focus of this
design is the maximization of the throughput, keeping a high
energy resolution. The readout of the detector by means of 8
separate channels enables to increase the maximum count-rate of
the system, while the custom design of the front-end ASIC allows
to handle the number of channels within a very compact
architecture of the detection system and maintaining excellent
noise performance. The use of a very-fast high-order processing
flter and of an efcient pile-up rejection strategy enables to
minimize the pile-up probability and maximize the throughput of
the single channels for a given processing time. As it will be
shown, the developed 3-phase peak-stretcher, together with a fast
output multiplexer, does not introduce additional dead-time
during the valid-data acquisition with respect to the pure pile-up
limitation of the shapero The ASIC is designed with the possibility
to operate with the input JFET integrated on the detector itself as
well as to operate in combination with an external CMOS
preamplifer. The measured noise-contribution added by the
front-end ASIC at 1.8 JS shaping time is only 2.9 electrons and
just 4.1 electrons ENC exploiting at best the speed capability
using the shortest 600 ns peaking time. In X-ray spectroscopy
measurements, the ASIC connected to a SDD has allowed to
achieve an energy resolution of 126 eV at 1.5 Is peaking time and
115 kcps/channel input rate, and 144 eV at 600 ns peaking time
and 800 kcps/channel input rate.
I. INTRODUCTION
5
everal X-ray spectroscopy applications (e.g. at synchrotron
facilities or for X-ray astronomy observatories) requires
detection systems operating with high-energy resolution and
high-counting rate capability. The use of Silicon Drif
Detectors (SDDs) is very ofen the best option to cope with
such demanding requirements. In order to increase the count
rate, there are different strategies which can be implemented
in a spectroscopy system. The segmentation of the detector in
separate SDDs units allows to increase the overall count-rate
capability subdividing the photon fux in more independent
units. The shaping time of the processing flter can be reduced
Manuscript received November 15, 2011. This work was supported in part
by Italian INFN and AS!.
L. Bombelli is with Politecnico di Milano, Dipartimento di Elettronica e
Informazione, INFN Sezione di Milano, and XGLab, Milan, Italy; email:
bombelli@elet.polimi.it.
C. Fiorini, R. Quaglia ad A. Tocchio are with Politecnico di Milano,
Dipartimento di Elettronica e Informazione; C. Fiorini and R. Quaglia are also
with INFN Sezione di Milano; email: carlo.forini@polimi.it.
R. Alberti and T. Frizzi are with XGLab srI, via Moretto da Brescia 23,
20133, Milan, Italy; email: info@xglab.it.
in order to increase the count-rate of the single electronic
channel. However it cannot be reduced indefnitely due to the
increase of the noise in the signal readout. Moreover, an
efcient pileup rejection strategy has be foreseen, in order to
discard the pileup event in the shaper maximizing the
throughput of the system keeping the best energy resolution.
We have pursuit all of the above solutions, with the aims to
develop an integrated analog-based processing system,
ofering a state-of-the-art tradeof between energy resolution
and count-rate capability. The system is composed by a font
end ASIC specifcally designed for fast and compact multi
channel applications based on SDDs and compact PCB Data
Acquisition System (DAQ) that provides the data acquisition
and the ASIC programming.
This paper describes the design and the performances of the
font-end ASIC designed for the readout of multi-elements
SDDs. Such ASIC, which is the core of the processing system,
allows to handle the number of channels within a very
compact architecture of the detection system and maintaining
excellent noise performance. The font-end ASIC implements
8 complete analog channels performing the contemporary
read-out of 8 independent SDDs. It provides a 8: 1 multiplexed
analog output (Fast Mode) or two separate 4:1 multiplexed
analog outputs (Ultra-Fast Mode) to the exteral acquisition
system. The layout of the circuit is shown in Fig. 1.
Diferent state-of-the-art preamplifers can be used with the
ASIC, as specifed in the following: preamplifers using JFET
integrated on the detector substrate [1], circuits based on
discrete components using exteral JFET as input transistor
[2], and the more recently developed CMOS preamplifer
using a MOSFET as input element (CUBE preamplifer) [3,4].
The frst solution offers a very good perforance at short
processing time due to the low value of the stray capacitance
at the anode achieved by the integration of the JFET in the
detector. Very recently, also the latter solution has shown
excellent performances at very short shaping time, thanks to
the very high transconductance of the input MOSFET which
more than compensate the higher anode capacitance. The
ASIC has been designed to cope with these diferent
preamplifer circuits, operating in the pulsed-reset regime. In
the case of SDD with integrated JFET, the ASIC includes
already the preamplifer.
978-1-4673-0120-6/11/$26.00 20 11 IEEE 944
Fig. I. Layout of the ASIC designed for multi-chanel detection systems
based on SODs.
II. THE CIRCUIT ARCHITECTURE
The circuit is composed by 8 identical analog chanels to
amplif and flter the amplitude information and by digital
sections to implement the logical fnctions and the
communication with the exteral acquisition system. The
blocks scheme of the ASIC is shown in Fig. 2.
DETECTOR
AND
ASIC
Fig. 2. Basic blocks of the ASIC. The confguration shown is the one with
an exteral preamplifer.
Each one of the 8 analog channels is based on a 9-order
complex-poles shaper amplifer (SA), a fast shaping amplifer
(FSA) to be used for pile-up rejection (PUR), two baseline
holders (BLH), for SA and FSA, a fast 3-phase peak stretcher
(PKS) and an efcient PUR exploiting the FSA. The high
order SA is not only adopted for the best approximation of the
optimum weighting function on the noise source, but also
because an high-order complex-pole shaper has an output
pulse almost symmetrical respect to the peaking time. Such
condition is very important in order to minimize pile-up at a
given shaping time.
The digital section is arranged in 2 hierarchal levels of
logic. The lower level, one per channel, consists of two logics,
channel logic and peak logic. The channel logic implements
some tasks directly related to the single channel. It detects if
945
the output of the preamplifer overcome a selectable threshold,
provides the inhibit of the shapers and of the BLHs during the
reset phase and allows to modif the shaping time (of SA) and
the dynamic range (of both SA and FSA).
The peak logic handles the three phases of the peak
stretcher and the pile up rejection strategy.
The top level, so called global logic, is one for the whole
ASIC. The global logic provides the interface with the
channel logics, the peak logic and the exteral DAQ. The
main role of the global logic is to handle the mUltiplexer,
working in polling mode, and to provide a communication
interface with the exteral DAQ, for this pu
r
ose a 160 bits
shif register with a custom SPI (Serial Peripheral Interface) is
included.
All the implemented features (gain, shaping time, etc.) are
programmed in the ASIC on interal register. A ROM
memory with a standard confguration is also included and
exterally selectable.
The output of one of the 8 shaper amplifers, one of the fast
shaper amplifers and one of the output of the preamplifers
can be buffered out-of-chip for testing purpose via 3 interal
buffers. The implemented architecture is modular so it can be
easily upgraded to a higher number of channels.
The chip is designed to reduce the exteral components
needed. Only passive components are required exterally,
ceramic capacitors are needed for fltering the voltage supplies
and some voltage references.
The interal current and voltage references are provided by
interal DACs so simply modifing bits in the shif register it
is possible to change the bias condition; this approach is very
useful to use the same ASIC also for low power application.
In order to maximize the throughput rate, we have found
that the implementation proposed by Goulding [5] is the best
strategy to discard only event really corrupted by pile-up. The
cores of the PUR are a digital logic and a 3-phase peak
stretcher. The logic, using the FSA output, start an inspection
window (which is function of the shaping time), for each
detected photon. If only one photon arrives in each window,
the corresponding event is eligible for the acquisition and
correctly acquired by the PKS. On the contrary, if more than
one photon are detected in the window, the PKS promptly
discard the pulse without adding additional dead-time. Using
such temporal constrains, instead of an arbitrary threshold on
the main flter, it is possible to acquire also slightly partially
overlapped pulses with not-corrupted peak amplitudes.
III. THE ANALOG CHANEL
As mentioned before, the circuit is designed to work with
diferent type of SODs, so to use those with JFET integrated
on the substrate [I] a preamplifer is included. The structure of
this preamplifer is a modifed version of the one presented in
[6].
The main flter is an 9-order complex poles composed by a
real pole followed by 4 biquad cells (3 Multiple Feedback -
MFB- and I Sallen-Key). A coupling capacitor is present at
the output of the charge preamplifer, so the gain of the frst
cell is given by the ratio between this capacitor and the one
used for the real pole.
The peaking time of the shaper is selectable between 4
values: 600 ns, 1.5 Is, 2.2 Is and 4 Is. The frst one has been
chosen in high count rate operations with still a good energy
resolution, the last one to have the best energy resolution for
SOD with interal JFET. The other two values are instead
very close to the optimum with the SOD coupled with the
CUBE preamplifer [3,4].
The fast shaping amplifer has the same structure of the
main one, but has only one peaking time equal to 200ns to
guarantee a fast, but not too noisy, analog processing of the
signal for PUR operation.
Both SA and FSA have different gains selectable via SPI,
corresponding to a fll scale 1.5 V at the output with 15 mY,
22.5 mY, 30 mV or 37.5 mV at their input.
To guarantee a minimum shif of the baseline at high count
rates both SA and FSA are connected to a fully integrated
BLH [7].
IV. PEAK STRETCHER AND PILE UP REJECTOR
The output of the main shaper is connected to a dedicated
peak stretcher (PKS) that detects and hold the maximum value
of the pulse until the PKS is reset.
In this application, a conventional PKS is not sufcient.
Suppose in fact that the input semi-Gaussian signal has
reached its maximum. Then the acquisition starts to read the
datum. If, during the readout, a second higher event interests
the same channel, the PKS updates the stored value because
the input is higher and the circuit tracks it. In this situation, the
acquisition would read wrong information. A standard 2-phase
PKS [8,9] allows to overcome this limitation.
In order to reset the PKS and re-activate it for new pulses,
two diferent approaches can be considered: reset the PKS for
a fxed time or kept the PKS reset until the output of the
shaper is lower again than a fxed threshold. The frst
approach is not totally safe (without adding a complex control
logic) because eroneous peaks can be detected (as shown in
the example of Fig. 3). The second idea is instead a safer
solution but drastically reduces the throughput at very high
count rate because it imposes a very conservative condition on
the output of the shaping amplifer which does not allow to
accept partially overlapped pulses still with not-corrupted
amplitudes.
CLR .f.r
r8idinl
Erroneous
peak value
Therefore, a modifed version of the conventional PKS has
been designed. In a 3-phases PKS, the WRITE and READ
phases are enabled only close to the peak. In the third phase,
called TRACKING, the PKS in operating in a buffer
confguration (see Fig. 4) and the WRITE/READ operation
are disabled.
I- I M,
V,
Tracking
Fig. 4. In the "tracking phase" the hold capacitance tracks the input.
In Fig. 5, a principle scheme about the operation of the 3-
phase PKS is shown and in Fig. 6 an example of simulation is
presented for a case similar to the one of Fig. 3.
PKSoutput
Tracking
;/ . .......
.
Read.Fas

Fig 5. In the tracking phase the PKS is in bufer confguration; the write
(green) and read (cyan) phases, activated only across the peak of the semi
gaussian pulse, are enabled by temporal windows.
Fig 6. The signal have the same amplitude are correctly read. The
simulation is with SPECTRE simulator in CAENCE Virtuoso
Fig. 3. Example of erroneous peak detected in a stadard 2 phase PKS
Environment.
with fxed reset time.
946
The almost symmetrical response of the 9-th order shaper is
mandatory to correctly operate with high count rate. Thanks to
this feature, in fact, the pileup rejector circuit can easily
handle fxed time windows maximizing the throughput.
In Fig. 7 a principle of the pile up rejection strategy for the
fastest peaking time is shown. In Fig. 8 the basic principle of
the peak logic is presented.
I
- - T.
"
<500"
W--- ------------

I
- T. " <600"

W___
II
Fig 7. Desired processing of the pulses to maimize the throughput. The
accepted tolerance is I %. I) Both events have to be discarded; II) frst event
has to be read, second event is corrupted and it has not to be read; III) both
events have to be read.
If the two pulses are temporally spaced at least 600 ns, we are
sure that there is no a pile up occurrence. This approach is
good also to catch signals with very different amplitudes
occurring one afer the other.
T2 = 600lls
'0Il0]?r'
0II
LDDfDlwD0DwuXuD5lDD
06|::0]

. _ _


TRJAST
2
PUR
_
_
__-_ ___ --

luU
000ODD
-----------
Fig 8. The pile up rejection strategy proposed. The length of the control
window T2 is equal to the decreasing tail of the semi-gaussian pulse. If a
trigger fast take place in this phase the T2 windows is extended for another
peaking time.
In the peak logic also another functionality has been
designed, there is the possibility to trig the logic with the main
shaper and not with the fast one. In this way, of course, the
9
947
pile up rejection circuit does not work but we can extend, for
low rate application, the energy range down to low values.
In both cases the threshold is set by a single DAC per
channel and can be fully programmable via SPI.
v. DATA ACQUISITION BOARD
The Data Acquisition Board (Fast-DAQ), realized by
XGLab, is based on an FPGA and performs both acquisition
and ASIC programming by SPI. It is able to read-out the ASIC
multiplexer up to 15 MHz. The analog signal is transmitted
fom the ASIC board to the Fast-DAQ in differential mode in
order to reduce pick-up disturbs. The signal is then sampled
with a commercial 16-bit resolution ADC. The sampled data is
buffered into the FPGA that stores the spectra (up to 8 spectra,
with fll ADC resolution) and then transmits via USB protocol
to the host Pc. The FPGA may be adapted for diferent ASICs
releases and readout schemes. All the acquisition parameters
(i.e. acquisition clock, ASIC confguration and other system
settings) are controlled through a custom sofware interface. A
simple data fow diagram and a picture of the complete system
(except for the Personal Computer) are shown in Fig. 9 and in
Fig. 10.

.
|P
_ADC
I

MEMORY
DATA BUS
11'"
SPECTRA
x
:
2

o
ACQUISIIR Ol
\
V

I
I
SPIINTERFACE
I
I
SYS TEM CONFIGURA TION TIMER
I US B FIF O
I
RESET/INHIBIT I C ONFIGURATION
I
1'
'
--
Fig 9. Data Flow Chart of the complete system.
-
I
1
w

t

'
:
:

! :


N
"


:
i
C
:
I

Fig 10. Picture of the complete system, the board on the lef (90mm x
150mm) hosts the 8-channels ASIC, the right one the FAST-DAQ.
VI. SYSTEM PERFORMACES
In this section, we show a selection of experimental results
obtained with this system.
In Fig.lO and Fig.ll, the output of the shaper at different
peaking time and at different gain is shown.
Fig 10. Output of the shaper at diferent peaking time, the yellow line is the
output of the fast shaper amplifer.
Fig I I. Output of the main shaper at diferent gain settings.
For X-ray spectroscopy tests, the ASIC has been connected
to a circular SOD and a CUBE preamplifer [4]. The reference
SOD here employed has an area of 10 mm
2
The measurement
are performed at -40C (SOD cooled with a Peltier cell) in
order to reduce as much as possible the noise associated to the
leakage current.
In Fig. 12, the measured spectrum of the
55
Fe source is
shown. The energy resolution at the Mn-Ka line is 126.2 eV
FWHM using the complete analog chain, with the 1.5 s
peaking time.
According to [4], the SOD + CUBE readout offers very
good performances at low shaping time, so we measured the
energy resolution also with the shortest peaking time (600 ns)
with different value of input count rate. In Fig. 13 we report a
measurement with an input count rate of 800 kcps and an
output count rate of 265 kcps on a single channel. The energy
948
resolution at the Mn-Ka line is 144.2 eV FWHM, a very
remarkable value at this peaking time and input count rate.
In Fig. 14 the output count rate vs. the input count rate is
plotted for all the 4 peaking times, the Poisson limit is also
shown for comparison. It possible to notice that the output
count rate is very close to the intrinsic Poisson limit.
12
X 10
4
10
8
V
+
C
6
:
0
U
4
2
.5 5
SS
Fe spectrum
1 .5 Is peaking time
Input count rate: 115 kcps
126.2eV FWHM

.l
5.5 6 6.5
Energy [KeV
7
.
7.5
Fig 12. Spectrum of the 5'Fe source measured with a SDD and the CMOS
CUBE preamplifer (temperature of _400 C). The best energy resolution of
126eV FWHM was achieved using 1. 5 Is peaking time. The input count rate
is 115 kcps, the output 92 kcps. The input count rate is estimated with a
commercial digital pulse processor.
55
Fe spectrum
600 ns peaking time
Input count rate: 800 kcps
14.2 eV FWHM
--
Fig 13. Spectrum of the 55Fe source measured with a SDD and the CMOS
preamplifer, at a temperature of _400 C. The peaking time of the shaper is 600
ns. The input count rate is 800 kcps, the output count rate 265 kcps.
A test with 4 CUBE preamplifers has been exploited and
we have obtained a total output count rate of 1.4 Mcps with an
input count rate of 3 Mcps with DAQ and MUX in Ultra-Fast
Mode (Fig. 15).
We also tested the speed capabilities of the Fast-DAQ by
pulsing 4 channels. The system shows an excellent throughput
performance, allowing the user to operate 4 channels up to
3.75 Mcps/channel input rate (Ultra-Fast Mode) or 8 channels
at 1. 8 Mcps/channel (Fast Mode).
1000
"i
O
U


N

+
C
D
O
L
'
10
B
O
0
10 100
Input Count Rate (kcps)
1000
Peaking time
O.6us
- -0.6us (Poisson Lmt.)
..1.Sus
- 1.5U5 (Poisson lrt.)
_2.2u5
~"2.2u5 (Poisson lrt.)
4.0us
- 4.0U5 (Poisson Lmt.)
Fig 14. Output count rate vs. input count rate, for diferent peaking time;
the Poisson limits are the dashed lines.
c10000
a Total input count rate: 3 Mcps

Total output count rate: 1.4 Mcps
Q 1000
Peaking time: 600 ns
-
t
0:
-
100
o
o
-
::
a 10
-
::
10
o
100 1000 10000
Input Count Rate (kcps)
Fig 15. Output count rate vs. input count rate, for 4 SODs connected to 4
chanels, Ultra-Fast Mode setting.
Finally, we have tested the pile-up rejection system. To
exploit the beneft of the pile-up rejection we have acquired a
spectrum with and without the pileup rejection system
enabled. The result is shown in Fig. 16. The plateau at high
energy due to the pile-up effect is very well reduced by almost
two orders of magnitude in the spectrum acquired with the
pile-up rejection enabled. It is known that the pile-up is less
efcient to reject photons close to the peaking time of the fast
shapero Therefore, the circuit is not able to identif the arrival
of two photons too close in time fom one photon with the
sum of energies. As result, the visible peaks in Fig. 16 at about
double or triple the Mn-Ka energy are reduced less
effectively.
W
+
T
5 T
o
U
T T4
Energy [keY]
Tl|QI0!|0-UQ
Fig 16. Efectiveness of the pileup rejection strategy. Comparison of the
typical spectra acquired with PUR disabled (in red) and with PUR enabled (in
blue). The peaking time is 600ns and the estimated input count-rare is 265
kcps.
VII. CONCLUSIONS
We have developed an integrated circuit that implements in
a monolithic solution most of the functionality required for an
X-Ray spectroscopic processing system.
The ASIC is designed to operate directly connected to SOD
with interal JFET or with SOD coupled to CMOS
preamplifer. The ASIC is conected to a FPGA-based DAQ.
The circuit is composed by 8 identical analog channels and by
a digital section. The chip has been realized and successfully
tested. The chip is flly working and the performances have
been evaluated and presented in this work.
Spectroscopic measurements have been carried out with a
SOD at the different peaking time in order to asset the best
tradeof between noise and count rate capability. The energy
resolutions achieved are very closed to the one obtained with
non integrated systems.
The architecture can handle rate up to 800 kHz per channel
with low dead time and high throughput. Moreover, the
implemented architecture can be expanded in the future to a
larger number of channels.
REFERENCES
[II
P.Lechner, et a!., "Silicon drif detectors for high count rate X-ray
spectroscopy at room temperature", Nucl. Instr. and Meth., A 458, 281-
287, 2001.
[2
1
T. Nashashibi,"The Pentafet and its applications in high resolution and
high rate radiation spectrometers ", Nuclear Instruments and Methods in
Physics Research Section A: Accelerators, Spectrometers, Detectors and
Associated Equipment, Volume 322, Issue 3, 15 November 1992, Pages
551-556.
[3
1
L.Bombelli, C.Fiorini, T.Frizzi, R.Nava, AOreppi, ALongoni "Low
noise CMOS Charge "Preamplifer for X-ray Spectroscopy Detectors"
Nuclear Science Symposium Conference Record, 2010, ISBN # 978-1-
4244-9104-9.
[4
1
L. Bombelli, C. Fiorini, T. Frizzi, R. Alberti, A Longoni, " CUBE, A
Low-noise CMOS preamplifer as alterative to JFET front-end for
High-count Rate Spectroscopy", these Proceedings, 2011.
949
[5] Goulding, F.S. ; Landis, D. A.; Madden, N.W. Design philosophy for
high-resolution rate and throughput spectroscopy systems. IEEE
Transactions on Nuclear Science, n I, p 301-310, 1982.
[6) Fiorini, C.; Alberti, R.; Bombelli, L. ; Frizzi, T.; Gola, A; Nava, R.
"Readout ASICs for Silicon Drif Detectors", Nuclear Instruments and
Methods in Physics Research Section A, Volume 624, Issue 2, p. 367-
372.
[7] G. De Geronimo, P. O'Connor and 1. Grosholz, "A CMOS Baseline
Holder (BLH) for Readout ASICs", IEEE Transaction on nuclear
science, 2000.
[8] Gianluigi De Geronimo, Paul O'Connor, and Anand Kandasamy.
Analog cmos peak detect and hold circuits. part I. aalysis of the
classical confguration. Nuclear instruments ad methods in physics
research A, 484:533-543, 2002.
[9] Gialuigi De Geronimo, Paul O'Connor, and Anand Kandasamy. Analog
cmos peak detect and hold circuits. part 2. the two-phase ofset-fee and
derandomizing confguration. Nuclear instruments and methods in
physics research A, 484:544-556, 2002.
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