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. _ _
TRJAST
2
PUR
_
_
__-_ ___ --
luU
000ODD
-----------
Fig 8. The pile up rejection strategy proposed. The length of the control
window T2 is equal to the decreasing tail of the semi-gaussian pulse. If a
trigger fast take place in this phase the T2 windows is extended for another
peaking time.
In the peak logic also another functionality has been
designed, there is the possibility to trig the logic with the main
shaper and not with the fast one. In this way, of course, the
9
947
pile up rejection circuit does not work but we can extend, for
low rate application, the energy range down to low values.
In both cases the threshold is set by a single DAC per
channel and can be fully programmable via SPI.
v. DATA ACQUISITION BOARD
The Data Acquisition Board (Fast-DAQ), realized by
XGLab, is based on an FPGA and performs both acquisition
and ASIC programming by SPI. It is able to read-out the ASIC
multiplexer up to 15 MHz. The analog signal is transmitted
fom the ASIC board to the Fast-DAQ in differential mode in
order to reduce pick-up disturbs. The signal is then sampled
with a commercial 16-bit resolution ADC. The sampled data is
buffered into the FPGA that stores the spectra (up to 8 spectra,
with fll ADC resolution) and then transmits via USB protocol
to the host Pc. The FPGA may be adapted for diferent ASICs
releases and readout schemes. All the acquisition parameters
(i.e. acquisition clock, ASIC confguration and other system
settings) are controlled through a custom sofware interface. A
simple data fow diagram and a picture of the complete system
(except for the Personal Computer) are shown in Fig. 9 and in
Fig. 10.
.
|P
_ADC
I
MEMORY
DATA BUS
11'"
SPECTRA
x
:
2
o
ACQUISIIR Ol
\
V
I
I
SPIINTERFACE
I
I
SYS TEM CONFIGURA TION TIMER
I US B FIF O
I
RESET/INHIBIT I C ONFIGURATION
I
1'
'
--
Fig 9. Data Flow Chart of the complete system.
-
I
1
w
t
'
:
:
! :
N
"
:
i
C
:
I
Fig 10. Picture of the complete system, the board on the lef (90mm x
150mm) hosts the 8-channels ASIC, the right one the FAST-DAQ.
VI. SYSTEM PERFORMACES
In this section, we show a selection of experimental results
obtained with this system.
In Fig.lO and Fig.ll, the output of the shaper at different
peaking time and at different gain is shown.
Fig 10. Output of the shaper at diferent peaking time, the yellow line is the
output of the fast shaper amplifer.
Fig I I. Output of the main shaper at diferent gain settings.
For X-ray spectroscopy tests, the ASIC has been connected
to a circular SOD and a CUBE preamplifer [4]. The reference
SOD here employed has an area of 10 mm
2
The measurement
are performed at -40C (SOD cooled with a Peltier cell) in
order to reduce as much as possible the noise associated to the
leakage current.
In Fig. 12, the measured spectrum of the
55
Fe source is
shown. The energy resolution at the Mn-Ka line is 126.2 eV
FWHM using the complete analog chain, with the 1.5 s
peaking time.
According to [4], the SOD + CUBE readout offers very
good performances at low shaping time, so we measured the
energy resolution also with the shortest peaking time (600 ns)
with different value of input count rate. In Fig. 13 we report a
measurement with an input count rate of 800 kcps and an
output count rate of 265 kcps on a single channel. The energy
948
resolution at the Mn-Ka line is 144.2 eV FWHM, a very
remarkable value at this peaking time and input count rate.
In Fig. 14 the output count rate vs. the input count rate is
plotted for all the 4 peaking times, the Poisson limit is also
shown for comparison. It possible to notice that the output
count rate is very close to the intrinsic Poisson limit.
12
X 10
4
10
8
V
+
C
6
:
0
U
4
2
.5 5
SS
Fe spectrum
1 .5 Is peaking time
Input count rate: 115 kcps
126.2eV FWHM
.l
5.5 6 6.5
Energy [KeV
7
.
7.5
Fig 12. Spectrum of the 5'Fe source measured with a SDD and the CMOS
CUBE preamplifer (temperature of _400 C). The best energy resolution of
126eV FWHM was achieved using 1. 5 Is peaking time. The input count rate
is 115 kcps, the output 92 kcps. The input count rate is estimated with a
commercial digital pulse processor.
55
Fe spectrum
600 ns peaking time
Input count rate: 800 kcps
14.2 eV FWHM
--
Fig 13. Spectrum of the 55Fe source measured with a SDD and the CMOS
preamplifer, at a temperature of _400 C. The peaking time of the shaper is 600
ns. The input count rate is 800 kcps, the output count rate 265 kcps.
A test with 4 CUBE preamplifers has been exploited and
we have obtained a total output count rate of 1.4 Mcps with an
input count rate of 3 Mcps with DAQ and MUX in Ultra-Fast
Mode (Fig. 15).
We also tested the speed capabilities of the Fast-DAQ by
pulsing 4 channels. The system shows an excellent throughput
performance, allowing the user to operate 4 channels up to
3.75 Mcps/channel input rate (Ultra-Fast Mode) or 8 channels
at 1. 8 Mcps/channel (Fast Mode).
1000
"i
O
U
N
+
C
D
O
L
'
10
B
O
0
10 100
Input Count Rate (kcps)
1000
Peaking time
O.6us
- -0.6us (Poisson Lmt.)
..1.Sus
- 1.5U5 (Poisson lrt.)
_2.2u5
~"2.2u5 (Poisson lrt.)
4.0us
- 4.0U5 (Poisson Lmt.)
Fig 14. Output count rate vs. input count rate, for diferent peaking time;
the Poisson limits are the dashed lines.
c10000
a Total input count rate: 3 Mcps
Total output count rate: 1.4 Mcps
Q 1000
Peaking time: 600 ns
-
t
0:
-
100
o
o
-
::
a 10
-
::
10
o
100 1000 10000
Input Count Rate (kcps)
Fig 15. Output count rate vs. input count rate, for 4 SODs connected to 4
chanels, Ultra-Fast Mode setting.
Finally, we have tested the pile-up rejection system. To
exploit the beneft of the pile-up rejection we have acquired a
spectrum with and without the pileup rejection system
enabled. The result is shown in Fig. 16. The plateau at high
energy due to the pile-up effect is very well reduced by almost
two orders of magnitude in the spectrum acquired with the
pile-up rejection enabled. It is known that the pile-up is less
efcient to reject photons close to the peaking time of the fast
shapero Therefore, the circuit is not able to identif the arrival
of two photons too close in time fom one photon with the
sum of energies. As result, the visible peaks in Fig. 16 at about
double or triple the Mn-Ka energy are reduced less
effectively.
W
+
T
5 T
o
U
T T4
Energy [keY]
Tl|QI0!|0-UQ
Fig 16. Efectiveness of the pileup rejection strategy. Comparison of the
typical spectra acquired with PUR disabled (in red) and with PUR enabled (in
blue). The peaking time is 600ns and the estimated input count-rare is 265
kcps.
VII. CONCLUSIONS
We have developed an integrated circuit that implements in
a monolithic solution most of the functionality required for an
X-Ray spectroscopic processing system.
The ASIC is designed to operate directly connected to SOD
with interal JFET or with SOD coupled to CMOS
preamplifer. The ASIC is conected to a FPGA-based DAQ.
The circuit is composed by 8 identical analog channels and by
a digital section. The chip has been realized and successfully
tested. The chip is flly working and the performances have
been evaluated and presented in this work.
Spectroscopic measurements have been carried out with a
SOD at the different peaking time in order to asset the best
tradeof between noise and count rate capability. The energy
resolutions achieved are very closed to the one obtained with
non integrated systems.
The architecture can handle rate up to 800 kHz per channel
with low dead time and high throughput. Moreover, the
implemented architecture can be expanded in the future to a
larger number of channels.
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[II
P.Lechner, et a!., "Silicon drif detectors for high count rate X-ray
spectroscopy at room temperature", Nucl. Instr. and Meth., A 458, 281-
287, 2001.
[2
1
T. Nashashibi,"The Pentafet and its applications in high resolution and
high rate radiation spectrometers ", Nuclear Instruments and Methods in
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551-556.
[3
1
L.Bombelli, C.Fiorini, T.Frizzi, R.Nava, AOreppi, ALongoni "Low
noise CMOS Charge "Preamplifer for X-ray Spectroscopy Detectors"
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[4
1
L. Bombelli, C. Fiorini, T. Frizzi, R. Alberti, A Longoni, " CUBE, A
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949
[5] Goulding, F.S. ; Landis, D. A.; Madden, N.W. Design philosophy for
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