Alphabetical List of Instructions

ACALL: Absolute Call ADD, ADDC: Add Accumulator (With Carry) AJMP: Absolute Jump ANL: Bitwise AND CJNE: Compare and Jump if Not Equal CLR: Clear Register CPL: Complement Register DA: Decimal Adjust DEC: Decrement Register DIV: Divide Accumulator by B DJNZ: Decrement Register and Jump if Not Zero INC: Increment Register JB: Jump if Bit Set JBC: Jump if Bit Set and Clear Bit JC: Jump if Carry Set JMP: Jump to Address JNB: Jump if Bit Not Set JNC: Jump if Carry Not Set JNZ: Jump if Accumulator Not Zero JZ: Jump if Accumulator Zero LCALL: Long Call LJMP: Long Jump MOV: Move Memory MOVC: Move Code Memory MOVX: Move Extended Memory MUL: Multiply Accumulator by B NOP: No Operation ORL: Bitwise OR POP: Pop Value From Stack PUSH: Push Value Onto Stack RET: Return From Subroutine RETI: Return From Interrupt RL: Rotate Accumulator Left RLC: Rotate Accumulator Left Through Carry RR: Rotate Accumulator Right RRC: Rotate Accumulator Right Through Carry SETB: Set Bit SJMP: Short Jump SUBB: Subtract From Accumulator With Borrow SWAP: Swap Accumulator Nibbles XCH: Exchange Bytes XCHD: Exchange Digits XRL: Bitwise Exclusive OR Undefined: Undefined InstructionHKHHIHA

Classic 8051
Home Architecture Overview Memory Classes and Layout Classic 8051 The following table shows the memory classes used for programming the classic 8051 architecture. These memory classes are available when you are using the A51 macro assembler and the BL51 linker/locater. Memory Class DATA BIT Address Range D:00 D:7F D:20 D:2F Description

Direct addressable on chip RAM. bit addressable RAM; accessed bit instructions. Indirect addressable on chip RAM; can be accessed IDATA I:00 I:FF with @R0 or @R1. 64 KB RAM (read/write access). Accessed with XDATA X:0000 X:FFFF MOVX instruction. 64 KB ROM (only read access possible). Used for CODE C:0000 C:FFFF executable code or constants. BANK 0 B0:0000 B0:FFFF Code Banks for expanding the program code space to BANK 31 B31:0000 B31:FFFF 32 x 64KB ROM. Note

The memory prefix D: I: X: C: B0: .. B31: cannot be used at Ax51 assembler or BL51 linker/locater level. The memory prefixes are only listed for better understanding. Several Debugging tools, for example the Vision Debugger, are using memory prefixes to identify the memory class of the address.

Classic 8051 Memory Layout

Home Architecture Overview Memory Classes and Layout Classic 8051 Memory Layout The classic 8051 memory layout, shown in the following figure, is familiar to 8051 users the world over. The classic 8051 architecture includes the following memory classes.

BIT, DATA, and IDATA

The BIT, DATA, and IDATA memory classes comprise the on-chip memory of the 8051 architecture and are shown in the following figure.

CODE and CONST

The CODE and CONST memory classes are typically stored in ROM that may be either off-chip or on-chip. The CODE memory class is used for the actual program code while the CONST memory class is used for constant variables declared in code space.

In addition, up to 32 code banks may be used for code banking applications. While these are technically located in code space, they are assigned their own address space.

XDATA and PDATA

The XDATA memory class is typically stored in RAM that may be off-chip or on-chip (on newer devices). It contains external program data (named because it was off-chip on the original 8051 devices) including variables declared with the xdata and pdata memory types. The PDATA memory class is a 256-byte page within the XDATA memory class.

Program Status Word (PSW)

Home Architecture Overview CPU Registers Program Status Word (PSW) The Program Status Word (PSW) contains status bits that reflect the current CPU state. The 8051 variants provide one special function register called PSW with this status information. The 251 provides two additional status flags, Z and N, that are available in a second special function register called PSW1.

PSW Register (all 8051 and 251 variants)

Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0 CY AC FO RS1 RS0 OV UD P

Additional PSW1 Register (on 251 Architecture only)

Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0 CY AC N RS1 RS0 OV Z The following table describes the status bits in the PSW: RS1 RS0 Working Register Bank and Address 0 0 Bank0 (D:0x00 - D:0x07) 0 1 Bank1 (D:0x08 - D:0x0F) 1 0 Bank2 (D:0x10 - D:0x17) 1 1 Bank3 (D:0x18H - D:0x1F) Symbol Function CY Carry flag AC Auxiliary Carry flag (For BCD Operations) F0 Flag 0 (Available to the user for General Purpose) RS1, Register bank select: RS0 RS1 RS0 Working Register Bank and Address 0 0 Bank0 (D:0x00 - D:0x07) 0 1 Bank1 (D:0x08 - D:0x0F) 1 0 Bank2 (D:0x10 - D:0x17)

0V UD P Z N

1 1 Bank3 (D:0x18H - D:0x1F) Overflow flag User definable flag Parity flag Reserved for future use (251 Only) Zero flag (251 Only) Negative flag (251 Only)