Sie sind auf Seite 1von 11

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 58, NO.

1, JANUARY 2011 221


Robust and Fast Three-Phase PLL Tracking System
Felice Liccardo, Pompeo Marino, and Giuliano Raimondo
AbstractThis paper presents a simple, robust, and fast syn-
chronization method to detect the phase angle of the positive
sequence of a three-phase ac system. The algorithm was derived
from a standard phase-locked-loop (PLL) circuit based on the pq
theory, but a feedforward action is implemented to guarantee high
dynamic performance in conjunction with a modied feedback
action to reduce the phase-angle estimation error to zero. The
result is a fast tracking system that improves the start-up stage
and rapid input variations. It guarantees accurate phase locking
and is robust with respect to ac distortions such as harmonics,
subharmonics, and voltage imbalance. The control model for the
proposed PLL system was based on the standard qPLL structure.
A linear analysis was performed to show the benets of the
proposed solution, and recommendations are given for tuning its
parameters. The proposed technique was tested and compared
with other algorithms by means of simulations. The experimental
and simulation results are shown and compared.
Index TermsPhase-locked loop (PLL), power systems, syn-
chronization, utility interface.
I. INTRODUCTION
T
HE growing use of static converters in both three- and
single-phase applications requires a fast and accurate
method for phase-angle estimation. This is a very important
task in any application where active/reactive power ow control
is needed. This control should guarantee the good operation
of the power-conditioning equipment connected to the utility
grid, such as an active front end (AFE), active lters, static
VAR compensator, uninterruptible power supply, exible ac
transmission systems, etc. [1][6].
The wide diffusion of distributed generation (DG) units in
electric networks has required the large use and improvement
of synchronization algorithms to detect the positive sequence
component of the utility network. In fact, when used as a wind
generator unit, photovoltaic-based unit, or microturbine gen-
erator unit, a converter-interfaced DG unit requires converter
synchronization under a polluted and/or variable-frequency
environment, both in grid-connected and microgrid (islanding)
congurations [7][13]. Moreover, due to the high number
of loads connected to a grid and the continuous variation of
network conditions, the synchronization process should be fast
and robust. These performances guarantee disturbance rejection
and fast algorithm convergence.
Hence, an ideal synchronization algorithm should detect the
phase angle of the positive sequence of the voltage system, with
Manuscript received July 31, 2009; revised January 12, 2010; accepted
February 16, 2010. Date of publication March 8, 2010; date of current version
December 10, 2010.
The authors are with the Dipartimento di Ingegneria dellInformazione,
Second University of Naples, 81031 Aversa, Italy (e-mail: felice.liccardo@
unina2.it; p.marino@unina.it; giuliano.raimondo@unina2.it).
Color versions of one or more of the gures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identier 10.1109/TIE.2010.2044735
Fig. 1. Basic PLL structure.
the ability to track the phase and frequency variations even if the
supply voltages are distorted and unbalanced.
Various phase-detecting methods have been proposed
[14][16]. The simplest, but not the most accurate method
under nonideal conditions, is the zero-crossing strategy. Even
if they are better than the zero-crossing method, techniques
based on low-pass lters (LPFs), space vector lters (SVFs), the
recursive weighted least-square estimation algorithm, Kalman
lters, or the fast Fourier transform do not have the best
performance under polluted supply conditions. Other methods
for managing the frequency and amplitude variations are based
on the concept of the adaptive notch lter (ANF).
The phase-looked-loop (PLL) technique, based on the syn-
chronous reference frame (SRF), is the most comprehensive
method under polluted supply conditions [17][23]. The basic
scheme of the conventional PLL method is shown in Fig. 1. The
simplicity of this structure makes this synchronization method
the most widely accepted solution, owing to the simple analog
and digital implementations. Based on a feedback structure and
the theory of dq transformations [1], a classical PLL struc-
ture comprises a phase detector, loop lter (LF), and voltage-
controlled oscillator. These structures have good performance
even with signals affected by harmonics, interharmonics, volt-
age sags, swells, and notches. On the other hand, they start to
present disadvantages in unbalanced operating conditions. In
the literature, various kinds of PLL methods have been tried to
overcome the aforementioned problems, such as enhanced PLL
(EPLL) and decoupled double SRF PLL. These methods are
complicated compared with the conventional PLL system, and
when the signal is distorted by harmonics, the bandwidth should
be reduced, thus increasing the time response. Moreover, the
start-up stage does not have a good dynamic response.
Three-phase PLL systems based on Akagis instantaneous
power pq theory [24],[25] have been intensely studied an-
alytically and experimentally, under both asymmetrical and
distorted supply conditions. The design criteria have also been
analyzed to tune their parameters. These PLL systems are
classied as pPLL and qPLL.
A modied classical qPLL closed-loop structure incorporat-
ing a feedforward action was presented and simulated in [26].
This feedforward action guarantees high dynamic estimation
0278-0046/$26.00 2011 IEEE
222 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 58, NO. 1, JANUARY 2011
Fig. 2. qPLL system.
performance and the reduction of the residual estimation error
to zero.
This paper can be considered to be an extension of [26]. It
introduces and analyzes the effect of the frequency variation on
the proposed solution, showing the good performances obtained
during start-up under all input conditions and providing a com-
plete linear analysis of the system stability in order to dene
accurate controller parameter design criteria. Moreover, nu-
merical results have been obtained by comparing the proposed
technique with the standard qPLL algorithm and recent syn-
chronization techniques proposed in literature. Experimental
verications were also carried out under various input voltage
conditions. The proposed feedforward qPLL (FFqPLL) gives
fast and accurate phase and frequency detection of the posi-
tive sequence of the input signals, particularly in the start-up
stage, with rapid input variation, and under unbalanced utility
conditions. The simplicity of the structure makes the presented
phase-nding system suitable for digital implementation.
II. CONVENTIONAL PLL SYSTEM
A PLL is a device that is able to keep an output signal
synchronized in frequency, as well as in phase, with a reference
input signal. More precisely, the PLL is a servo system that
controls the phase of its output signal in order to minimize
the phase error between the output and reference phases. A
traditional PLL analysis system is based on a single input
system, as shown in Fig. 1. In the case of three-phase input
signals, a small simplication is needed and the inputs can eas-
ily be converted into a stationary plane through the Clarke
transformation or into a synchronously rotating reference frame
through the Park transformation. Starting from the -plane
representation of the three-phase input and adopting the space
vector representation proposed by Aredes in [23], the phase
error signal can be expressed as
u
d
(t) = (u
1
u
2
+u
1
u
2
) +j(u
1
u
2
u
1
u
2
). (1)
By applying Akagis instantaneous power theory [24], [25],
two different approaches can be adopted to estimate the input
signal phase angle. The rst uses the real part of u
d
and yields a
pPLL system, while the second uses the real part of u
d
to yield
a qPLL system.
The conceptual scheme of a classical qPLL system for a
utility interface is shown in Fig. 2, where
d,n
is the nominal
line pulsation. Referring to the following symmetrical voltage
system:
v
abc
= V [ sin sin
_

2
3
_
sin
_
+
2
3
_
] (2)
where V and are the amplitude and the phase angle, respec-
tively, Clarkes transformation is characterized by the following
matrix:
T
c
=
_
2
3
_
1 1/2 1/2
0

3/2

3/2
_
(3)
which gives rise to the voltage system (v

, v

)
v

=
_
3
2
V [ sin cos ] (4)
which represents the voltage system (2) in the plane. Then,
the algorithm in Fig. 2 can be used to calculate and regulate to
zero the quantity
q(t) = v

= 3/2 V sin(

q
) (5)
which is Akagis imaginary power associated both with the
voltage system (2) and the ctitious current system (i

, i

).
This represents a balanced current system with unitary ampli-
tude and phase angle

q
in the plane.
Due to the action of the LF [typically proportionalintegral
(PI) controller], the algorithm in Fig. 2 may reach two equi-
librium points under steady-state conditions. The former is
characterized by

q
=

q
= (6)
and is unstable. In fact, if a slight positive phase variation
occurs, then
q
> . For (5), q(t) becomes negative and the
action of the controller increases
q
. Likewise, if a slight
negative variation makes
q
< , then the algorithm further
reduces the value of
q
. The latter equilibrium point

q
= 0 (7)
is stable. In fact, if a slightly positive phase variation occurs,
making
q
> 0, for (5), q(t) becomes positive and the action
of the controller reduces
q
. Analogously, if a slight negative
variation makes
q
< 0, then the algorithm reduces the value
of
q
to zero.
The PI controller is used in conjunction with a feedforward
action at the nominal pulsation
d,n
and is saturated in order to
increase the dynamic performance of the qPLL and avoid phase
locking on an eventual interharmonic component of the voltage
system.
The conceptual scheme of a classical robust pPLL system for
a utility has the same structure as that in Fig. 2. In addition, this
algorithm relies on the transformation in (3), which is used to
obtain the voltage system (v

, v

) expressed by (4). Then, it


calculates and regulates to zero the p(t) value dened as
p(t) = v

+v

= 3/2 V cos(

p
) (8)
which is Akagis real power ([4]), which is associated with
both the voltage system (2) and the ctitious current system
(i

, i

) and represents a balanced current system with unitary


amplitude and phase angle

p
in the plane.
LICCARDO et al.: ROBUST AND FAST THREE-PHASE PLL TRACKING SYSTEM 223
Fig. 3. FFqPLL.
Moreover, it can be shown [20] that, due to the action of the
controller, the algorithm may reach two equilibrium points. The
former is characterized by

p
=
d

p
= /2 (9)
and is unstable. The latter, which is stable, is characterized by

p
=
d

p
= /2. (10)
All of the results that are presented next are for a qPLL
system, but are also applicable to a pPLL system.
A conventional PLL system implemented in an SRF uses a PI
controller to track the phase angle of the grid voltages. The con-
troller parameters represent a tradeoff between a fast dynamic
system providing quick synchronization and a slow dynamic
system providing an accurate ltered output. Therefore, under
ideal grid conditions, the conventional SRF-PLL gives good
results. Under distorted and/or unbalanced supply voltages, the
bandwidth of the PLL controller should be further reduced to
provide a good synchronization signal. However, reducing the
PLL bandwidth results in an increase in response time, which
means that the system cannot track the phase angle () quickly.
III. PROPOSED PHASE TRACKING SYSTEM
The proposed system is shown in Fig. 3. The idea is to
use an open-loop synchronization method as a forward action
for a modied classic qPLL. This tracking system has several
advantages in terms of dynamics.
A. Input Signal Analysis
Referring to the following asymmetrical and distorted volt-
age system, made of the sum of positive sequence and negative
sequence distorted systems:
v
a
=
+

k=1
[V
d,k
sin(
d,k
) +V
i,k
sin(
i,k
)]
v
b
=
+

k=1
_
V
d,k
sin
_

d,k

2
3
k
_
+V
i,k
sin
_

i,k
+
2
3
k
__
v
c
=
+

k=1
_
V
d,k
sin
_

d,k
+
2
3
k
_
+V
i,k
sin
_

i,k

2
3
k
__
(11)
where V
d,k
and V
i,k
are the amplitude of the kth harmonic com-
ponent of the aforementioned positive and negative sequence
Fig. 4. Feedforward action.
systems and
d,k
and
i,k
are their phase angles, respectively. If
V
d,k
= 0 for k > 1 and V
i,k
= 0 for any k, then (11) coincides
with (2). With this assumption, q(t) can be expressed as
q(t)=
3
2
+

k=1
V
d,k
sin(
d,k

d,q
)+
3
2
+

k=1
V
i,k
sin(
i,k

d,q
).
(12)
This equation can be divided into a dc component to be
controlled to zero and a disturbance component as follows:
q(t) =q(t) + q(t)
q(t) =
3
2
V
d,1
sin(
d,1

d,q
)
q(t) =
3
2
+

k=2
V
d,k
sin(
d,k

d,q
)
+
3
2
+

k=1
V
i,k
sin(
i,k
+

d,q
). (13)
The disturbance component q(t) consists of the innite sum
of the sinusoidal signals at frequency multiples of the line
frequency, around the stable equilibrium point (7).
For any type of voltage system, it is possible to dene the
quantity q(t) and, thus, the lower disturbance frequency. This
is useful information for the LF design. When the system is
affected by an interharmonic component, the situation is more
critical because q(t) may oscillate at a very low frequency.
B. Feedforward Action
The feedforward action shown in Fig. 4 guarantees the high
dynamic performance of the phase locking in the start-up stage,
as well as the low error in the steady state, in the presence of
asymmetrical and distorted supply voltage systems. Moreover,
it is possible to estimate the frequency with high precision and
fast dynamics. By taking into consideration the voltage system
(2), whose representation in the plane is expressed by (4),
and applying a reference rotation synchronous with the nominal
line frequency, the dq representation is obtained
_
v
d
v
q
_
=
_
sin
n
cos
n
cos
n
sin
n
_ _
v

_
=
_
3
2

cos(
d,1

n
)
. .
=v
d
cos(
d,1
+
n
)
. .
= v
d
sin(
d,1

n
)
. .
=v
q
+sin(
d,1
+
n
)
. .
= v
q

(14)
where
n
= 2f
n
t is the phase related to the nominal frequency
(e.g., 50Hz). The phase relatedtothe real supplyfrequencyf
d,1
is

d,1
= 2f
d,1
t +
0
d
(15)
224 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 58, NO. 1, JANUARY 2011
where
0
d
is the initial phase of the positive sequence of the
supply voltage system (2). By low-pass ltering (14) and taking
into account that the lower frequency to eliminate is related to
f
d,1
+f
n
, the following quantities are obtained:
v
d
=
_
3
2
cos
_
2 f t +
lpf
+
0
d
_
=
_
3
2
cos(
f
)
v
q
=
_
3
2
sin
_
2 f t +
lpf
+
0
d
_
=
_
3
2
sin(
f
) (16)
where f = f
d,1
f
n
and
lpf
is the phase delay introduced
by LPF
f
. By evaluating the arctangent of v
q
on v
d
, it is
possible to extract
f
. If the supply voltage frequency and the
nominal one are the same, f = 0,
lpf
= 0, and the extracted
value represents the initial phase. If f = 0, this implies that

lpf
= 0 and a phase estimation error is obtained. In this case,
the feedback action will compensate for the error. In any case,
summing to
f
, i.e., the nominal phase,
d,1
+
lpf
is obtained.
After deriving this quantity, the supply voltage frequency can be
evaluated. The dynamic response and the steady-state precision
are strictly connected to the LPF
f
cutoff frequency chosen.
The bandwidth and the order of the LPF
f
must be deter-
mined with reference to the voltage system (11), considering
that the dq components present a disturbance component, as in
v
d
=
3
2
+

k=2
V
d,k
cos(
d,k

n
)

3
2
+

k=i
V
i,k
cos(
i,k
+
n
) (17)
v
q
=
3
2
+

k=2
V
d,k
sin(
d,k

n
)
+
3
2
+

k=i
V
i,k
sin(
i,k
+
n
). (18)
Therefore, it must be taken into account that the lower
frequency involved in (17) and (18) is equal to the line fre-
quency and is due to the second-order harmonic of the negative
sequence system. Even more critical is the situation connected
to the voltage system when affected by an interharmonic
component. In fact, v
d
and v
q
may oscillate at a very low
frequency when the interharmonic component is located near
the component at the line frequency.
C. Feedback Action
As mentioned before, if the supply frequency is not exactly
equal to its nominal value, v
d
and v
q
in (14) are not dc
quantities. Therefore, during the low-pass ltering, they are
affected by the phase distortion of LPF
f
and
lpf
= 0. Hence,
the resulting angle
f
is not exactly equal to
d,1
and is affected
by a constant estimation error for a constant line frequency
different from f
d,n
. In order to reduce this residual estimation
error to zero, the use of the feedback action, based on the
conventional PLL scheme shown in Fig. 3, is proposed. Due
to the aforementioned feedforward action, this last ensures
a tracking error equal to zero for a constant line frequency
different from f
n
.
Fig. 5. Linearized model of the FFqPLL.
In this case, the gain k
p
of the controller and the time constant

f
of the LPF have to be determined while also taking into
account the inuence of the residual voltage disturbance effects
on the feedforward action on

d
.
IV. LINEAR ANALYSIS AND DESIGN CRITERIA
This section discusses considerations about the design crite-
ria of the proposed phase-locking system.
The FFqPLL can be modeled in the Laplace domain, as
shown in Fig. 5. The feedforward transfer function G(s) de-
pends only on the associated LPF LPF
f
. The poles of this lter
are external to the feedback loop. Hence, the presence of the
feedforward action is not relevant in terms of stability. Thus, in
the following analysis, it will not be considered. However, the
stability analysis is very similar to a conventional qPLL.
The qPLL and pPLL can be analyzed using the same ap-
proach. For this reason, only the former will be considered in
this section. A small tracking error is hypothesized near the
equilibrium point, i.e.,

d,q

=
d
. (19)
It is worth noting that the pPLL also admits a linearization
model with the structure of the system in Fig. 5, near the
equilibrium point

d,p

= /2. (20)
Using the model in Fig. 5, it is possible to evaluate the
transfer functions describing the PLL behavior. The transfer
function considered for the rst-order low-pass lter and the
PI controller are reported in
PI = k
p
+
k
i
s
LPF =
1
1 +s
f
. (21)
A. Stability
The system stability can be studied by evaluating transfer
function

d,q
, as shown in

d,q
(s) = F
1
(s)
d,1
(s) +F
2
(s)
n
(s) +F
3
(s)

Q(s) (22)
where
F
1
(s) =
V
d,1
(k
p
s +k
i
)
s
3

f
+s
2
+
3
2
V
d,1
k
p
s +
3
2
V
d,1
k
i
(23)
F
2
(s) =
G(s)
s
3

f
+s
2
+
3
2
V
d,1
k
p
s +
3
2
V
d,1
k
i
(24)
F
3
(s) =
k
p
s +k
i
s
3

f
+s
2
+
3
2
V
d,1
k
p
s +
3
2
V
d,1
k
i
. (25)
LICCARDO et al.: ROBUST AND FAST THREE-PHASE PLL TRACKING SYSTEM 225
Fig. 6. Maximum k
i
value versus k
p
and LPF cutting frequency f
t
.
The system is stable if the characteristic polynomial (26)
only has roots with negative real parts
p(s) = s
3

f
+s
2
+
3
2
V
d,1
k
p
s +
3
2
V
d,1
k
i
. (26)
Using the Routh criteria, the stability is guaranteed if condi-
tion (27) is veried
k
p
k
i
>
f
. (27)
The previous equation shows that the stability is dependent
on the PI and LPF parameters. A fast graphical approach useful
for designing the system is shown in Fig. 6. For the selected k
p
and lter cutting frequency f
t
, the graph reports the maximum
admissible k
i
values for a stable system.
B. Error Estimation
The error dynamic can be analyzed by means of
E(s) = E
1
(s)
d,1
(s) +E
2
(s)
n
(s) +E
3
(s)

Q(s) (28)
where
E
1
(s) =
(1 +s
f
)s
2
s
3

f
+s
2
+
3
2
V
d,1
k
p
s +
3
2
V
d,1
k
i
(29)
E
2
(s) =
G(s)
s
3

f
+s
2
+
3
2
V
d,1
k
p
s +
3
2
V
d,1
k
i
(30)
E
3
(s) =
k
p
s +k
i
s
3

f
+s
2
+
3
2
V
d,1
k
p
s +
3
2
V
d,1
k
i
. (31)
Equation (28) can also be used to evaluate the steady-state
error. By considering the feedforward input
n
(s) and the
phase input
d,1
(s) as ramp inputs, the steady-state error is
reported in
e

(t) = e
1
+e
2
+
n

i=1
A
qi
|E
3
(j
qi
)|
sin (
qi
t +
qi
+Arg [E
3
(j
qi
)]) (32)
TABLE I
PLL PARAMETERS
where the presence of n generic disturbances have been consid-
ered, as shown in
q(t) =
n

i=1
A
qi
sin(
qi
t +
qi
) (33)
according to the nal value theorem
e
1
= lim
s0
sE
1
(s)

d,1
s
2
= 0 e
2
= lim
s0
sE
2
(s)

n
s
2
0. (34)
In (34), e
2
can be considered to be almost equal to zero
because, when the gains of transfer functions (30) and (31) are
compared, the rst one always presents a higher attenuation in
the disturbed frequency range.
It is clear from (32) and (34) that if the voltage is not
contaminated by disturbances such as harmonics or an un-
balance, the steady-state error is zero. Otherwise, it depends
on the disturbance entity according to (32). The designer can
use the aforementioned equations for the desired disturbance
attenuation and, thus, the desired steady-state error.
If the ltering of

Q(s) is delegated to the PI controller as in
a conventional PLL, an analysis can be made by evaluating all
of the transfer functions with
f
= 0. In this case, the system
is always stable and k
i
and k
p
have to be chosen accurately in
order to have an acceptable disturbance attenuation.
The presence of the lter leads to better results in terms
of disturbance attenuation, such as unbalances. However, the
system bandwidth is smaller, and therefore, the dynamic re-
sponse is reduced. Adding the feedforward action enhances the
dynamic response.
V. SIMULATION RESULTS
In this section, several simulation results are shown in order
to validate the analysis reported in the previous section and to
compare the conventional qPLL with the proposed topology.
These numerical simulations were obtained from Simulink
models. The parameters used are reported in Table I.
A. Start-Up
As a rst case, a noncontaminated direct sequence voltage
can be considered with amplitude V
d
= 100 V. The considered
initial phase values (
d
) are /8, /4, and /2.
The start-up stage will be considered in order to evaluate the
phase locking. All of the results are shown in Figs. 79. These
show that, as stated in Section I, the steady-state error is zero in
the case of a nondistorted voltage.
In all of the simulation results, it is possible to observe that
the FFqPLL error is always smaller than the classical qPLL,
independently from the initial phase. This means that, during
the start-up stage, the synchronization error is reduced, leading
to a higher power factor.
226 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 58, NO. 1, JANUARY 2011
Fig. 7.
d
= /8. (1) Phase error. (2) qPLL output. (3) FFqPLL output.
Fig. 8.
d
= /4 phase error.
Fig. 9.
d
= /2 phase error.
In order to test the start-up stage even when a disturbance is
present, simulations were carried out in the case of a nonideal
supply. The results shown in Fig. 10(a)(1) show the start-up
phase error in the case of a nonideal supply frequency of
48 Hz. Moreover, in Fig. 10(b)(1) and (c)(1), the presence
of a 30% unbalance and 1-Hz subharmonic is considered.
The respective locked frequencies are shown in Fig. 10(a)(2),
10(b)(2), and 10(c)(2). The simulation results show that, even
in the case of nonideal voltages, the FFqPLL presents a smaller
error in the start-up period.
B. Disturbed Voltage
In order to evaluate the performance of the PLL in a dis-
torted network, a disturbed voltage is considered in the next
simulations.
1) Unbalance: The presence of a 30% unbalance can be
analyzed considering V
d
= 100 V and V
i
= 30 V. The initial
phases considered in the simulations are
d
= 0 and
I
= 0.
In order to evaluate the benets of the proposed method, the
parameters reported in Table I have been chosen to give the
same system dynamics.
LICCARDO et al.: ROBUST AND FAST THREE-PHASE PLL TRACKING SYSTEM 227
Fig. 10. Start-up in nonideal conditions.
Fig. 11. Error E
3
(s) bode diagram.
The E
3
(s) bode diagram is shown in Fig. 11 to evaluate the
steady-state error. In this case, the disturbance is
q(t) =
3
2
30 sin(2100t +
d
+
i
). (35)
The amplitude attenuation is |E
3
(j2100)|
dB
= 78; there-
fore, the resultant steady-state error amplitude is 0.0057 rad.
The disturbance is introduced at 1 s. Fig. 12(1) shows the
error dynamics, with an enlargement shown in Fig. 12(2). In
the latter gure, only the effect of E
3
(s) is appreciable, while
the error due to E
2
(s) is negligible, as shown in Section IV.
Fig. 12. 30% unbalancephase error. (1) Phase error. (2) Phase-error
enlargement.
It is possible to observe that the FFqPLL and the conventional
PLL have the same dynamics, but the former presents a higher
attenuation as expected.
228 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 58, NO. 1, JANUARY 2011
Fig. 13. Phase error for 10% fth and 5% eleventh harmonics.
d
= 0,
i,5
= 0, and
i,11
= 0.
Fig. 14. Phase error for 10% subharmonic.
Fig. 15. Supply frequency variation.
2) Harmonics: The presence of harmonics can also be con-
sidered in this section. A 10% fth harmonic and a 5% eleventh
harmonic are added to the fundamental at 1 s. The PLLs
parameters are the same as those in the case of unbalance.
The results are shown in Fig. 13.
3) Subharmonics: The performances of the PLLs in the
presence of 10% subharmonic oscillations at a very low fre-
quency (1 Hz) are illustrated in this case. Fig. 14 shows the
simulation results.
4) Supply Frequency Variation: To test the performance of
the proposed PLL during supply frequency variation, a 2-Hz
drop of 2-s duration was given at 0.4 s. The settling time was
found to be about 120 ms (Fig. 15).
In all of the aforementioned simulations, the conventional
qPLL and the FFqPLL successfully locked the desired phase
even under distorted conditions. Comparing the two systems,
the FFqPLL has shown improved performance, owing to the
benets of the error ltering and the feedforward action. In fact,
the presence of the feedforward action enhances the system
dynamics, which are reduced by the LPF needed to have a small
steady-state error.
Compared with the new PLL topologies, such as ANF based
or EPLL, the proposed technique seems to show comparable
TABLE II
PLL PARAMETERS
results in terms of dynamics and steady-state error. However,
FFqPLL presents higher dynamics in the start-up stage under
all nonideal supply conditions. Moreover, the simplicity of
FFqPLL makes this an interesting technique for both analog
and digital implementations.
Finally, the simulation results conrm the linear analysis
made in Section IV.
VI. EXPERIMENTAL RESULTS
In this section, several experimental results are presented.
The qPLL and the FFqPLL were implemented with xed-point
arithmetic in a TMS320F240 DSP using an analog-to-digital
converter at a 10-kHz sampling frequency. A controlled power
source was employed to generate the desired input voltage. The
parameters used are reported in Table II.
LICCARDO et al.: ROBUST AND FAST THREE-PHASE PLL TRACKING SYSTEM 229
Fig. 16. Nondistorted input voltage. (1) qPLL output. (2) FFqPLL output. (3) qPLL phase error. (4) qPLL phase error.
Fig. 17. 12.5% unbalanced input voltage. (1) qPLL output. (2) FFqPLL output. (3) qPLL phase error. (4) qPLL phase error.
In order to compare the experimental and simulation results,
the same conditions as those in the previous section were con-
sidered for the input voltage. The results shown in Figs. 1619
show that the experimental results match the numerical ones.
Each gure shows that the PLL outputs overlapped with the
reference phase voltage and that the evaluated PLL error is
comparable with that of the simulation.
VII. CONCLUSION
In this paper, a robust and fast three-phase tracking sys-
tem has been shown. The proposed PLL structure for the
estimation of the phase angle of the fundamental positive
sequence of the supply voltage system consists of feedfor-
ward and feedback actions. This PLL, compared with the
classical qPLL and pPLL structures, improves the dynamic
and steady-state estimation performances. The start-up stage
is very fast in any utility condition, and the performances
in unbalanced conditions are better than conventional PLL
systems and are comparable with the most recent algorithms
proposed in the literature. Moreover, the proposed method
tracks the frequency variations well. A steady-state error analy-
sis in the Laplace domain was performed to dene the design
criteria.
Simulation and experimental results were compared and
showed good agreement.
230 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 58, NO. 1, JANUARY 2011
Fig. 18. 10% fth and 5% eleventh harmonics in input voltage. (1) qPLL output. (2) FFqPLL output. (3) qPLL phase error. (4) qPLL phase error.
Fig. 19. 10% subharmonics at 1 Hz in input voltage. (1) qPLL output. (2) FFqPLL output. (3) qPLL phase error. (4) qPLL phase error.
The proposed PLL can be employed in any supply voltage
condition in order to lock the positive sequence component,
and the simplicity of this structure makes the presented phase-
locking system suitable for digital implementation.
REFERENCES
[1] G. C. Paap, Symmetrical components in the time domain and their appli-
cation to power network calculations, IEEE Trans. Power Syst., vol. 15,
no. 2, pp. 522528, May 2000.
[2] B. Singh, K. Al-Haddad, and A. Chandra, A review of active lters for
power quality improvement, IEEE Trans. Ind. Electron., vol. 46, no. 5,
pp. 960971, Oct. 2001.
[3] G. Bonifacio, A. Lo Schiavo, P. Marino, and A. Testa, A new high
performance shunt active lter based on digital control, in Proc. IEEE
PES Winter Meeting, 2000, vol. 4, pp. 29612966.
[4] S.-K. Chung, A phase tracking system for three phase utility interface
inverters, IEEE Trans. Power Electron., vol. 15, no. 3, pp. 431438,
May 2000.
[5] F. Blaabjerg, R. Teodorescu, M. Liserre, and A. V. Timbus, Overview
of control and grid synchronization for distributed power generation
systems, IEEE Trans. Ind. Electron., vol. 53, no. 5, pp. 13941409,
Oct. 2006.
[6] F. Liccardo, P. Marino, and M. Trigianese, An efcient connection be-
tween grid and wind farm by means an Synchronous AFE, in Proc.
SPEEDAM Symp., Taormina, Italy, 2006, pp. 12111216.
[7] M. Karimi-Ghartemani and M. R. Iravani, A method for synchroniza-
tion of power electronic converters in polluted and variable-frequency
environments, IEEE Trans. Power Syst., vol. 19, no. 3, pp. 12631270,
Aug. 2004.
[8] R. M. Santos Filho, P. F. Seixas, P. C. Cortizo, L. A. B. Torres, and
A. F. Souza, Comparison of three single-phase PLL algorithms for UPS
applications, IEEE Trans. Ind. Electron., vol. 55, no. 8, pp. 29232932,
Aug. 2008.
LICCARDO et al.: ROBUST AND FAST THREE-PHASE PLL TRACKING SYSTEM 231
[9] M. A. Perez, J. R. Espinoza, L. A. Moran, M. A. Torres, and E. A. Araya,
A robust phase-locked loop algorithm to synchronize static-power con-
verters with polluted AC systems, IEEE Trans. Ind. Electron., vol. 55,
no. 5, pp. 21852192, May 2008.
[10] A. M. Salamah, S. J. Finney, and B. W. Williams, Three-phase phase-
lock loop for distorted utilities, IET Electr. Power Appl., vol. 1, no. 6,
pp. 937945, Nov. 2007.
[11] V. Kaura and V. Blasko, Operation of a phase locked loop system under
distorted utility conditions, IEEE Trans. Ind. Appl., vol. 33, no. 1, pp. 58
63, Jan./Feb. 1997.
[12] A. V. Timbus, M. Liserre, F. Blaabjerg, R. Teodorescu, and P. Rodriguez,
PLL algorithm for power generation systems robust to grid faults, in
Proc. IEEE Power Electron. Spec. Conf., 2006, pp. 13601366.
[13] J. M. Espi Huerta, J. Castello, J. R. Fischer, and R. Garcia-Gil, A syn-
chronous reference frame robust predictive current control for three-phase
grid-connected invert, IEEE Trans. Ind. Electron., vol. 57, no. 3, pp. 954
962, Mar. 2010.
[14] H. Song and K. Nam, Instantaneous phase-angle estimation algo-
rithm under unbalanced voltage-sag conditions, Proc. Inst. Elect. Eng.,
vol. 147, no. 6, pp. 409415, Nov. 2000.
[15] D. Yazdani, A. Bakhshai, G. Joos, and M. Mojiri, A nonlinear adaptive
synchronization technique for grid-connected distributed energy sources,
IEEE Trans. Power Electron., vol. 23, no. 4, pp. 21812186, Jul. 2008.
[16] D. Yazdani, M. Mojiri, A. Bakhshai, and G. Joos, A fast and accurate
synchronization technique for extraction of symmetrical components,
IEEE Trans. Power Electron., vol. 24, no. 3, pp. 674684, Mar. 2009.
[17] D. Jovcic, Phase locked loop system for FACTS, IEEE Trans. Power
Syst., vol. 18, no. 3, pp. 11161124, Aug. 2003.
[18] S. Shinnaka, A robust single-phase PLL system with stable and
fast tracking, IEEE Trans. Ind. Appl., vol. 44, no. 2, pp. 624633,
Mar./Apr. 2008.
[19] P. Rodriguez, J. Pou, J. Bergas, J. I. Candela, R. P. Burgos, and
D. Boroyevich, Decoupled double synchronous reference frame PLL for
power converters control, IEEE Trans. Power Electron., vol. 22, no. 2,
pp. 584592, Mar. 2007.
[20] G.-C. Hsieh and J. C. Hung, Phase-locked loop techniques. A survey,
IEEE Trans. Ind. Electron., vol. 43, no. 6, pp. 609615, Dec. 1996.
[21] M. Karimi-Ghartemani and M. R. Iravani, A new phase-locked loop
(PLL) system, in Proc. 44th IEEE MWSCAS, 2001, vol. 2, pp. 421424.
[22] D. R. Costa, L. G. B. Rolim, and M. Aredes, Analysis and software
implementation of a robust synchronism circuit-PLL circuit, in Proc.
IEEE Int. Symp. Ind. Electron., 2003, vol. 1, pp. 292297.
[23] L. G. B. Rolim, D. R. da Costa, and M. Aredes, Analysis and soft-
ware implementation of a robust synchronizing PLL circuit based on the
pq theory, IEEE Trans. Ind. Electron., vol. 53, no. 6, pp. 19191926,
Dec. 2006.
[24] H. Akagi, Y. Kanazawa, and A. Nabae, Generalized theory of the in-
stantaneous reactive power in three-phase circuits, in Proc. IPEC, 1983,
pp. 13751386.
[25] H. Akagi, Y. Kanazawa, and A. Nabae, Instantaneous reactive power
compensator comprising switching devices without energy storage com-
ponents, IEEE Trans. Ind. Appl., vol. IA-20, no. 3, pp. 625630,
May/Jun. 1984.
[26] F. Liccardo, P. Marino, C. Schiano, and N. Visciano, A new robust
phase tracking system for asymmetrical and distorted three phase net-
works, in Proc. 11th Int. Conf. Harmon. Quality Power, Sep. 1215,
2004, pp. 525530.
Felice Liccardo was born in Naples, Italy, on May 8,
1975. He received the M.Sc. degree in computer
science engineering from the University of Naples
Federico II, Naples, in 2001 and the Ph.D. degree
in electrical energy conversion from the Second Uni-
versity of Naples, Aversa, Italy, in 2005.
He is currently with the Second University of
Naples. His research interests include power elec-
tronic converters for power quality improvement.
Pompeo Marino was born in Frosinone, Italy, on
April 8, 1948. He received the M.Sc. degree in elec-
tronics engineering from the University of Naples
Federico II, Naples, Italy, in 1973.
He is a Professor in industrial electronics and
electrical drives with the Dipartimento di Ingegne-
ria dellInformazione, Second University of Naples,
Aversa, Italy. He is engaged in research works on
electrical power system reliability and harmonic
analysis. His interests include power converter de-
sign, ac and dc drives, and motion control.
Giuliano Raimondo was born in Naples, Italy, on
January 23, 1983. He received the B.Sc. and M.Sc.
degrees in electronics engineering from the Second
University of Naples, Aversa, Italy, in 2005 and
2008, respectively, where he is currently working to-
ward the Ph.D. degree and in the Laboratoire Plasma
et Conversion dEnergie, University of Toulouse,
Toulouse, France.
His research interests include digital control and
power electronic converters for power quality im-
provement in railway networks.