Tms 320 C 44

TMS320C44 DIGITAL SIGNAL PROCESSOR
SPRS031B AUGUST 1994 REVISED DECEMBER 1995
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Highest Performance Floating-Point Digital Signal Processor (DSP) TMS320C44-60: 33-ns Instruction Cycle Time, 330 MOPS, 60 MFLOPS, 30 MIPS, 336M Bytes / s TMS320C44-50: 40-ns Instruction Cycle Time Four Communication Ports Six-Channel Direct Memory Address (DMA) Coprocessor Single-Cycle Conversion to and From IEEE-754 Floating-Point Format Single Cycle, 1/x, 1 / x Source-Code Compatible With 320C3x and 320C4x Single-Cycle 40-Bit Floating-Point, 32-Bit Integer Multipliers Twelve 40-Bit Registers, Eight Auxiliary Registers, 14 Control Registers, and Two Timers IEEE-1149.1 (JTAG) Boundary-Scan Compatible Two Identical External Data and Address Buses Supporting Shared Memory Systems and High Data-Rate, Single-Cycle Transfers High Port-Data Rate of 120M Bytes / s (TMS320C44-60) (Each Bus) 128M-Byte Program / Data / Peripheral Address Space Memory-Access Request for Fast, Intelligent Bus Arbitration Separate Address-Bus, Data-Bus, and Control-Enable Pins Four Sets of Memory-Control Signals Support Different Speed Memories in Hardware 304-Pin Plastic Quad Flatpack (PDB Suffix) Fabricated Using 0.72-m Enhanced Performance Implanted CMOS (EPIC) Technology by Texas Instruments (TI) Separate Internal Program-, Data-, and DMA-Coprocessor Buses for Support of Massive Concurrent I / O of Program and Data, Thereby Maximizing Sustained CPU Performance
PDB PACKAGE ( TOP VIEW )

304 1 229 228
76 77 152
153
See Pin Assignments table and Pin Functions table for location and description of all pins.
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IDLE2 Clock-Stop Power-Down Mode Communication-Port-Direction Pin On-Chip Program Cache and Dual-Access/ Single-Cycle RAM for Increased Memory-Access Performance 512-Byte Instruction Cache 8K Bytes of Single-Cycle Dual-Access Program or Data RAM ROM-Based Boot Loader Supports Program Bootup Using 8-, 16-, or 32-Bit Memories or One of the Communication Ports Software-Communication-Port Reset NMI With Bus-Grant Feature
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. IEEE Standard 1149.11990 Standard Test-Access Port and Boundary-Scan Architecture EPIC and TI are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 1995, Texas Instruments Incorporated
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443

block diagram
Cache (512 bytes) 32 PDATA Bus D31 D0 A23 A0 DE AE STAT3 STAT0 LOCK STRB0, STRB1 R / W0, R / W1 PAGE0, PAGE1 RDY0, RDY1 CE0, CE1 PADDR Bus DDATA Bus MUX DADDR 1 Bus DADDR 2 Bus DMADATA Bus DMAADDR Bus 32 32 32 32 32 Continued on next page MUX CPU1 CPU2 REG 1 REG1 R E G 1 REG2 REG2 REG1 40 Multiplier 40 Extended Precision Registers ( R0 R11)
DISP, IR0, IR1 ARAU0 BK ARAU1
RAM Block 0 (4K bytes) 32 32
RAM Block 1 (4K bytes) 32 32
ROM Block (reserved) 32 32
32
IR PC X1 X2 / CLKIN ROMEN RESET RESETLOC0, RESETLOC1 CPU1 NMI IIOF(3 0) IACK H1 H3 CVSS DVDD DVSS IVSS DVDD DVDD VDDL VSSL VSUBS 32 32 32 32 32 32 Other Registers (14) Auxiliary Registers (AR0 AR7) 40 40 32 Controller
40
40
40
32-Bit Barrel Shifter

ALU
40 40 40
32 32 32 32

block diagram (continued)
Continued from previous page
PDATA Bus PADDR Bus DDATA Bus DADDR 1 Bus DADDR 2 Bus DMADATA Bus DMAADDR Bus MUX
LD31 LD0 LA23 LA0 LDE LAE LSTAT3 LSTAT0 LLOCK LSTRB0, LSTRB1 LR / W0, LR / W1 LPAGE0, LPAGE1 LRDY0, LRDY1 LCE0, LCE1
MUX 32 32 COM Port 1 Input FIFO PAU Output FIFO Port-Control Registers COM Port 2 COM Port 4 Peripheral Address Bus COM Port 5 Input FIFO PAU Output FIFO Port-Control Registers Timer 0 Global-Control Register Time-Period Register Timer-Counter Register Timer 1 Global-Control Register Time-Period Register Timer-Counter Register Port Control Global Local CREQ5 CACK5 CSTRB5 CRDY5 C5D7 C5D0 CDIR5 CREQ1 CACK1 CSTRB1 CRDY1 C1D7 C1D0 CDIR1 Four Communication Ports
DMA Coprocessor DMA Channel 0 DMA Channel 1 DMA Channel 2 DMA Channel 3 DMA Channel 4 DMA Channel 5 Peripheral Data Bus
Six DMA Channels
TCLK0
TCLK1
Communication ports 0 and 3 are not connected.

functions
This section lists signal descriptions for the 320C44 device: each signal, number of pins, operating mode(s) (that is, input, output, or high-impedance state as indicated by I, O, or Z, respectively ), and function. The signals are grouped according to function. Pin Functions
SIGNAL NAME NO. OF PINS TYPE DESCRIPTION
GLOBAL-BUS EXTERNAL INTERFACE (73 pins) D31 D0 DE A23 A0 AE STAT3 STAT0 LOCK STRB0 R / W0 PAGE0 RDY0 CE0 STRB1 R / W1 PAGE1 RDY1 CE1 LD31 LD0 LDE LA23 LA0 LAE LSTAT3 LSTAT0 LLOCK LSTRB0 LR / W0 LPAGE0 LRDY0 LCE0 LSTRB1 LR / W1 LPAGE1 LRDY1 32 1 24 1 4 1 1 1 1 1 1 1 1 1 1 1 32 1 24 1 4 1 1 1 1 1 1 1 1 1 1 I/O/Z I O/Z I O O O/Z O/Z O/Z I I O/Z O/Z O/Z I I I/O/Z I O/Z I O O O/Z O/Z O/Z I I O/Z O/Z O/Z I 32-bit data port of the global-bus external interface Data-bus-enable signal for the global-bus external interface 24-bit address port of the global-bus external interface Address-bus-enable signal for the global-bus external interface Status signals for the global-bus external interface Lock signal for the global-bus external interface Access strobe 0 for the global-bus external interface Read / write signal for STRB0 accesses Page signal for STRB0 accesses Ready signal for STRB0 accesses Control enable for the STRB0, PAGE0, and R / W0 signals Access strobe 1 for the global-bus external interface Read / write signal for STRB1 accesses Page signal for STRB1 accesses Ready signal for STRB1 accesses Control enable for the STRB1, PAGE1, and R / W1 signals LOCAL-BUS EXTERNAL INTERFACE (73 pins) 32-bit data port of the local-bus external interface Data-bus-enable signal for the local-bus external interface 24-bit address port of the local-bus external interface Address-bus-enable signal for the local-bus external interface Status signals for the local-bus external interface Lock signal for the local-bus external interface Access strobe 0 for the local-bus external interface Read / write signal for LSTRB0 accesses Page signal for LSTRB0 accesses Ready signal for LSTRB0 accesses Control enable for the LSTRB0, LPAGE0, and LR / W0 signals Access strobe 1 for the local-bus external interface Read / write signal for LSTRB1 accesses Page signal for LSTRB1 accesses Ready signal for LSTRB1 accesses
LCE1 1 I Control enable for the LSTRB1, LPAGE1, and LR / W1 signals I = input, O = output, Z = high impedance The effective address range is defined by the local /global STRB ACTIVE bits in the memory interface-control registers.

Pin Functions (Continued)

SIGNAL NAME NO. OF PINS TYPE DESCRIPTION
COMMUNICATION PORT 1 INTERFACE (13 pins) C1D7 C1D0 CREQ1 CACK1 CSTRB1 CRDY1 CDIR1 C2D7 C2D0 CREQ2 CACK2 CSTRB2 CRDY2 CDIR2 C4D7 C4D0 CREQ4 CACK4 CSTRB4 CRDY4 CDIR4 C5D7 C5D0 CREQ5 CACK5 CSTRB5 CRDY5 CDIR5 IIOF3 IIOF0 NMI IACK RESET RESETLOC1 RESETLOC0 ROMEN TCLK0 8 1 1 1 1 1 8 1 1 1 1 1 8 1 1 1 1 1 8 1 1 1 1 1 4 1 1 1 2 1 1 I/O I/O I/O I/O I/O O I/O I/O I/O I/O I/O O I/O I/O I/O I/O I/O O I/O I/O I/O I/O I/O O I/O I O I I I I/O Communication port 1 data bus Communication port 1 token-request signal Communication port 1 token-request-acknowledge signal Communication port 1 data-strobe signal Communication port 1 data-ready signal Communication port 1 direction signal Communication port 2 data bus Communication port 2 token-request signal Communication port 2 token-request-acknowledge signal Communication port 2 data-strobe signal Communication port 2 data-ready signal Communication port 2 direction signal Communication port 4 data bus Communication port 4 token-request signal Communication port 4 token-request-acknowledge signal Communication port 4 data-strobe signal Communication port 4 data-ready signal Communication port 4 direction signal Communication port 5 data bus Communication port 5 token-request signal Communication port 5 token-request-acknowledge signal Communication port 5 data-strobe signal Communication port 5 data-ready signal Communication port 5 direction signal Interrupt and I / O flags Nonmaskable interrupt. NMI is sensitive to a low-going edge. Interrupt acknowledge Reset signal Reset-vector location On-chip ROM enable (0 = disable, 1 = enable) Timer 0 Timer 1
COMMUNICATION PORT 2 INTERFACE (13 pins)
INTERRUPTS, I / O FLAGS, RESET, TIMER (12 pins)
TCLK1 1 I/O I = input, O = output, Z = high impedance

Pin Functions (Continued)

SIGNAL NAME NO. OF PINS TYPE CLOCK (4 pins) X1 X2 / CLKIN H1 H3 CVSS DVSS IVSS DVDD VSUBS VDDL VSSL TCK TDI TDO TMS TRST EMU0 1 1 1 1 17 17 6 22 1 4 4 1 1 1 1 1 1 O I O O I I I I I I I I I O/Z I I I/O Crystal Crystal /oscillator H1 clock H3 clock POWER (71 pins) Ground Ground Ground 5-VDC supply Substrate (tie to ground) 5-VDC supply Ground EMULATION (7 pins) IEEE 1149.1 test port clock IEEE 1149.1 test port data in IEEE 1149.1 test port data out IEEE 1149.1 test port mode select IEEE 1149.1 test port reset Emulation pin 0 Emulation pin 1 DESCRIPTION
EMU1 1 I/O I = input, O = output, Z = high impedance

PDB Package Pin Assignments Alphabetical Listing

PIN NAME A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 AE C1D0 C1D1 C1D2 C1D3 C1D4 C1D5 C1D6 C1D7 C2D0 C2D1 C2D2 C2D3 C2D4 C2D5 C2D6 NO. 149 150 151 152 154 155 156 157 158 159 160 162 165 166 167 168 169 170 171 174 175 176 177 178 57 269 271 274 276 278 280 283 286 26 27 29 30 31 32 33 NAME C2D7 C4D0 C4D1 C4D2 C4D3 C4D4 C4D5 C4D6 C4D7 C5D0 C5D1 C5D2 C5D3 C5D4 C5D5 C5D6 C5D7 CACK1 CACK2 CACK4 CACK5 CDIR1 CDIR2 CDIR4 CDIR5 CE0 CE1 CRDY1 CRDY2 CRDY4 CRDY5 CREQ1 CREQ2 CREQ4 CREQ5 CSTRB1 CSTRB2 CSTRB4 CSTRB5 CVSS PIN NO. 34 87 88 90 92 94 97 99 100 37 39 41 42 45 46 47 48 13 21 73 50 19 18 16 15 93 101 8 23 85 53 11 20 71 49 14 22 84 52 148 NAME CVSS CVSS CVSS CVSS CVSS CVSS CVSS CVSS CVSS CVSS CVSS CVSS CVSS CVSS CVSS CVSS D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 PIN NO. 134 117 102 78 62 44 25 7 282 262 247 230 218 202 182 164 104 105 106 107 108 110 111 112 113 114 115 118 120 122 123 125 127 128 129 130 131 132 135 136 NAME D24 D25 D26 D27 D28 D29 D30 D31 DE DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS PIN NO. 137 138 140 141 142 143 144 145 89 139 124 109 96 83 67 51 40 28 17 302 288 272 256 244 236 223 207 188 172 161 153 147 133 116 103 79 63 43 24 6

PDB Package Pin Assignments Alphabetical Listing (Continued)

PIN NAME DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS EMU0 EMU1 H1 H3 IACK IIOF0 IIOF1 IIOF2 IIOF3 IVSS IVSS IVSS IVSS IVSS IVSS LA0 LA1 LA2 LA3 LA4 LA5 LA6 LA7 LA8 LA9 LA10 LA11 LA12 LA13 LA14 LA15 LA16 NO. 281 261 246 231 217 201 179 163 75 74 266 268 270 10 9 5 4 126 65 35 2 285 209 232 233 234 235 237 238 239 240 241 242 243 245 248 249 250 251 252 NAME LA17 LA18 LA19 LA20 LA21 LA22 LA23 LAE LCE0 LCE1 LD0 LD1 LD2 LD3 LD4 LD5 LD6 LD7 LD8 LD9 LD10 LD11 LD12 LD13 LD14 LD15 LD16 LD17 LD18 LD19 LD20 LD21 LD22 LD23 LD24 LD25 LD26 LD27 LD28 LD29 PIN NO. 253 254 255 257 258 259 260 287 297 292 183 184 185 186 187 192 194 195 196 197 200 203 204 205 206 208 210 211 212 213 215 216 219 220 221 222 224 225 226 227 NAME LD30 LD31 LDE LLOCK LOCK LPAGE0 LPAGE1 LRDY0 LRDY1 LR / W0 LR / W1 LSTAT0 LSTAT1 LSTAT2 LSTAT3 LSTRB0 LSTRB1 NC NC NC NC NC NC NC NC NC NC NC NC NMI PAGE0 PAGE1 RDY0 RDY1 RESET RESETLOC0 RESETLOC1 ROMEN R / W0 R / W1 PIN NO. 228 229 291 284 95 299 294 298 293 300 295 279 277 275 273 301 296 1 77 173 180 181 189 190 198 199 214 303 304 3 60 72 91 98 54 55 56 12 59 70 NAME STAT0 STAT1 STAT2 STAT3 STRB0 STRB1 TCK TCLK0 TCLK1 TDI TDO TMS TRST VDDL VDDL VDDL VDDL VSSL VSSL VSSL VSSL VSUBS X1 X2 / CLKIN PIN NO. 68 66 64 61 58 69 86 290 289 76 80 82 81 38 121 191 267 36 119 193 265 146 264 263

PDB Package Pin Assignments Numerical Listing

PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 NAME NC IVSS NMI IIOF3 IIOF2 DVSS CVSS CRDY1 IIOF1 IIOF0 CREQ1 ROMEN CACK1 CSTRB1 CDIR5 CDIR4 DVDD CDIR2 CDIR1 CREQ2 CACK2 CSTRB2 CRDY2 DVSS CVSS C2D0 C2D1 DVDD C2D2 C2D3 C2D4 C2D5 C2D6 C2D7 IVSS VSSL C5D0 VDDL C5D1 DVDD NO. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 PIN NAME C5D2 C5D3 DVSS CVSS C5D4 C5D5 C5D6 C5D7 CREQ5 CACK5 DVDD CSTRB5 CRDY5 RESET RESETLOC0 RESETLOC1 AE STRB0 R / W0 PAGE0 STAT3 CVSS DVSS STAT2 IVSS STAT1 DVDD STAT0 STRB1 R / W1 CREQ4 PAGE1 CACK4 EMU1 EMU0 TDI NC CVSS DVSS TDO NO. 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 PIN NAME TRST TMS DVDD CSTRB4 CRDY4 TCK C4D0 C4D1 DE C4D2 RDY0 C4D3 CE0 C4D4 LOCK DVDD C4D5 RDY1 C4D6 C4D7 CE1 CVSS DVSS D0 D1 D2 D3 D4 DVDD D5 D6 D7 D8 D9 D10 DVSS CVSS D11 VSSL D12 NO. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 PIN NAME VDDL D13 D14 DVDD D15 IVSS D16 D17 D18 D19 D20 D21 DVSS CVSS D22 D23 D24 D25 DVDD D26 D27 D28 D29 D30 D31 VSUBS DVSS CVSS A0 A1 A2 A3 DVDD A4 A5 A6 A7 A8 A9 A10

PDB Package Pin Assignments Numerical Listing (Continued)

PIN NO. 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 NAME DVDD A11 DVSS CVSS A12 A13 A14 A15 A16 A17 A18 DVDD NC A19 A20 A21 A22 A23 DVSS NC NC CVSS LD0 LD1 LD2 LD3 LD4 DVDD NC NC VDDL LD5 VSSL LD6 LD7 LD8 LD9 NC NC LD10 NO. 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 PIN NAME DVSS CVSS LD11 LD12 LD13 LD14 DVDD LD15 IVSS LD16 LD17 LD18 LD19 NC LD20 LD21 DVSS CVSS LD22 LD23 LD24 LD25 DVDD LD26 LD27 LD28 LD29 LD30 LD31 CVSS DVSS LA0 LA1 LA2 LA3 DVDD LA4 LA5 LA6 LA7 NO. 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 PIN NAME LA8 LA9 LA10 DVDD LA11 DVSS CVSS LA12 LA13 LA14 LA15 LA16 LA17 LA18 LA19 DVDD LA20 LA21 LA22 LA23 DVSS CVSS X2 / CLKIN X1 VSSL H1 VDDL H3 C1D0 IACK C1D1 DVDD LSTAT3 C1D2 LSTAT2 C1D3 LSTAT1 C1D4 LSTAT0 C1D5 NO. 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 PIN NAME DVSS CVSS C1D6 LLOCK IVSS C1D7 LAE DVDD TCLK1 TCLK0 LDE LCE1 LRDY1 LPAGE1 LR / W1 LSTRB1 LCE0 LRDY0 LPAGE0 LR / W0 LSTRB0 DVDD NC NC
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memory map
Figure 1 shows the memory map for the 320C44. Refer to the TMS320C4x Users Guide (literature number SPRU063B) for a detailed description of this memory mapping.
Structure Depends Upon Romen Bit 00000 0000h 1M Accessible Local Bus (External) 00000 0FFFh 00000 1000h Reserved 0000F FFFFh 00010 0000h 00010 00FFh 00010 0100h Reserved 0001F FFFFh 00020 0000h Reserved 1M 1K RAM BLK 0 (Internal) 1K RAM BLK 1 (Internal) Local Bus (External) 000FF FFFFh 0100 0000h 2 G 16 M Local Bus (alias region, see Figure 2) 7FFF FFFFh 8000 0000h 16 M Global Bus (External) 80FF FFFh 8100 0000 Global Bus (External) Local Bus (alias region, see Figure 2) 0002F F7FFh 0002F F800h 0002F FBFFh 0002F FC00h 0002F FFFFh 00030 0000h Structure Identical 13 M Local Bus (External) Reserved Reserved
Boot-Loader ROM (Internal)
Peripherals (Internal) 1M
Peripherals (Internal)
1K RAM BLK 0 (Internal) 1K RAM BLK 1 (Internal)
2 G 16 M
Global Bus (alias region, see Figure 2)
Global Bus (alias region, see Figure 2)
FFFF FFFFh (a) INTERNAL ROM DISABLED (ROMEN = 0) Microprocessor Mode (b) INTERNAL ROM ENABLED (ROMEN = 1) Microcomputer Mode
Figure 1. Memory Map for the 320C44
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description
The TMS320C44 DSP is a 32-bit, floating-point processor manufactured in 0.72-m double-level-metal CMOS technology. The TMS320C44 is part of the TMS320C4x generation of DSPs from Texas Instruments. The on-chip parallel-processing capabilities of the C44 make the immense floating-point performance required by many applications achievable.
operation
The 320C44 has four on-chip communication ports for processor-to-processor communication with no external hardware and simple communication software. This allows connectivity with no external-glue logic. The communication ports remove input / output bottlenecks, and the independent smart 6-channel DMA coprocessor is able to handle the CPU input / output burden. To fit the 320C40 into a 304-pin PQFP package ( thermally enhanced plastic quad flatpack), two communication ports are removed and the external local and global address buses are reduced to 24 address lines each. In this case, both the bond pads and driver circuits are removed, decreasing die size and power consumption. Otherwise, functionality remains the same as the rest of the 320C4x family. The communication-port token and data-strobe control lines are internally connected to avoid spurious data, boot-up, and power consumption problems.
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memory aliasing The 320C44 offers global and local addresses of A0 A23 and LA0 LA23, giving an external address reach of (2 buses) (2 24) = 225 words. Since the internal address span of the 320C44 is 232 words, reading or writing to memory outside of the base-address region causes memory aliasing. Figure 2 shows how the memory pages overlap each other.
Local Bus 0x0000 0000 Base-Address Region 0x00FF FFFF 0x0100 0000 External Alias 1 0x01FF FFFF 0x0200 0000 External Alias 2 0x02FF FFFF 0x82FF FFFF 0x81FF FFFF 0x8200 0000 External Alias 2 0x80FF FFFF 0x8100 0000 External Alias 1 0x8000 0000 Base-Address Region Global Bus
0x7F00 0000 External Alias n 0x7FFFFFFF
0xFF00 0000 External Alias n 0xFFFFFFFF
Figure 2. Memory Alias central processing unit The 320C44 CPU is configured for high-speed internal parallelism for the highest sustained performance. The key features of the CPU are:
Eight operations / cycle: 40- / 32-bit floating-point / integer multiply 40- / 32-bit floating-point / integer ALU operation Two data accesses Two address-register updates
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Floating-point conversion Divide and square-root support C3x and C4x assembly-language compatibility Byte and halfword accessibility
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DMA coprocessor The DMA coprocessor allows concurrent I / O and CPU processing for the highest sustained CPU performance. The key features of the DMA coprocessor are:
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Link pointers to allow DMA channels to autoinitialize without CPU intervention Parallel CPU operation and DMA transfers Six DMA channels to support memory-to-memory data transfers Split-mode operation which doubles the available channels to twelve when data transfers to and from a communication port are required
communication ports The 320C44 contains four identical high-speed communication ports, each of which provides a bidirectional-communication interface to other C4x devices and external peripherals. The key features of the communication ports are:
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Direct interprocessor communication and processor I / O 20M-byte / s bidirectional interface on each communication port for high-speed multiprocessor interface Port direction pin (CDIR) to ease interfacing Separate input and output 8-word-deep FIFO buffers for processor-to-processor communication and I / O Automatic arbitration and handshaking for direct processor-to-processor connection
communication-port direction pin A port-direction pin (CDIR1, CDIR2, CDIR4, CDIR5) is available for each C44 communication port. When the communication port is in the output mode, CDIRx is driven low. When the communication port is in the input mode, CDIRx is driven high. The truth table for two 320C44 devices is shown in Table 1. Communication port 1 of CPUA is connected to communication port 4 of CPUB. Table 1. Truth Table for Two 320C44 Devices
CDIR1 0 0 1 1 CDIR4 0 1 0 1 Token error CPUA is configured to transmit to CPUB. CPUB is configured to transmit to CPUA . Token exchange overlap, if > 1H then token error DESCRIPTION
communication-port-software reset The input and output FIFO levels for a communication port can be flushed by writing at least two back-to-back values to its communication-port software-reset address as specified in Table 2. This software reset flushes any word or byte already present in the FIFOs, but it does not affect the status of the communication-port pins. Table 2. Communication-Port Software-Reset Address
COMMUNICATION PORT 1 2 4 5 SOFTWARE-RESET ADDRESS 0x0100053 0x0100063 0x0100083 0x0100093
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communication-port-software reset (continued) When used in conjunction with the communication-port direction pins and NMI bus-grant, an effective method of error detection and correction can be achieved. A subroutine showing how to reset communication port 1 is given in Figure 3.
; -; ; RESET1:Flushes FIFOs data for communication port 1; ; -; RESET1 push AR0 ; Save registers push R0 ; push RC ; ldhi 010h,AR0 ; Set AR0 to base address of COM 1 or 050h,AR0 ; FLUSH: rpts 1 ; Flush FIFO data with back-to-back write sti R0,*+AR0(3) ; rpts 10 ; Wait nop ; ldi *+AR0(0),R0 ; Check for new data from other port and 01FE0h,R0 ; bnz FLUSH ; pop RC ; Restore registers pop R0 ; pop AR0 ; rets ; Return
Figure 3. Example of Communication-Port-Software Reset NMI with bus-grant feature The 320C44 devices have a software-configurable feature that allows forcing the internal-peripheral bus ready when the NMI signal is asserted. The NMI bus-grant feature is enabled when bits 19 and 18 of the status register (ST) are set to 10b. When enabled, a peripheral bus-grant signal is generated on the falling edge of NMI. If NMI is asserted and this feature is not enabled, the CPU stalls on access to the peripheral bus if it is not ready. A stall condition occurs when writing to a full output FIFO or reading an empty input FIFO. This feature is useful in correcting communication-port errors when used in conjunction with the communication-port software-reset feature.
IDLE2 clock-stop power-down mode The 320C44 has a clock-stop mode, or power-down mode (IDLE2) to achieve extremely low power consumption. When an IDLE2 instruction is executed, the clocks are halted with H1 held high. ( Exiting IDLE2 requires asserting one of the IIOF3 IIOF0 pins configured as an external interrupt.) A macro showing how to generate the IDLE2 opcode is given in Figure 4. During this power-down mode:
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No instructions are executed. The CPU, peripherals, and internal memory retain their previous state. The external-bus outputs are idle. The address lines remain in their previous state; the data lines are in the high-impedance state; and the output-control signals are inactive.
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IDLE2 clock-stop power-down mode (continued)

; --; ; IDLE2: Macro to generate idle2 opcode ; ; -; IDLE2 .macro .word 06000001h .endm
Figure 4. Example Software Subroutine Using IDLE2 IDLE2 is exited when one of the five external interrupts (NMI and IIOF3 IIOF0) is asserted low for at least four input clocks (two H1 cycles). The clocks then start after a delay of two input clocks (one H1 cycle). The clocks can start in the opposite phase; that is, H1 can be high when H3 was high before the clocks were stopped. However, the H1 and H3 clocks remain 180 degrees out of phase with each other. During IDLE2 operation, an external interrupt can be recognized and serviced by the CPU if it is enabled before entering IDLE2 and asserted for at least two H1 cycles. For the processor to recognize only one interrupt, the interrupt pin must be configured for edge-trigger mode or asserted less than three cycles in level-trigger mode. Any external interrupt pin can wake up the device from IDLE2, but for the CPU to recognize that interrupt, it must also be enabled. If an interrupt is recognized and executed by the CPU, the instruction following the IDLE2 instruction is not executed until after a return opcode is executed. When the device is in emulation mode, the CPU executes an IDLE2 instruction as if it were an IDLE instruction. The clocks continue to run for correct operation of the emulator. boot-loader mode selection Table 3. Boot-Loader Mode Selection Using Pins IIOF3 IIOF0
EXTERNAL PIN IIOF3 1 1 1 0 0 0 0 1 NOTES: 1. 2. 3. 4. IIOF2 1 0 0 1 1 0 0 1 IIOF1 0 1 0 1 0 1 0 1 IIOF0 1 1 1 1 1 1 1 1 SOURCE PROGRAM LOCATION Load source program from address 0030 0000h Load source program from address 4000 0000h (see Note 1) Load source program from address 80 0000h Load source program from address 8000 0000h (see Note 2) Load source program from address 8040 0000h (see Note 3) Load source program from address 8080 0000h (see Note 4) Reserved (boot-loader program terminates) Load source program from communication port
This selection cause the C44 to drive 0 in the 24 external local address pins and activates the LSTRB0 signal. This selection cause the C44 to drive 0 in the 24 external global address pins ando activates the STRB0 signal. This selection cause the C44 to drive 0x40 0000 in the 24 external global address pins and activates the STRB0 signal. This selection cause the C44 to drive 0x80 0000 in the 24 external global address pins and to activate the STRB0 signal.
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development tools A key aspect to a parallel-processing implementation is the development tools available. The C44 is supported by a host of parallel-processing tools for developing and simulating code easily and for debugging parallel-processing systems. The code-generation tools include:
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An optimizing ANSI C compiler with a runtime-support library that supports use of communication ports and DMA Third party support for C, C++, and Ada compilers Several operating systems available for parallel-processing support as well as DMA and communication-port drivers Assembler and linker with support for mapping program and data to parallel processors
The simulation tools include a TI software-simulator with a high-level-language debugger interface for simulating a single processor. The hardware development and verification tools consist of the XDS510 ( parallel-processor in-circuit emulator and high-level-language debugger ).
silicon revision identification

DSP TMS320C44PDB EAXXX YYYYY 1991 TI TAIWAN Device Type Revision Number and Package Data Code E XXXXX : Silicon rev 1.X EA XXXXX : Silicon rev 2.X Lot Number (May or may not exist)
17

absolute maximum ratings over specified temperature range (unless otherwise noted)
Supply voltage range, VDD (see Note 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to 7 V Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to 7 V Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to 7 V Operating case temperature range, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 85C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55C to 150C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 5: All voltage values are with respect to VSS.
recommended operating conditions

MIN VDD VIH VIL IOH Supply voltage (DDVDD, etc.) X2 / CLKIN High-level input voltage Low-level input voltage High-level output current 0 CSTRB and CRDY pins All other pins 4.75 2.6 2.4 2 0.3 TYP 5 MAX 5.25 VDD + 0.3 VDD + 0.3 VDD + 0.3 0.8 300 2 85 V A mA C UNIT V V
IOL Low-level output current TC Operating case temperature All typical values are at VDD = 5 V, TA (air temperature)= 25C. This parameter is characterized but not tested.
electrical characteristics over recommended ranges of supply voltage and operating case temperature (unless otherwise noted)
PARAMETER VOH VOL IZ High-level output voltage Low-level output voltage High-impedance current X2 / CLKIN only II Input current Inputs with internal pullups (see Note 6) All others ICC CI Supply current y Input capacitance TA = 25 C, VDD = MAX, fx = MAX (see Note 7) 320C44-40 320C44-50 320C44-60 VI = VSS to VDD TEST CONDITIONS VDD = MIN, VDD = MIN, VDD = MAX IOH = MAX IOL = MAX 20 30 400 10 350 350 MIN 2.4 TYP# 3 0.3 0.6 20 30 20 10 850 mA 950 15|| pF A MAX UNIT V V A
Co Output capacitance 15|| pF For conditions shown as MIN / MAX, use the appropriate value specified under recommended operating conditions. # All typical values are at VDD = 3.3 V, TA (air temperature) = 25C. || This parameter is specified by design but not tested. NOTES: 6. Pins with internal pullup devices: TDI, TCK, TMS. Pin with internal pulldown device: TRST. 7. fx is the input clock frequency. The maximum value (max) for the 320C44-40, 320C44-50, and 320C44-60 is 40, 50 and 60 MHz, respectively.
18

PARAMETER MEASUREMENT INFORMATION

IOL
Tester Pin Electronics
VLoad CT
Output Under Test
IOH
Where: IOL = = IOH VLOAD = = CT
2 mA (all outputs) 300 A (all outputs) 2.15 V 80 pF typical load-circuit capacitance
Figure 5. Test Load Circuit
signal transition levels

TTL-level outputs are driven to a minimum logic-high level of 2.4 V and to a maximum logic-low level of 0.6 V. Output transition times are specified as follows:
D D
For a low-to-high transition, the level at which the output is said to be no longer low is 1 V and the level at which the output is said to be high is 2 V. For a high-to-low transition on a TTL-compatible output signal, the level at which the output is said to be no longer high is 2 V and the level at which the output is said to be low is 1 V.
2.4 V 2V 1V 0.6 V
Figure 6. TTL-Level Outputs Transition times for TTL-compatible inputs are specified as follows:
D D
For a low-to-high transition on an input signal, the level at which the input is said to be no longer low is 0.92 V (10%) and the level at which the input is said to be high is 1.88 V (90%). For a high-to-low transition on an input signal, the level at which the input is said to be no longer high is 1.88 V (90%) and the level at which the input is said to be low is 0.92 V (10%).
2V 1.88 V (90%) 0.92 V (10%) 0.8 V
Figure 7. TTL-Level Inputs
19

PARAMETER MEASUREMENT INFORMATION timing parameter symbology

Timing parameter symbols used herein were created in accordance with JEDEC Standard 100-A. In order to shorten the symbols, pin names that have both global and local applications are generally represented with (L) immediately preceding the basic signal name (for example, (L)RDY represents both the global term RDY and local term LRDY). Other pin names and related terminology have been abbreviated as follows, unless otherwise noted:
A AE ASYNCH BYTE CA CD CDIR CE CI COMM CONTROL CRQ CRDY CS D DE H (L)A23 (L)A0 or (L)Ax (L)AE Asynchronous reset signals in the high-impedance state Byte transfer CACK(1,2,4,5) or CACKx C(1,2,4,5)D7 C(1,2,4,5)D0 or CxDx CDIR(1,2,4,5) or CDIRx (L)CE0, (L)CE1, or (L)CEx CLKIN Asynchronous reset signals Control signals CREQ(1,2,4,5) or CREQx CRDY(1,2,4,5) or CRDYx CSTRB(1,2,4,5) or CSTRBx (L)D31 (L)D0 or (L)Dx (L)DE H1, H3 IACK IF IIOF LOCK P PAGE RDY RESET RW S ST TCK TCLK TDO TMS WORD IACK IIOF(3 0) or IIOFx IIOF(3 0) or IIOFx (L)LOCK tc(H) (L)PAGE0 and (L)PAGE1 or (L)PAGEx (L)RDY0, (L)RDY1, or (L)RDYx RESET (L)R / W0, (L)R / W1, or (L)R / Wx (L)STRB0, (L)STRB1, or (L)STRBx (L)STAT3 (L)STAT0 or (L)STATx TCK TCLK0, TCLK1, or TCLKx TDO TMS / TDI 32-bit word transfer
20

timing for X2/CLKIN, H1, H3 (see Figure 8 and Figure 9)

NO. NO 1 2 3 4 5 6 7 8 9 9.1 tf(CI) tw(CIL) tw(CIH) tr(CI) tc(CI) tf(H) tw(HL) tw(HH) tr(H) td(HL - HH) Fall time, CLKIN Pulse duration, CLKIN low, tc(CI) = MIN Pulse duration, CLKIN high, tc(CI) = MIN Rise time, CLKIN Cycle time, CLKIN Fall time, H1 and H3 Pulse duration, H1 and H3 low Pulse duration, H1 and H3 high Rise time, H1 and H3 Delay time from H1 low to H3 high or from H3 low to H1 high Cycle time, H1 and H3 1 40 tc(CI) 6 tc(CI) 6 20 7 7 5 242.5 3 tc(CI) + 6 tc(CI) + 6 4 4 485 1 33.3 tc(CI) 6 tc(CI) 6 16.67 TMS320C44- 50 MIN MAX 5 TMS320C44- 60 MIN 5 5 5 242.5 3 tc(CI) + 6 tc(CI) + 6 4 4 485 MAX 5 UNIT ns ns ns ns ns ns ns ns ns ns ns
10 tc(H) This value is specified by design but not tested. Maximum cycle time is not limited during IDLE2 operation.
5 4 1 X2 / CLKIN 3 2
Figure 8. X2 / CLKIN Timing
10 9 H1 8 9.1 7 9.1 H3 8 9 7 10 6 6
Figure 9. H1 and H3 Timings
21

memory-read-cycle and memory-write-cycle timing [(L)STRBx = 0] (see Note 8, Figure 10, and Figure 11)
NO. NO 1 2 3 4 5 6 7 8 8.1 9 10 11 12 td(H1L - SL) td(H1L - SH) td(H1H - RWL) td(H1L - A) tsu(D-H1L)R th(H1L-D)R tsu(RDY-H1L) th(H1L-RDY) td(H1L - ST) td(H1H-RWH)W tv(H1L-D)W th(H1H-D)W Delay time, H1 low to (L)STRBx low Delay time, H1 low to (L)STRBx high Delay time, H1 high to (L)R / Wx low Delay time, H1 low to (L)Ax valid Setup time, (L)Dx valid before H1 low (read) Hold time, (L)Dx after H1 low (read) Setup time, (L)RDYx valid before H1 low Hold time, (L)RDYx after H1 low Delay time, H1 low to (L)STAT3 (L)STAT0 valid Delay time, H1 high to (L)R / Wx high (write) Valid time, (L)Dx after H1 low (write) Hold time, (L)Dx after H1 high (write) 0 9 0 TMS320C44- 50 MIN 0 0 0 0 10 0 20 0 8 9 16 0 8 0 MAX 9 9 9 9 TMS320C44- 60 MIN 0 0 0 0 9 0 18 0 8 8 13 MAX 8 8 8 8 UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns
td(H1H - A) Delay time, H1 high to address valid on back-to-back write cycles This value is specified by design but not tested. If this setup time is not met, the read / write operation is not assured. NOTE 8: For consecutive reads, (L)R / Wx stays high and (L)STRBx stays low.
22

memory-read-cycle and memory-write-cycle timing [(L)STRBx = 0] (continued)

H3
H1 1 (L)STRBx 2
(L)R / Wx 4
5 3
(L)Ax 6 (L)Dx 8 (L)RDYx 8.1 (L)STATx 7
Figure 10. Memory-Read-Cycle Timing [(L)STRBx = 0]
23

memory-read-cycle and memory-write-cycle timing [(L)STRBx = 0] (continued)

H3
H1 1 (L)STRBx 3 (L)R / Wx 4 (L)Ax 10 (L)Dx 8 (L)RDYx 7 (L)STATx 11 12 9 2
Figure 11. Memory-Write-Cycle Timing [(L)STRBx = 0]
24

(L)DE-, (L)AE-, and (L)CEx-enable timing (see Figure 12)

NO. NO 1 2 3 4 5 6 7 8 9 td(DEH - DZ) td(DEL - DV) td(AEH - AZ) td(AEL - AV) td(CEH - RWZ) td(CEL - RWV) td(CEH - SZ) td(CEL - SV) td(CEH - PAGEZ) Delay time, (L)DE high to (L)D0 (L)D31 in the high-impedance state Delay time, (L)DE low to (L)D0 (L)D31 valid Delay time, (L)AE high to (L)A0 (L)A23 in the high-impedance state Delay time, (L)AE low to (L)A0 (L)A23 valid Delay time, (L)CEx high to (L)R / W0, (L)R / W1 in the high-impedance state Delay time, (L)CEx low to (L)R / W0, (L)R / W1 valid Delay time, (L)CEx high to (L)STRB0, (L)STRB1 in the high-impedance state Delay time, (L)CEx low to (L)STRB0, (L)STRB1 valid Delay time, (L)CEx high to (L)PAGE0, (L)PAGE1 in the high-impedance state TMS320C44- 50 MIN 0 0 0 0 0 0 0 0 0 0 MAX 15 21 15 18 15 21 15 21 15 21 TMS320C44- 60 MIN 0 0 0 0 0 0 0 0 0 0 MAX 15 16 15 16 15 16 15 16 15 16 UNIT ns ns ns ns ns ns ns ns ns ns
10 td(CEL - PAGEV) Delay time, (L)CEx low to (L)PAGE0, (L)PAGE1 valid This value is specified by design but not tested. This value is characterized but not tested. (L)DE 1 (L)Dx Hi-Z 2
(L)AE 3 (L)Ax Hi-Z 4
(L)CEx 5 (L)R / Wx 7 (L)STRBx 9 (L)PAGEx Hi-Z Hi-Z 10 Hi-Z 8 6
Figure 12. (L)DE -, (L)AE -, and (L)CEx-Enable Timing
25

timing for (L)LOCK when executing LDFI or LDII (see Figure 13)
NO. NO 1 td(H1L - LOCKL) Delay time, H1 low to (L)LOCK low LDFI or LDII External Access H3 TMS320C44- 50 MIN MAX 8 TMS320C44- 60 MIN MAX 8 UNIT ns
H1
(L)STRBx
(L)R / Wx
(L)Ax
(L)Dx
(L)RDYx
1 (L)LOCK
Figure 13. Timing for (L)LOCK When Executing LDFI or LDII
26

timing for (L)LOCK when executing STFI or STII (see Figure 14)
NO. NO 1 td(H1L - LOCKH) Delay time, H1 low to (L)LOCK high TMS320C44- 50 MIN MAX 8 TMS320C44- 60 MIN MAX 8 UNIT ns
STFI or STII External Access H3
H1
(L)STRBx
(L)R / Wx
(L)Ax
(L)Dx
(L)RDYx 1 (L)LOCK
Figure 14. Timing for (L)LOCK When Executing STFI or STII
27

timing for (L)LOCK when executing SIGI (see Figure 15)

NO. NO 1 2 td(H1L - LOCKL) td(H1L - LOCKH) Delay time, H1 low to (L)LOCK low Delay time, H1 low to (L)LOCK high H3 TMS320C44- 50 MIN MAX 8 8 TMS320C44- 60 MIN MAX 8 8 UNIT ns
H1 1 (L)LOCK 2
(L)R / Wx
(L)Ax
(L)Dx
(L)RDYx
(L)STATx
Figure 15. Timing for (L)LOCK When Executing SIGI
28

timing for (L)PAGE0, (L)PAGE1 during memory access to a different page (see Figure 16)
NO. NO 1 2 td(H1L - PAGEH) td(H1L - PAGEL) Delay time, H1 low to (L)PAGEx high for access to different page Delay time, H1 low to (L)PAGEx low for access to different page TMS320C44- 50 MIN 0 0 MAX 9 9 TMS320C44- 60 MIN 0 0 MAX 8 8 UNIT ns ns
H1
(L)R / Wx
(L)STRBx
(L)RDYx 1 (L)PAGEx 2 1 2
(L)Dx
(L)Ax
(L)STATx
(L)STRB1 write to a different page
(L)STRB1 read from a different page
Figure 16. (L)PAGE0, (L)PAGE1 Timing Cycle, Memory Access to a Different Page
29

timing for the IIOFx when configured as an output (see Figure 17)
NO. NO 1 tv(H1L - IIOF) H1 low to IIOFx valid TMS320C44- 50 MIN MAX 14 TMS320C44- 60 MIN MAX 14 UNIT ns
Fetch Load Instruction H3
Decode
Read
Execute
H1
FLAGx (IIF Register)
1 or 0 1
IIOFx Pins
Figure 17. Timing for the IIOFx When Configured as an Output
30

timing of IIOFx changing from output to input mode (see Figure 18)
NO. NO 1 2 th(H1L - IIOF) tsu(IIOF-H1L) Hold time, IIOFx after H1 low Setup time, IIOFx before H1 low 11 0 TMS320C44- 50 MIN MAX 14 TMS320C44- 60 MIN 11 0 MAX 14 UNIT ns ns ns
3 th(H1L-IIOF) Hold time, IIOFx after H1 low This value is specified by design but not tested.
Execute Load of IIF Register H3
Buffers Go From Output to Input
Synchronizer Delay
Value on IIOF Seen in IIF
H1 2 TYPEx (IIF Register) 1 IIOFx Output 3
FLAGx (IIF Register)
Data Sampled Data Seen
Figure 18. Change of IIOFx From Output to Input Mode
31

timing of IIOFx changing from input to output mode (see Figure 19)
NO. NO 1 td(H1L - IFIO) Delay time, H1 low to IIOFx switching from input to output Execution of Load of IIF Register H3 TMS320C44- 50 MIN MAX 14 TMS320C44- 60 MIN MAX 14 UNIT ns
H1
TYPEx (IIF Register) 1 IIOFx
Figure 19. Change of IIOFx From Input to Output Mode
RESET timing (see Figure 20)

NO. NO 1 2.1 2.2 3 4.1 4.2 5 6 7 8 9 10 11 tsu(RESET-C1L) td(CIH - H1H) td(CIH - H1L) tsu(RESETH - H1L) td(CIH - H3L) td(CIH - H3H) td(H1H - DZ) td(H3H - AZ) td(H3H - CONTROLH) td(H1H - IACKH) td(RESETL - ASYNCH) td(RESETH - COMMH) td(H1H-CDIRL) td(H1H-CDIRH) Setup time for RESET before CLKIN low Delay time, CLKIN high to H1 high Delay time, CLKIN high to H1 low Setup time for RESET high before H1 low and after ten H1 clock cycles Delay time, CLKIN high to H3 low Delay time, CLKIN high to H3 high Delay time, H1 high to (L)Dx in the high-impedance state Delay time, H3 high to (L)Ax in the high-impedance state Delay time, H3 high to control signals high [low for (L)PAGE] Delay time, H1 high to IACK high Delay time, RESET low to asynchronous reset signals in the high-impedance state Delay time, RESET high to asynchronous reset signals high Delay time, TMS320C44- 50 MIN 11 2 2 13 2 2 10 10 13 9 9 9 21 15 9 9 MAX tc(CI) 10 10 TMS320C44- 60 MIN 11 2 2 13 2 2 10 10 13 9 9 9 21 15 9 9 MAX tc(CI) 10 10 UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns
12 Delay time, This value is characterized but not tested.
32
CLKIN RESET (see Notes A and B) H1 4.1 H3 (L)Dx (see Note C) 4.2 Control Signals (L)Ax see Note C) Control Signals (see Note D) (L)PAGEx (see Note D) IACK Asynchronous Reset Signals (see Note E) Asynchronous Reset Signals (see Note A) CDIRx (see Note F) 12 CDIRy (see Note F) NOTES: A. Asynchronous reset signals that go to a high logic level after RESET returns to a high state include CREQy, CACKx, CSTRBx, and CRDYy (where x = 1 or 2 and y = 4 or 5). B. RESET is an asynchronous input and can be asserted at any point during a clock cycle. If the specified timings are met, the exact sequence shown occurs; otherwise, an additional delay of one clock cycle can occur. C. For this diagram, (L)Dx includes D31 D0, LD31 LD0, and CxD7 CxD0; (L)Ax includes LA(23 0) and A(23 0). D. Control signals LSTRB0, LSTRB1, STRB0, STRB1, (L)STAT3 (L)STAT0, (L)LOCK, (L)R/W0, and (L)R/W1 go high while (L)PAGE0 and (L)PAGE1 go low. E. Asynchronous reset signals that go into the high-impedance state after RESET goes low include TCLK0, TCLK1, IIOF3 IIOF0, and the communication-port control signals CREQx, CACKy, CSTRBy, and CRDYx (where x = 1 or 2, and y = 4 or 5). At reset, ports 1 and 2 become outputs, and ports 4 and 5 become inputs. F. x = 1 or 2 and y = 4 or 5
1 2.2 2.1 5 Ten H1 Clock Cycles 6 7 7 8 9 9 11 10 3
POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
Figure 20. RESET Timing
33

timing for IIOFx interrupt response [P = tc(H)] (see Notes 9 and 10 and Figure 21)
NO. NO 1 2 tsu(IIOF-H1L ) tw(INT ) Setup time, IIOFx before H1 low Pulse duration, to assure one interrupt seen (see Note 11) TMS320C44- 50 MIN 11 P TYP MAX TMS320C44 - 60 MIN 11 P TYP MAX UNIT ns 1.5P < 2P ns
1.5P
< 2P
If this timing is not met, the interrupt is recognized in the next cycle. This value only applies to level-triggered interrupts and is specified by design but not tested. NOTES: 9. IIOFx is an asynchronous input and can be asserted at any point during a clock cycle. If the specified timings are met, the exact sequence shown occurs; otherwise, an additional delay of one clock cycle can occur. 10. Edge-triggered interrupts require a setup of time (1) and a minimum duration of P. No maximum duration limit exists. 11. Level-triggered interrupts require interrupt-pulse duration of at least 1P wide (P = one H1 period) to assure it will be seen. It must be less than 2P wide to assure it will be responded to only once. Recommended pulse duration is 1.5P. Fetch First Instruction of Service Routine
Reset or Interrupt Vector Read H3
H1 1 (see Note A) 2 FLAGx (IIF Register) First Instruction Address
IIOFx
Address Vector Address Data NOTE A: The C44 can accept an interrupt from the same source every two H1 clock cycles.
Figure 21. IIOFx Interrupt-Response Timing [P = tc(H)]
34

timing for IACK (see Note 12 and Figure 22)

NO. NO 1 2 td(H1L - IACKL) td(H1L - IACKH) Delay time, H1 low to IACK low Delay time, H1 low to IACK high during first cycle of IACK instruction data read TMS320C44 - 50 MIN MAX 9 9 TMS320C44 - 60 MIN MAX 7 7 UNIT ns ns
NOTE 12: The IACK output is active for the entire duration of the bus cycle and is, therefore, extended if the bus cycle utilizes wait states.
Fetch IACK Instruction H3
Decode IACK Instruction
IACK Data Read
Execute IACK Instruction
H1 1 IACK 2
Address
Data
Figure 22. IACK Timing
35

communication-port word-transfer-cycle timing [P = tc(H)] (see Note 13 and Figure 23)

NO. NO 1 2 tc(WORD) td(CRDYL-CSL)W Cycle time, word transfer (4 bytes = 1 word) Delay time, CRDYx low to CSTRBx low between back-to-back write cycles TMS320C44 - 50 MIN 1.5P + 7 1.5P + 7 MAX 2.5P + 170 2.5P + 28 TMS320C44 - 60 MIN 1.5P + 7 1.5P + 7 MAX 2.5P + 170 2.5P + 28 UNIT ns ns
For these timing values, it is assumed that the C4x receiving data is ready to receive data. Line propagation delay is not considered. This value is characterized but not tested. tc(WORD) max = 2.5P + 28 ns + the maximum summed values of 4 td(CSL-CRDYL)R, 3 td(CRDYL-CSH), 3 td(CSH-CRDYH)R, and 3 td(CRDYH-CSL)W as seen in Figure 24. This timing assumes two C4xs are connected. NOTE 13: These timings apply only to two communicating C4xs. When a non-C4x device communicates with a C44, timings can be longer. No restriction exists in this case on how slow the transfer could be except when using early silicon (C40 PG 1.x or 2.x). Refer to the CSTRB width restriction section of the TMS320C4x Users Guide (literature number SPRU063B). CREQx
CACKx 1 CSTRBx
CxDx
B0
B1
B2
B3
Undef. 2
B0
CRDYx
= When signal is an input (clear = when signal is an output). Begins byte 0 of the next word. NOTE A: For correct operation during token exchange, the two communicating C4xs must have CLKIN frequencies within a factor of 2 of each other (in other words, at most, one of the C4xs can be twice as fast as the other).
Figure 23. Communication-Port Word-Transfer-Cycle Timing [P = tc(H)]
36

communication-port byte-cycle timing (write and read) (see Note 14 and Figure 24)
NO. NO 1 2 3 4 5 6 7 8 9 tsu(CD-CSL)W td(CRDYL - CSH)W th(CRDYL - CD)W td(CRDYH - CSL)W tc(BYTE) td(CSL - CRDYL)R tsu(CSL - CD)R th(CRDYL - CD)R Setup time, CxDx valid before CSTRBx low (write) Delay time, CRDYx low to CSTRBx high (write) Hold time, CxDx after CRDYx low (write) Delay time, CRDYx high to CSTRBx low for subsequent bytes (write) Cycle time, byte transfer Delay time, CSTRBx low to CRDYx low (read) Setup time, CxDx valid after CSTRBx low (read) Hold time, CxDx valid after CRDYx low (read) 0 0 2 0 TMS320C44 - 50 MIN 2 0 2 0 12 44 10 0 0 2 0 MAX 12 TMS320C44 - 60 MIN 2 0 2 0 12 44 10 MAX 12 UNIT ns ns ns ns ns ns ns ns
td(CSH - CRDYH)R Delay time, CSTRBx high to CRDYx high (read) 10 10 ns This value is specified by design but not tested. tc(BYTE) max = summed maximum values of td(CRDY-CSH), td(CSL-CRDYL)R, td(CSH-CRDYH)R, and td(CRDYH-CSL)W. This assumes two C4xs are connected. This value is characterized but not tested. NOTE 14: Communication port timing does not include line length delay.
CREQx
CACKx
5 5 CSTRBx 1 CxDx Valid Data 8 6 2 9 7
3 CRDYx 4 (a) WRITE TIMING = When signal is an input (clear = when signal is an output).
(b) READ TIMING
Figure 24. Communication-Port Byte-Cycle Timing (Write and Read)
37

timing for communication-token transfer sequence, input to an output port [P = tc(H)] (see Figure 25)
NO. 1 2 3 4 4.1 4.2 5 6 7 MIN td(CAL - CS)T td(CAL - CRQH)T td(CRQH - CRQ)T td(CRQH - CA)T td(CRQH - CD)T td(CRQH - CRDY)T td(CRQH - CSL)T td(CRDYL - CSL)T td(CRQH - CDIRL) Delay time, CACKx low to CSTRBx change from input to a high-level output Delay time, CACKx low to start of CREQx going high for token-request acknowledge Delay time, start of CREQx going high to CREQx change from output to an input Delay time, start of CREQx going high to CACKx change from an input- to an output-level high Delay time, start of CREQx going high to CxDx change from input-driven to output-driven Delay time, start of CREQx going high to CRDYx change from an output to an input Delay time, start of CREQx going high to CSTRBx low for start of word-transfer out Delay time, CRDYx low at end of word-input to CSTRBx low for word-output Delay time, CREQx high to CDIRx low, change from input to output 0.5P+ 6 P+5 0.5P 5 0.5P 5 0.5P 5 0.5P 5 1.5P 8 3.5P + 12 0.5P 5 MAX 1.5P + 22 2P + 22 0.5P + 13 0.5P + 13 0.5P + 13 0.5P + 13 1.5P + 9 5.5P + 48 0.5P + 13 UNIT ns ns ns ns ns ns ns ns
ns These values are characterized but not tested. These timing parameters result from synchronizer delays and are referenced from the falling edge of H1. The inputs (that cause the output-signal pins to change values) are sampled on H1 falling. The minimum delay occurs when the input condition occurs just before H1 falling, and the maximum delay occurs when the input condition occurs just after H1 falling.
CDIRx 7 3 CREQx 2 CACKx 1 CSTRBx 4.1 5 4
CxDx 6 CRDYx 4.2 = When signal is an input (clear = when signal is an output).
Valid Data Out
NOTE A: Before the token exchange, CREQx and CRDYx are output signals asserted by the 320C44 receiving data. CACKx, CSTRBx, and CxD7 CxD0 are input signals asserted by the device sending data to the C44; these are asynchronous with respect to the H1 clock of the receiving 320C44. After token exchange, CACKx, CSTRBx, and CxD7 CxD0 become output signals, and CREQx and CRDYx become inputs.
Figure 25. Communication-Token Transfer Sequence, Input to an Output Port [P = tc(H)]
38

timing for communication-token transfer sequence, output to an input port [P = tc(H)] (see Figure 26)
NO. 1 2 3 4 5 6 7 8 td(CRQL - CAL)T td(CRDYL - CAL)T td(CAL - CD)I td(CAL - CRDY)T td(CRQH - CRQ)T td(CRQH - CA)T td(CRQH - CS)T td(CRQH - CRQL)T Delay time, CREQx low to start of CACKx going low for token-request-acknowledge Delay time, CRDYx low at end of word-transfer out to start of CACKx going low Delay time, start of CACKx going low to CxDx change from outputs to inputs Delay time, start of CACKx going low to CRDYx change from an input to output, high level Delay time, CREQx high to CREQx change from an input to output, high level Delay time, CREQx high to CACKx change from output to an input Delay time, CREQx high to CSTRBx change from output to an input Delay time, CREQx high to CREQx low for the next token-request MIN P+5 P+6 0.5P 8 0.5P 8 4 4 4 P4 MAX 2P + 22 2P + 27 0.5P + 8 0.5P + 8 22 22 22 2P + 8 UNIT ns ns ns ns ns ns ns ns
9 td(CAL - CDIRH) Delay time, CACKx low to CDIRx high, change from output to input 0.5P 8 0.5P + 10 ns These values are characterized but not tested. These timing parameters result from synchronizer delays and are referenced from the falling edge of H1. The inputs (that cause the output-signal pins to change values) are sampled on H1 falling. The minimum delay occurs when the input condition occurs just before H1 falling, and the maximum delay occurs when the input condition occurs just after H1 falling.
CDIRx 9 8 CREQx 1 CACKx 6 CSTRBx 3 7 CxDx Valid Data Valid Data 4 CRDYx 2 = When signal is an input (clear = when signal is an output). NOTE A: Before the token exchange, CACKx, CSTRBx, and CxD7 CxD0 are asserted by the C44 sending data. CREQx and CRDYx are input signals asserted by the C44 receiving data and are asynchronous with respect to the H1 clock of the sending C44. After token exchange, CREQx and CRDYx become outputs, and CSTRBx, CACKx, and CxD7 CxD0 become inputs. 5
Figure 26. Communication-Token Transfer Sequence, Output to an Input Port [P = tc(H)]
39

timer-pin timing (see Note 15 and Figure 27)

NO. 1 2 3 tsu(TCLK-H1L) th(H1L-TCLK) Setup time, TCLKx before H1 low Hold time, TCLKx after H1 low MIN 10 0 13 MAX UNIT ns ns ns
td(H1H-TCLK) Delay time, TCLKx valid after H1 high NOTE 15: Period and polarity are specified by contents of internal control registers.
H3
H1 2 1 TCLKx 3 3
Figure 27. Timer-Pin Timing Cycle
timing for IEEE-1149.1 test access port (see Figure 28)

NO. NO 1 2 3 tsu(TMS - TCKH) th(TCKH-TMS) td(TCKL - TDOV) Setup time, TMS / TDI to TCK high Hold time, TMS / TDI from TCK high Delay time, TCK low to TDO valid TMS320C44 - 50 MIN 10 5 0 15 MAX TMS320C44 - 60 MIN 10 5 0 12 MAX UNIT ns ns ns
TCK 1 TMS/TDI 3 TDO 2
Figure 28. IEEE-1149.1 Test Access Port Timings
40

MECHANICAL DATA
PDB (S-PQFP-G304)
228 229 Heat slug
PLASTIC QUAD FLATPACK (DIE-DOWN)

153 152
0,27 0,17
0,08 M
0,50
0,13 NOM 304 77 1 37,50 TYP 40,20 SQ 39,80 42,80 SQ 42,40 4,00 3,60 76 Gage Plane 0,25 0,25 MIN 0,75 0,50 0 7
Seating Plane 4,50 MAX 0,08 4040148 / B 10/94 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Thermally enhanced molded plastic package with a heat slug (HSL) Falls within JEDEC MO-143 Thermal Resistance Characteristics Parameter RJC RJA RJA C / W 0.8 16.0 14.2 Air Flow LFPM N /A 0 100 Parameter RJA RJA C / W 12.1 10.0 Air Flow LFPM 250 500
41
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Copyright 1998, Texas Instruments Incorporated

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TMS320C44 DIGITAL SIGNAL PROCESSOR

SPRS031B AUGUST 1994 REVISED DECEMBER 1995

PDB PACKAGE ( TOP VIEW )

Copyright 1995, Texas Instruments Incorporated

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RAM Block 0 (4K bytes) 32 32

RAM Block 1 (4K bytes) 32 32

ROM Block (reserved) 32 32

32-Bit Barrel Shifter

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block diagram (continued)

Continued from previous page

Six DMA Channels

Communication ports 0 and 3 are not connected.

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Pin Functions (Continued)

COMMUNICATION PORT 2 INTERFACE (13 pins)

COMMUNICATION PORT 4 INTERFACE (13 pins)

COMMUNICATION PORT 5 INTERFACE (13 pins)

INTERRUPTS, I / O FLAGS, RESET, TIMER (12 pins)

TCLK1 1 I/O I = input, O = output, Z = high impedance

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Pin Functions (Continued)

EMU1 1 I/O I = input, O = output, Z = high impedance

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PDB Package Pin Assignments Alphabetical Listing

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PDB Package Pin Assignments Alphabetical Listing (Continued)

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PDB Package Pin Assignments Numerical Listing

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PDB Package Pin Assignments Numerical Listing (Continued)

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Boot-Loader ROM (Internal)

1K RAM BLK 0 (Internal) 1K RAM BLK 1 (Internal)

Global Bus (alias region, see Figure 2)

Global Bus (alias region, see Figure 2)

Figure 1. Memory Map for the 320C44

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