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ADHESIVE (SMT)
A substance such as glue or cement used to fasten objects together. In surface mounting, an epoxy adhesive is used to adhere SMDs to the substrate. De-ionized water wash process used to remove contaminates and flux residue from the PCB. Teradyne uses an aqueous cleaning system. The act or operation of assembling discrete components to printed boards by means of electronically controlled equipment. Manual process to route, solder and tie down coax or other cable assemblies. Component insertion equipment installs the leads of a PTH component Into the PCB, cuts each lead to the proper length and then clinches some or all of the leads against the Surface of the PCB. Current capability includes axial insertion, DIP insertion, SIP insertion and socket Insertion.
CURE DPMO
A chemical reaction that changes the physical properties of a substance, e.g., an adhesive. Defects per million opportunities is the number of defects divided by the number of opportunities multiplied by one million. Process to dispense adhesive material used to secure large parts on the bottom side of PCB. Solder paste is also dispensed on land pads for BGA rework. Manual process to incorporate jumper wires and other add-on components required by engineering change documentation. Preconditioning leaded components by forming and/or trimming leads prior to insertion. Manual process. Soldering using a solder iron or other hand-held, operator controlled apparatus. Manual installation of mechanical components such as Ejectors, Heat sink Plates, air baffles etc.
DISPENSING (SMT)
ECO ASSEMBLY
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Abbreviation
Description
PRESS-FIT
Manual process to press-fit an electrical contact into a hole in a printed board with or without Plated thru holes. Process to apply a material (solder paste or thermally conductive epoxy) by forcing it thru a stainless steel stencil. Two methods are employed in printing: automated (solder paste printing for PCBs) and manual (thermally conductive epoxy for heat sink applications). The joining of surfaces that have been tinned and have solder between them, placing them together, heating them until solder flows, and allowing the surfaces and the solder to cool in the joined surfaces. The act of reprocessing non-complying articles, thru the use of original or alternate equivalent processing, in a manner that assures compliance of the article with applicable drawings or specifications. Manual process to hand load socketed components such as relays into pre-installed sockets. Solder paste is a homogeneous mixture of metal spheres and flux that promotes wetting. Two automated methods are used to apply solder paste to the PCB surface: printing or dispensing. Printing, which has the fastest cycle time and best process capability, is the preferred process. Manual process where the bonding surfaces are abraded prior to applying epoxy. A process wherein an assembled printed board is brought in contact with the surface of a continuously flowing and circulating mass of solder Unplated holes used to position component alignment fixtures during assembly and soldering. PCB material used to adapt PCB arrays to conform to PTH, In-Line or Carrier formats. PCB material used to extend the dimensions of a PCB image or array to conform to PTH or In-Line formats. Snap-off tabs between images in an array to permit depanelization after assembly. PCB images arranged in rows & columns to reduce costs or meet processing format requirements.
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PRINTING (SMT)
MULTI-IMAGE ARRAYS
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Abbreviation
Description
PANELIZATION
Method to reduce costs by using break off borders, extensions or by creating multi-image arrays. Processing format for Mixed Technology Boards that do not meet requirement of In-Line format. Refers to a single PCB which can be processed individually or as part of an array. Processing format for leaded technology boards that permits use of standard board holding plates. Webs of PCB material between images in an array which are cut or routed after assembly. Grooves cut between images in an array to permit depanelization after assembly. Processing format for SMT or Mixed Technology Boards that do not meet requirement of In-Line format. Processing format for Mixed Technology Boards that permits conveyorized board handling. Un plated holes used for mechanical board alignment during assembly and test.
SAW SCORING SMT CARRIER FORMAT SMT IN-LINE FORMAT TOOLING HOLES
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Table of Contents
1 2 3 4 5 6 7 8 9 10 11 Introduction..................................................................................................................................8 Tooling Holes, Fiducials..............................................................................................................8 Layout considerations (SMT/THT)...............................................................................................9 PTH Calculations .......................................................................................................................11 Outline Drawing dimension and requirements.........................................................................12 Stackup construction ................................................................................................................12 Silkscreen guidelines ................................................................................................................13 SOLDERMASK REQUIREMENTS ..............................................................................................13 Solder Paste Requirements.......................................................................................................14 PCB Surface Finishes................................................................................................................14 Soldering Types and Layout Requirements .............................................................................16 11.1 11.2 11.3 11.4 12 13 Design Guideline for Reflow soldering...........................................................................16 Design Guideline for Intrusive Reflow............................................................................16 Design Guideline for Wave Soldering............................................................................17 Selective Wave Soldering Requirements.......................................................................18
Assembly Drawing Requirements:............................................................................................18 Panelization and De-Panelization..............................................................................................19 13.1 13.2 Panelization: .................................................................................................................19 Depanelization Methods:...............................................................................................20
14 15 16
Vias (Types, Preferred, Via Selection).......................................................................................22 Laminate Material Selection ......................................................................................................25 Pb-free Laminate Characteristics..............................................................................................26 16.1 Laminate Selection .......................................................................................................27
17
ROHS compliance......................................................................................................................28 17.1 17.2 Minimum RoHS Component Requirements ...................................................................28 All PCB surface finishes must meet the following requirements .....................................29
18 19
Chip Components......................................................................................................................30 Design for Testability Guidelines..............................................................................................52 19.1 ICT (In circuit Test) Mechanical Guidelines ...................................................................52 19.1.1 19.1.2 19.1.3 19.1.4 19.1.5 Probe Spacing .....................................................................................................52 Probe Access.......................................................................................................52 Test Pad Density..................................................................................................53 Test Pad Requirement: ........................................................................................53 Test Pad Diameter: ..............................................................................................54
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19.1.6 19.1.7 19.1.8 19.1.9 19.1.10 19.1.11 19.1.12 19.1.13 19.1.14 19.1.15 19.2 19.3
Test Pad to Test Pad Spacing: .............................................................................54 Test Pad to a Via Clearance.................................................................................55 Test Pad to Component Pad Clearance ...............................................................55 Test Pad to Edge of Secondary Side Component Clearance ................................56 Test Pad to Secondary Side Trace Clearance ....................................................56 Test Pad to Edge of Board Clearance ................................................................57 Test Pad to Tooling Hole Clearance ...................................................................57 Test Pad to thru-hole device lead clearance .......................................................58 Test Pad to high components.............................................................................58 Table for quick reference....................................................................................59
Design for Test (DFT) Deliverables: ..............................................................................59 ICT (In circuit Test) Electrical Guidelines.......................................................................60 19.3.1 19.3.2 19.3.3 19.3.4 19.3.5 19.3.6 19.3.7 19.3.8 19.3.9 19.3.10 19.3.11 19.3.12 Tri-State Devices, Output Enables........................................................................60 Do Not Tie Control Pins Directly to Power or Ground Rails. ..................................60 Common Circuitry Must Have Unique Control.......................................................61 Break Feedback Loops ........................................................................................62 Clocks and Oscillators..........................................................................................62 Tweaks ................................................................................................................63 Three-Pin Polarized Capacitors............................................................................64 Logic Cell Programmable Gate Arrays (LCA)........................................................64 Boundary Scan Implementation............................................................................64 FPGA's and Non-1149.1 ASICS .........................................................................65 Pass-Through Mode...........................................................................................65 Identification and Revision Code ........................................................................65
19.4
19.5
19.6
BGA devices with NAND-Chain Test Capability.............................................................67 19.6.1 19.6.2 19.6.3 Tri-State Control Pin/Sequence ............................................................................67 Maximum Size Pin Group or NAND Chain Length ................................................67 NAND Chain Test Point Allocation........................................................................67
19.7
Power & Ground Test Pad Requirements......................................................................67 19.7.1 19.7.2 Supply Power Probe Calculations.........................................................................67 Ground Probe Calculations ..................................................................................68
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20
COMPONENT AND ASSEMBLY ISSUES:..................................................................................69 20.1 20.2 20.3 20.4 20.5 Considerations for Component Mounting:......................................................................69 Automatic/Manual placement and Insertion: ..................................................................70 PCB AND ASSEMBLY PANELIZATION:.......................................................................72 PRINTED BOARD AND ASSEMBLY VIEWING PRINCIPLES:......................................74 COMPONENT SELECTION & LAND PATTERN DESIGN.............................................75 20.5.1 20.5.2 20.5.3 20.5.4 20.5.5 20.6 SMT component Selection: ..................................................................................75 Component Mix....................................................................................................75 Process Compatibility Requirements ....................................................................75 Non-Preferred Components .................................................................................76 Land Pattern Design: ...........................................................................................76
COMPONENT PLACEMENT ........................................................................................77 20.6.1 20.6.2 Primary vs. Secondary Side Placement................................................................77 COMPONENT ORIENTATIONS ..........................................................................82
20.7
ASSEMBLY CONSIDERATIONS FOR SURFACE MOUNT ..........................................88 20.7.1 20.7.2 TECHNOLOGY (SMT) .........................................................................................88 SMT Assembly Process Sequence.......................................................................88
PCB ASSEMBLY DRAWING NOTES ...........................................................................90 ASSEMBLY PANEL DRAWING ....................................................................................90 HARDWARE ASSEMBLY INSTRUCTIONS..................................................................91 DESIGN FOR ASSEMBLY (DFA) O/P DATA REQUIREMENT......................................91 REWORK .....................................................................................................................92 Heatsink Effects............................................................................................................93 Dependence on Printed Board Material Type ................................................................93 Dependence on Copper Land and Conductor Layout ....................................................93 Design Considerations for Repair and Inspection ..........................................................93
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1 Introduction
Design for Manufacturability, which defines the rules and standards for the best suitability of the PCB manufacturability by most of the vendors. By implementing these rules at design phase (i.e., before proto build) will gives us following advantages, Production Cost - get reduced as the problems at production will be less Engineering Change Cost - will be less, as changes at production stage will be less in turn the staffing required for the ECO will be less Quality by following the DFM guidelines all the problem which could occur in the field will be identified at the proto development itself. This increases the quality of the product developed Reduced Time to Market Design cycle of the DFM implemented products will take more time than the regular designs but the production phase and the deliverable phase will get reduced dramatically. Almost 40% of the product development time will be reduced by following DFM guidelines.
Automatic Insertion In-Circuit Test Fixtures Custom Carrier Fixtures Wave Solder Fixtures
In-Circuit Test Fixtures Custom Carrier Fixtures Wave Solder Fixtures Press Fit Fixtures
b) Fiducials are used to get the reference on the board, for auto placement of components and other PCB handling equipments to avoid mechanical placement errors. Local, Global and Panel fuducials are the types of fiducial marking. Following rules should adhere to have a clear use of Fiducials on the board i) ii) Should be placed minimum of 0.200 and maximum of 1.5 from the board edges Should have clearance from silk, mask and copper. Mask should be cleared for the size of at least double as pad size.
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iii) iv)
Should be visible all the time, even after the board is populated There should be 3 board fiducials placed each on either side of the board on the corners, 2 of them should be placed in diagonal corners. Bottom side fiducials should be placed in the same location as of the Top side fiducials, as this will give a different image for both the layers while the board is placed in PCB handling equipments. These fiducials should be placed where there is no plane underneath or the plane under the fiducials can be voided to have clarity of the fiducial. Local fiducials should be placed for the fine pitch components which have less than 0.5mm pitch including BGA and this fiducial can be shared by the fine pitch components placed within 5 circumferences. This will lead to find accurate position of the component and placement. Preferred fiducial size is 0.040 pad and 0.080 soldermask.
v) vi)
vii)
d) SMT parts and PRESS FIT parts placement in 90 rotation is preferred and 1 increment is allowed, but for Though hole parts 90 rotation is only allowed and preferably these parts should be placed in same direction. Auto insertion of thru hole components is not possible other than 90. Nomenclatures should be placed in 90 rotation for readability. e) Rework clearance for all the components to be provided for debugging and rework. This will vary per component size and height of the component. Please refer page no 75 & 76 for these values. f) Thermal relief should be used to connect thru hole pin to get connected to copper area/plane, else the heat will be dissipated and solder alloy will not get the temperature for proper solder flow, results in cold solder joints.
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g) Copper traces connected to 1206 and smaller components should have equal width on both pins, this will help to prevent part movement during re-flow soldering.
h) Copper traces should not be routed between discrete component packages, to avoid soldermask opening (Copper expose) in that areas due to adhesive material usage during solder process. Vias also should be avoided underneath the components like
i)
In BGA, fan-out vias can be removed wherever not used, but the fan-out trace should be retained to hold the pads of BGA to the PCB during rework process.
j)
Direct routing between the SMD pins not allowed, routing should be done outside the land pattern, which will be used to do rework when there is a need. Direct short will make the board testing person to think that it is unintentionally done.
k) Enough clearance should be maintained between via to via and pad to via. VIA to VIA VIA to VIA Minimum spacing 12 mil Minimum spacing 15 mil Trace width / space 4 / 4 Trace width / space 5 / 5
Pad to VIA
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4 PTH Calculations
Axial lead span calculation, Lead protrusion, Hole clearance a) Axial lead span can be calculated as follows
Dia = B X
A
Lead span X = A + B + 0.200
Lead span value to be rounded off to the next largest 0.025 increment.
b) Lead Protrusion:
c) Hole Clearance:
Pad
d = Pin Size (diameter if lead is round, diagonal size if the pin is rectangular or square) D = Hole Clearance d+0.015 if d < 0.050 d+0.018 if d = 0.050 to 0.080 d+0.020 if d = 0.081 to 0.100 and d+0.022 if d > 0.100
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6 Stackup construction
Stackup should be designed such a way that the copper weight is balanced from centerline of the cross section of the board, by symmetrically distributed Plane layers and Signal layers. Stackup diagram should give all the necessary details like, layer order, thickness of signal, plane and dielectric layers, total thickness of the board with tolerance. Stackup Rules: a) Symmetrical dielectric thickness to be used. b) Layer count cannot be odd, use even number of layers (like 2, 4, 6, 8 c) Dielectric layer thickness should be more than 0.004 d) Offset the plane layer edges around the perimeter to avoid mechanical damages to the dielectric, for minimum of 0.025. e) Copper weight should be equal on both sides of each core layer. f) Copper distribution should be done across each individual layer. )
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7 Silkscreen guidelines
Silkscreen is used in a PCB to identify component locations, polarity, component orientation, component reference designators and label locations. Following are the requirements of silkscreen in PCB, a) b) c) Pin one marking should be done on silkscreen layer for both SMT and PTH multileaded device. Polarity marking should be done for the polarized components. Reference Designators for the components should have the minimum dimension of 0.031 height by 0.023 wide with 0.006 line width and preferred dimension is 0.031 width and 0.050 height with 0.006 line width. Silkscreen is not allowed on solderable pads, should be cleared from these pads for a minimum distance of 0.016 to 0.020. On a complex design these values can be 0.005 to 0.010. Silkscreen to silkscreen overlap should be avoided. Reference designators and polarity marking of a component should be placed outside the symbol to have the visibility of the same during testing and rework. Label location should be defined in Silkscreen, Label type and size will vary depends on the requirement. This will be used to identify the part number and the serialization of the work done. Label area should be away from SMT locations, test pads and nomenclature. Multiple Pin numbers on silkscreen for high pin count component is advisable and if the pin number for BGA is provided on non-component side, debugging will be easier.
d)
e) f)
g) h)
8 SOLDERMASK REQUIREMENTS
a) Solder Mask is provided to avoid soldering of unwanted portions of a pad and trace, usually the mask will have a clearance maximum of 3 mils on all sides of the pad. b) LPI is the material being used usually for the board containing fine pitch components like BGA. c) SolderMask web of less than 0.005 should be avoided in dense packages like QFP, QFN, and SOP. To achieve this gang mask will be used for the pins on each side of the package. Gang mask is required on the components having pin pitch less than 0.020.
d) Soldermask dam should be present between via and the solder pad to avoid copper thieving on via.
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e) On Thermal pads inside a component should have adequate opening in soldermask and should have solder paste if required. f) Vias can be tented wherever the density of via is high to avoid shorts. g) Via plug-in to be used where vias are tented on one side, and via plug-in should not extend beyond the via pad edge and should have height less than 0.002 from via surface. h) Solder mask tenting is not preferred with HASL and immersion surface finishes due to solder ball formation or contamination entrapment.
Plus: Common technology, Nothing solders like solder. Press fit compatible. Plated solder with flat topology is highly desirable for lead free application. Minus: Horizontal vs. Vertical Domed Surface makes it unsuitable to Fine Pitch QFPs, BGAs and 0402/0201 passives PCB thickness limits b) Organic Solderability Preservatives (OSP) Use: Surface mount, Plated-through hole HASL alternative Plus: Low cost alternative to HASL. Environmental friendly, planar surface perfect for Fine Pitch QFPs, BGA and small passives Press fit compatible Capable of being "renewed" prior to use if oxidized Lead free alternative
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Minus: Variability in spread, not visible to the eye Prone to oxidation if poorly handled Shelflife less than 6 months Degrades with exposure to high temperatures and alcohol/water washes c) Immersion Gold over Electro less Nickel (Also known as Electro less Nickel, Immersion Gold (ENIG)) Use: Surface mount with ultrafine pitch and co planarity, 3-8 micro inches gold Plus: Low, stable electrical contact resistance over long periods excellent solderability, may be wire bonded Planar surface perfect for Fine Pitch QFPs, BGA and small passives Press fit compatible, cosmetically appealing and Low oxidation. Lead free alternative Minus: Tight process window, Phosphorus Enrichment, Skip plating, Black Pad, Brittle Ni/Sn inter-metallic, Micro-voiding d) Electrolytic Gold over Nickel Use: Full body gold plating, Selective plating for surface mount connectors and internal switch contacts, typical 2040 micro inches Plus: Low and stable electrical contact resistance over long periods cosmetically appealing. Low oxidation. Minus: Requires bussing or pre-etch plating distribution and thickness variation across panel. Selective gold requires extra process and adds cost. Bussing leaves stubs and embrittlement. e) Tab Plated Hard Gold over Nickel Use: Edge connectors for plug-in boards Plus: Excellent wear resistance Minus: Conveyor driven, plating line bussing required, Taping required f) Immersion Tin Use: Surface Mount with ultrafine pitch and co-planarity Plus: Planar surface. Metallic finish applied over copper with Ni barrier. Uses the same chemistry and set up as HASL. Shelf life of two years Lead free alternative Minus: Batch Plating Line. Tin whisker potential g) Immersion Silver Use: Surface Mount with ultrafine pitch and co-planarity, typical 30-60 micro inch thickness Plus: Planar surface perfect for Fine Pitch QFPs, BGA and small passives Press fit compatible. Cosmetically appealing. Low oxidation. Lead free alternative for Class I & II Products only
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Minus: Emerging technology. Not available at all suppliers. Limited assembly performance data. Micro-voiding
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a) Active SMT and Fine Pitch components typically should not be wave soldered. b) Small components should not be placed next to tall components to prevent shadowing. c) Topside PTH connectors should be oriented with the long axis perpendicular to the wave. d) A large number of open vias can cause fine pitch SMT components on the component side of the PCB to reflow during wave. Tenting or plugging vias can help reduce thermal heat transfer to the top of the PCB. Dispersing vias away from the fine pitch component will also help. e) Orient bottom side components in one direction if the assembly is to be waved. Axis of chip components should be parallel to wave and ICs should have long axis perpendicular to wave. Incorrect component orientation can result in uneven solder joint fillet formation or solder skip as shown in figures below
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f) Minimum pad-to-pad spacing for a surface mount pads and through-hole PGA and axial component for wave soldering is recommended to be as shown in figures below
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c) Pin numbers at corners if pin count is higher than 24 d) Board outline e) Board title block f) Notes, to describe assembly instructions if there is any g) Cross reference for the mechanical parts against the Assembly BOM
7 6
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1. Non-plated tooling hole at left bottom corner, the drill size allowed is between 0.125
(IRM)), is used to identify the partially good image or partially good panel, where the assembly process will not be carried out so that the process cycle time will get reduced by omission of the bad board. i. There should be space allotted for local IRM and Global IRM as shown in the figure and there are two types of IRM used as shown, one is local and another is global. One IRM per side should be placed where components to be populated on PCB (Component / Solder side). Edge of these IRM should be away from the board edge as well as panel edge for 0.197.
ii. iii.
3. Local Bad-Board Markers or IRMs located at a corner of the panel, one per each
board image and in the same pattern as the board images placed in the panel.
4. Two sides of the Panel other than conveyor edges should have cleared from all
solder processes
d) If any of the images crosses the panel keepout should follow the panel keepout for
components.
e) Solder mask must be removed from the board edge for a minimum of 0.015 and
preferred is 0.025.
f)
Copper must be avoided for 0.025 from the board edge to mitigate corrosion issues that affect the reliability of the PCB. cutting depth.
g) Maximum board thickness for panelized edges is 0.150 based on maximum router-bit h) Asymmetric placement of tooling holes and global fiducials are preferred to prevent
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Minus: Requires custom fixturing, requires custom programs, Highest manufacturing costs, Process generates dust, requires solder sample for programming and setup. Recommended For Small boards, complex outlines, more number of images on subpanels. Boards are less than 0.150 nominal thickness. Accuracy: 0.005 and 0.015 for less expensive routing. 2) Score and break Plus: Inexpensive depanelization method, Requires no unique fixturing, de-lamination is less likely since solder mask layer is cut off during scoring. Minus: Less accurate than routing, rough edge with thick boards, Requires 0.025" solder mask to edge keepout, Requires largest copper pullback and component keepout. Recommended For: Rectangular boards, 0.093" boards, No cosmetic or precise dimensional requirement. Accuracy: 0.015".
3) Shear: Plus: Allows for quick separation of thin cards using guillotine. Minus: Only advised on boards less than 0.032" thick, Imparts a high degree of stress to the PCA. Recommended For: Thin boards with simple outline and nominal thickness of 0.029". Accuracy: 0.020". 4) Breakaway: Plus: Inexpensive manual method of breaking cards out of panel. Minus: Leaves rough edges at tab locations. Recommended For: Boards greater than 0.093", Non-rectangular boards, No cosmetic or precise dimensional requirement (external breaks extend past the outer dimensions of the card). Accuracy: 0.005" except at break locations.
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4) Thru hole vias should not be placed on SMT pads, blind vias can be used on decaps to connect to the immediate plane layer. 5) Vias should not be placed between the pads of passive components. This will reduce solder shorts.
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6) Plug or tent vias within BGA footprint on the device side. On the opposite side of the board bring mask up to knee of barrel but leave via open. This will reduce the risk of outgassing. 7) Spacing between via-via and via-pad limited to 0.015 and can go down upto 0.010 on a complex board. 8) Preferred thru via sizes are 0.010 drill 0.020 pad for digital signals and 0.020 drill 0.036 drill for power and analog signals, but the calculations will be done by the design engineer to decide what sizes to be used on the board depends on the design requirement. 9) Via drill should be selected as per the aspect ratio requirement as follows, The aspect ratio of plated-through holes plays an important part in the ability of the ratio guidelines for holes. Exceptions can be made depending on board house capability and plated-through hole life requirements. Aspect ratio is defined as the ratio of the length or depth of a hole relative to its pre-plated (drilled) diameter. The aspect ratio plays an important part in the ability of the manufacturer to provide sufficient plating within the drilled hole. The producibilty impact of various levels of complexity is shown below (reference IPC-D275, paragraph 5.4.8.1) Level a General Design Complexity Preferred AR 3:1 to 5:1 Level B Moderate Design Complexity Standard AR 6:1 to 8:1 Level C High Design Complexity Reduced AR > 9:1 A PWB with a nominal thickness of .090 and with minimum diameter holes drilled using a .0135 (#80) drill falls into the moderate design complexity range i.e., .090/.0135 = 6.7:1 10) Recommended minimum drill size versus board thickness is given in the table below
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11) Blind via plated-through holes extend from the surface and connect the surface layer with one or more internal layers. If an interconnection is desired between the surface layer and more than one internal layer, sequential etching, laminating, drilling and plating-through of these layers together before final multilayer lamination is required. Blind via holes should be filled or plugged with a polymer or solder resist preventing solder form entering them since solder in the small holes decreases reliability. Minimum drill sizes for blind vias are given below (as per IPC 2221),
12) Buried via plated-through holes do not extend to the surface but interconnect only internal layers. Most commonly the interconnection is between two adjacent internal layers. These are produced by drilling the thin laminate material, plating the holes through and then etching the internal layer pattern on the layers prior to multilayer lamination. Buried vias between non-adjacent layers requires sequential etching of
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inside layers, laminating them together, drilling the laminated panel, plating the holes through, etching external sides and laminating this panel into the final multilayer panel. Minimum drill sizes for buried vias are given below (as per IPC 2221),
When selecting laminates for high frequency applications make sure the Dk and Df for a given Tg is appropriate for the application of the product. Other laminate characteristics have become more critical at Pb-free soldering temperatures. When selecting laminates for use in the Pb-free process the following additional characteristics should be considered: Decomposition Temp Z-axis expansion CAF Resistance Moisture Sensitivity Time to de-lamination - at T = 288C and T = 260C
Table below prescribes laminate recommendations based on reliability requirements of the assembly, complexity of technology used in the assembly and the physical PCB characteristics (thickness, layer count and weight of Cu). Although the table includes typical technology descriptions of the PCBs for the respective reliability categories, the primary driver when selecting a laminate should be the reliability requirements. Note: CAF (Conductive Anodic Filament) - describes the growth of a conductive filament from an anodic (-ve) to a cathodic (+ve) surface along the glass-epoxy interface. This growth can result in shorts between adjacent vias and ground or power planes, if the filament is allowed to bridge completely. De-lamination may also occur in severe cases. CAF resistance is affected by the plating process, size of barrel, laminate material (coupling agents) and quality of drilling process. At elevated temperatures, where there is a higher propensity for laminate cracking, the threat of filament growth increases and CAF resistance becomes a critical parameter. The
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effects of filament growth are only detectable in the field and cannot be caught at ICT. The growth of the CAF does not immediately lead to a reduction in resistance between vias, in fact resistance only drops as the CAF grows the last few percent of the gap. Dicyandiamide (dicy), is the most common cross-linking agent used in FR-4. The traditional "dicy" resin system that has been used for High Tg FR4 based materials generally will not be able to withstand the higher temperature reflow profiles, and as such, a "non-dicy" resin based material will need be used in most cases.
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For low frequency applications (<900 MHz) standard FR4 material will be sufficient if the board thickness and number of layers is kept to a minimum. Applications in the 900MHz 1.9 GHz a more stable glass based material can be used. If the application is over 1.9 GHz or the temperature is extreme then a PTFE/Ceramic material will be required. If design requires mixed signals such as RF/IF or RF/Digital then a board with mixed materials design should be considered. As in all designs the number of layers (thickness) should be kept to a minimum (2 preferred for RF only designs), but also the diameter of the vias should be kept as small as possible.
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17 ROHS compliance
The Restriction of Hazardous Substances (RoHS) Directive comes into effect on July 1, 2006 and bans the sale of electrical and electronic equipment containing the following chemicals: Lead (Pb) Cadmium (Cd) Mercury (Hg) Hexavalent Chromium (Cr6+ or Cr VI) Polybrominated Biphenyls (PBB) Polybrominated Diphenyl Ethers (PBDE)
The proposed wording of the legislation indicates that "... the maximum permissible amount of each material is 0.1% by weight in the applicable homogeneous material, with the exception of Cadmium. The maximum permissible amount of cadmium is 0.01% by weight in the applicable homogeneous material." The Waste Electrical and Electronic Equipment (WEEE) Directive introduces mandatory collection, re-use and recycling of electrical and electronic products, and requires producers of electrical and electronic equipment to finance collection arrangements for their products -both new products and goods already on the market - at the end-of-life. Compliance readiness expectations for WEEE begin in 2004. The biggest challenge to the printed circuit assembly process due to RoHS, is the elimination of Lead (Pb) from the soldering process. The new Pb-free products that primarily affect the following areas. Component Selection PCB surface finishes PCB laminate selection Hot Air Rework Via technology Through hole processes (Pin through Hole (PTH) wave and Paste in Hole PIH))
IPC/JEDEC J-STD-020) at a process temperature of 260C +5C/-0C. The MSL rating at this temperature shall be determined using the method listed in J-STD-020. This rating shall be clearly indicated on the barcode or MSL Caution Label as defined in J-STD-033.
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4. All
process
package
classification
reflow
5. All components should meet the RoHS directive (2002/95/EC) material requirements.
17.2 All PCB surface finishes must meet the following requirements
Environmental impact: RoHS banned substance must not be part of the finish Chemistry. Must be capable of withstanding multiple reflows at elevated temperatures (max 260C) Must be compatible with the finish on the component leads to limit the impact of intermetallic growth after reflow. Must exhibit good wetting, as per J-STD-003 and IPC-A-610 specifications. Dendrite formation - should show minimum amounts of electro migration (effect worsens at Pb-free process temps) Discolouration - should show minimum amounts of discoloration from soldering operations (effect worsens at Pb-free process temps) It is preferred (but not required) that the surface finish can be used with both SnPb and Pb-free soldering operations.
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EIA 0201, METRIC 0603 EIA 0402, METRIC 1005 EIA 0504, METRIC 1310 EIA 0603, METRIC 1608 EIA 0805, METRIC 2012 EIA 1206, METRIC 3216 EIA 1210, METRIC 3225 EIA 2010, METRIC 5025 EIA 2512, METRIC 6332
Confidential
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Standard Name
Z (mm)
G (mm)
X (mm)
Y(REF) (mm)
C(REF) (mm)
EIA 0201, METRIC 0603 EIA 0402, METRIC 1005 EIA 0504, METRIC 1310 EIA 0603, METRIC 1608 EIA 0805, METRIC 2012 EIA 1206, METRIC 3216 EIA 1210, METRIC 3225 EIA 2010, METRIC 5025 EIA 2512, METRIC 6332
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Standard Name
Z (mm)
G (mm)
X (mm)
Y(REF) (mm)
C(REF) (mm)
EIA 0201, METRIC 0603 EIA 0402, METRIC 1005 EIA 0603, METRIC 1608 EIA 0805, METRIC 2012 EIA 1206, METRIC 3216 EIA 1210, METRIC 3225 EIA 1812, METRIC 4532
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EIA 1825, METRIC 4564 EIA 2220, METRIC 5650 EIA 2225, METRIC 5664
Standard Name
Z (mm)
G (mm)
X (mm)
Y(REF) (mm)
C(REF) (mm)
EIA 0201, METRIC 0603 EIA 0402, METRIC 1005 EIA 0603, METRIC 1608 EIA 0805, METRIC 2012
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Standard Name
Z (mm)
G (mm)
X (mm)
Y(REF) (mm)
C(REF) (mm)
EIA 1206, METRIC 3216 EIA 1210, METRIC 3225 EIA 1812, METRIC 4532 EIA 1825, METRIC 4564 EIA 2220, METRIC 5650 EIA 2225, METRIC 5664
0.90 1.45
1.10 1.75
0.30 0.65
0.70 0.95
0.10 0.20
0.40 0.50
0.60 0.95
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2012 Chip 2520 Chip 3216 Chip 3225 Chip 4532 Chip 5750 Chip 6350 Chip
1.80 2.30
2.20 2.70
1.05 1.70
1.45 2.30
0.20 0.20
0.80 0.50
1.30 2.20
Standard Name
Z (mm)
G (mm)
X (mm)
Y(REF) (mm)
C(REF) (mm)
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Standard Name
Z (mm)
G (mm)
X (mm)
Y(REF) (mm)
C(REF) (mm)
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TW max (mm) H
Z (mm)
G (mm)
X (mm)
Y (mm)
C (mm)
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T max (mm)
Component Type
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Z (mm)
G (mm)
X (mm)
Y (mm)
C (mm)
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Z (mm)
G (mm)
X (mm)
Y (mm)
C (mm)
7028 (Resistor)
8.05
3.55
3.10
2.25
5.80
T max (mm)
A max (mm)
B max (mm)
H max (mm)
Pitch (mm)
SOT 23
2.60
3.00
0.41
0.55
0.35
1.30
2.90
0.55
1.35
0.95
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Component Identifier
Z (mm)
G (mm)
X (mm)
Y (mm)
C (mm)
P (mm)
SOT 23
3.75
1.25
0.65
1.25
2.50
0.95
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T max (mm)
A max (mm)
B max (mm)
H max (mm)
K Min
(mm)
(mm)
SOIC28
0.49
0.40
1.10
7.60
18.10 2.65
1.27
0.10
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Component Identifier
Z (mm)
G (mm)
X (mm)
Y (mm)
C (mm)
E (mm)
SOIC28
11.30
7.50
0.60
1.90
9.40
1.27
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T max (mm)
A max (mm)
B max (mm)
H max (mm)
P (mm)
SOJ28
11.05 11.30
0.38
0.51
1.52
2.04
10.29
18.85 3.75
1.27
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Component Identifier
Z (mm)
G (mm)
X (mm)
Y (mm)
C (mm)
E (mm)
SOIC28
12.00
7.20
0.65
2.40
9.60
1.27
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W1 max (mm)
H max (mm)
P (mm)
(mm)
QFN16
2.90
3.10
2.90
3.10
0.20
0.30
0.95
1.25
0.30
0.50
0.80
0.50
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Component Identifier
Z1/Z2 (mm)
X1 (mm)
Y1 (mm)
X2/Y2 (mm)
C1/C2 (mm)
E (mm)
QFN16
3.75
0.30
0.85
1.25
2.90
0.50
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A max (mm)
B max (mm)
H max (mm)
P (mm)
PLCC32
12.32 12.57
14.86
15.11 11.51
14.05
0.33
0.53
1.50
2.00
3.57
1.27
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Z1 min (mm)
Z2 max (mm)
G1 min (mm)
G2 min (mm
C1 max (mm)
C2 max (mm)
X1 min (mm
Y1 max (mm)
E (mm)
PLCC32
13.30 15.90
8.50
11.10 10.90
13.50
0.65
2.40
1.27
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B Ref. (mm)
H Max (mm)
BGA256
27.00
27.00
0.75
2.56
1.27
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C1/C2 (mm)
X (mm
E1 / E2 (mm)
BGA256
24.13
0.60
1.27
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Building test fixtures for almost anything is possible given enough time and money. However, using the guidelines presented here will help you design boards that are economical and reliable to test. In many cases you may not be able to fully follow the guidelines, but if you deviate as little as possible, you will achieve the best success
Confidential
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Probe Targets or Preferred Test Points Assignment of test points should be prioritized in part by the type of test target. Maintain the following priority when assigning test points listed in descending order of preference: Test pad, round or square, Through-hole with a soldered lead, Open through-hole. Non-masked via
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A B
Test PAD A = Minimum Test Pad diameter = 0.762mm (0.030") B = Minimum Solder Mask and Silkscreen - Keep Out diameter = A + 0.152mm (0.006")
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Test PAD
VIA
Minimum test pad to via distance 19.1.8 Test Pad to Component Pad Clearance
As shown in below Figure, the minimum clearance, D, required between a test pad and a Component pad is 0.015". However a spacing of 0.020" is preferred for proper clearance.
Test PAD
COMPO E T.
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Test PAD
COMPO E T.
Minimum test pad to component body clearance 19.1.10 Test Pad to Secondary Side Trace Clearance
As shown in below Figure, the minimum clearance, D, required between a test pad and Secondary or bottom side trace is 0.010". However a spacing of 0.015" is preferred for proper clearance.
nce.
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19.1.11
As shown in below Figure, the minimum clearance, D, required between a test pad and edge of board or any big aperture of the board is 0.040". However a spacing of 0.125" is recommended.
Edge of BUT
Test PAD
19.1.12
As shown in below Figure, the minimum spacing, D, required between a test pad and a tooling hole is 0.125". However, a space of 0.200" is recommended. Benefit of this is it ensures that the test pad will have a probe assigned to it.
Test PAD
Tooling Hole
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19.1.13
As shown in below Figure, the minimum clearance, D, required between a test pad and Through-hole device lead is 0.125".
Test PAD
D Minimum test pad to thru-hole device lead clearance 19.1.14 Test Pad to high components
The minimum clearance required between a test pad and a high component (> 0.2") is 0.200". Edge of a gold finger to PTH test pad As shown in below Figure, the minimum spacing between edge of gold finger and PTH test pad is 0.040" however a spacing of 0.050" is recommended.
D Trace
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19.1.15
PART TYPE
BOARD SIDES
NOTES
0.762mm (0.030")
Includes IPC component placement acceptability, ICT probe radius, and ICT probing accuracy. Special test fixture features may be required. Consult for further details. Adequate clearance critical for topside probes and fixture hold-downs, which may collide with tail components when the fixture lid is closed. Assumes heat sink placement tolerance=+/0.762mm (+/-0.030"). Special test fixture features may be required. Consult for further details. Adequate clearance critical for topside probes and fixture hold-downs, which may collide with tall components when the fixture lid is closed.
Bottom Tall component (height> 7.62mm (0.300")) (Primary probe side) Top (Secondary probe side) Bottom (Primary probe side) Top (Secondary probe side) Board Edge Tooling Hole Edge Non-tooling Hole Edge Both Both Both
1.905mm (0.075")
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CAD Tool
Cadence Allegro
<job name>.cad or <job name>.val Needs to run an extraction script (CDS2FAB) to extract the ASCII output.
MENTOR ASCII File Components file Nets File ASCII Parts file Wires (traces) file
Zuken-redac
<job name>.udf ASCII layout file <job name>.bsf ASCII technology file (layer count, units, etc.) <job name>.mdf ASCII representation of the footprints used in the design (package description file). file (layer count, units, etc.). <job name>.ccf file is the ASCII netlist.
<job_name>.asc
In addition to the ASCII CAD output, the following supplementary information required: 1) Schematic 2) BOM 3) NC drills 4) Fabrication drawing 5) Assembly drawing
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Guideline: Enable, Set, Reset, Clear, and tri-state control pins must not be tied directly to a power or ground rail. As shown in below figure, this can be achieved by using individual pullup/pull-down resistors. The value of the resistor depends on the power line the resistor is place and the capability of the system, the value of resistor will be calculated with the following formula V=RI Where V is the power line tied to the resistor and I is the maximum current the in circuit system can handle. Benefit: Control pins that are not constrained to power or ground allow easy disabling.
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Preferred way to disable clocks Preferred LOGIC CIRCUITS ctl vcc gnd OSC VCC
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19.3.10
Tri-State Control Pin Guideline: All device outputs must be tri-stateable by a single dedicated tri-state control pin without using the JTAG port. Benefit: Place the device in a high impedance state to allow in-circuit testing of neighboring devices.
19.3.11
Pass-Through Mode
Guideline: As shown in the below figure, a pass-through mode should be designed into the device that allows signals to pass directly from input pins to outputs using minimal test vectors. Benefit: Pass through mode allows pin fault coverage to be obtained easily for device inputs and outputs.
Example of a pass-through mode designed into an FPGA (This specific architecture uses a 4-to-1 mux scheme to pass input signals to output pins in only a few vectors).
19.3.12
Guideline: Use an ID and Rev code. Benefit: The ID and REV code features enable verification of the proper revision and differentiation of similar devices.
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Example of using OR-inputs and muxed outputs for testability of digital signals 19.4.2 Analog Testability
Interpolator DAC Pin Guideline: For interpolators bring the DAC output to a pin and provide a test point. Benefit: Bringing the DAC output to a pin will provide allowances to perform DAC functionality testing at the board level.
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Benefit: Place the device in a high impedance state to allow in-circuit testing of neighboring devices.
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Number of Nodes = 1203 / 32 = 37.6 1.0 Amps = + 01 Number of Supplies = + 02 Number of nodes = + 38 Total = 44
We recommend that an additional 10% be added to the above total to help resolve possible fixturing accessibility issues. Notes: There are 3 problems that result from not having enough ground probes connected to the board. They are: Power supplies may drop out of regulation. Ground bounce may appear between the board and the system. The quality of high-speed digital signals is affected.
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The tradeoffs to be made regarding component mounting must be considered early in design. Through-hole components are mostly mounted on the side opposite to that which comes into contact with the solder. Automatic insertion techniques are preferred, so rules for these conditions should be taken into account when arranging through-hole parts. These rules include appropriate clearances for the insertion heads of the automatic equipment, and having sufficient clearance between the lead diameter and the components hold used for attachment and electrical connection. The orientation of the components is also important. This includes the direction in which the components are lined up electrically with respect to the polarity of polarized components to one another and usually with respect to the board edges. In addition, uniform component orientation, i.e. all pin #1s located at the lower left, reduces machine cycle time, thus controlling cost during the assembly operation. The edge of the board becomes the design envelope. Except for connectors, components should not extend over the edge of the board or interfere with board mounting. Design for Assembly (DFA) principles dictate that the designer also know how the assembly will be manufactured. Automated techniques require that standard assembly panels be used to maximize the use and the efficiency of the equipment. Special fixtures can accommodate any shape, however, these fixtures add unnecessary cost to the assembly process. Thus the board perimeter at LMC (least material condition) should be the boundary that no component, at MMC (maximum material condition), extends beyond. Assembly equipment limitations must be recognized early in the design process. Mounting rails for the automatic machines may require additional clearance. All requirements should be documented on the assembly drawing. There are many other parameters that must be considered for component mounting; component body centering, mounting over conductive areas, clearance between components, and physical support are just a few. When designing mixed assemblies that include standard SMT, fine pitch, BGA and CSP parts along with through-hole parts the designer must have close contact with the assembly manufacturing representative to ensure an assembly doesnt require workarounds of the process being used by the manufacturer.
Confidential
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Another element of through-hole component mounting that must be considered is the lead clinching requirement. Is it allowed? Is it required? Will it interfere with the surface mount parts? Sometimes it is left to the discretion of the assembly manufacturer. If the requirements are restrictive they should be indicated on the assembly drawing. The designer should also be knowledgeable of electrical test requirements. Test point lands must be established before the design starts.
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Last, but not least, is the relationship between the hole size and the lead diameter. In general, automated assembly requires a slightly larger hole than manual techniques. The larger hole is intended to account for the differences in machine accuracy versus printed board hole location accuracy. Some companies provide additional targets called Fiducials to compensate for hole to machine location mismatch. Other systems require that the hole is oversize from what is could be with manual insertion. But, it is important that the hole diameter should no exceed the lead diameter too much. If this occurs the solder might not stay in plated-through or unsupported hole. The maximum for automated attachment is usually 0.7mm (0.028) larger than the lead. Surface mounting (SMT) is the process of electrically connecting components to the surface of a conductive pattern that does not utilize component holes. The process requires placing the components on the pattern and attaching them using solder. The attachment process can take a variety of forms but fall into two distinct groups; those where solder is added to the joint and those where existing solder (tin and lead) is reflowed. The differences between manual and automatic placement depends a great deal on the method of attachment. Manual placement has its limitations in speed and accuracy (even though some operators have excellent skills in positioning and hand soldering very small parts or leads to the surface of the printed board). To get started in SMT many companies first experimented with manual techniques. They positioned components into a location and added the solder with a fine tip soldering iron. As the parts became more exotic or wave soldered, they used a small dot of adhesive to secure the part before soldering. So the process was one of positioning and soldering. If the solder was already on the land in the form of solder paste or a solid solder dot, the manual technique was to use a hot air device which reflowed the solder. This hot air technique is currently used in many assembly operations to remove and replace defective parts. It is important to know the methods of attachment in order to take full advantage of the placement technology. Adding solder is done manually with solder paste dispensers (solder dot), or solder wire that contains the flux. Solder is also added automatically by: Sending the board through a wave solder machine where a rotating solder wave or dual waves comes into contact with the components and the board. Drag soldering where the parts are brought into contact with a stagnant pool of hot solder. Reflow soldering requires that solder is on the land prior to component placement. Following component placement, the board must be exposed to a heat source in order to get the solder to liquefy or reflow. Techniques include hot air, vapor phase, infra-red, or a combination of these. The reflow may be accomplished in a normal or inert oven environment. A blanket or nitrogen gas has been used for the tin/lead reflow process. The technique varies for the higher temperature lead free alloy, and depends on the paste composition.
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Pin in Paste is a process where solder paste is deposited on a through-hole land pattern prior to the component being inserted. The volume of paste is critical so that it fills the plated-through hole when the assembly is submitted to reflow. Solid Solder Deposition, or solder bumping, is another technique where the solder is added into a mask opening, reflowed and flatted. The solder bump is coated with flux which holds the component in place during the reflow process.
Automatic component placement is performed by machine that pick up parts from reels of tape, trays, or cassettes, hence the name pick-and-place. The placement is very fast and in most instances, very accurate provided that the board or panel is properly registered to the machine origin. The fastest machines are those that place discrete resistors and capacitors. These are called chip shooters. They place the parts into solder paste that is already on the board, or glue them on the side intended to go through the wave. Most of these machines use a vacuum pick-up so the heads do not require any special added clearance. However, some components require electrical test before they are placed and the pick-up tool must make contact with the electrodes of the chip in order to test the part. More complex IC parts that are packaged in a variety of configurations are also placed automatically, though not as fast as the discrete chips. Most require that they are reflowed using solder paste or forms of solid solder already on the land. A few components, for example SOTs and SOICs can tolerate the temperature of wave or drag soldering, and may be reflowed or have the solder added. These components are attached with adhesive to position them. Very complex parts with may leads and small lead pitch require that the machine reorient itself to the exact placement locations. Typically, machines require 2 Fiducials in opposite corners. They are positioned near the fine-pitch part, and an optical TV camera senses their location and repositions the machines memory board and part location.
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48 inches; in Europe and Asia the common sheet size is 1 meter square. The designer should be aware of the board size that the manufacturer of choice uses in production so they will be able to optimize the board to panel yield and cost relationships. There was a time that it was sufficient to simply take the board dimensions, divide them into the fabrication dimensions, and allow sufficient room for borders. The issues are more complex today since many assembly companies do not want to assemble boards in individual format. They also want boards delivered in arrays. The use of the largest panel in board fabrication provides the most effective labor cost per unit area. The industry processes panels. Being able to get twelve boards on a panel instead of six (3 X 4 versus 2 X 3), immediately increases the yield by 100%. The most common panel in the US is 457 X 610mm [18 X 24 inches]. Some of the processing equipment can accommodate larger panels, however, human factors such as strength, reach and control, preclude the use of much larger panels, Borders and margins are usually required and range between 9.5 to 38 mm [0.38 to 1.5 inches]. Tooling holes, coupons, and other manufacturing entities such as serialization or customer control numbers are also contained in the borders of the panel. Separating boards or assembly arrays from the fabrication panel varies depending on the next use of the board, material, the shape and size, and volume of production. Higher volume production requirements utilize punching and blanking dies to excise boards, or assembly arrays, from fabrication panels. Fixturing is relatively expensive and requires careful maintenance to assure good quality board edges. Freshly sharpened blanking dies will generally provide a relatively smooth board edge. However, as the die is used, the board edges tend to roughen with exposed broken fibers. Scoring and routing are two of the most common methods used for excising printed boards or assembly panels. The easiest way to separate the board is to score each side with a diamond grinder and break the boards or panels apart. The board must be square or rectangular, in shape, in order to use scoring and care is required to not have conductors too close to the scored area, as the score wheel is chamfered. It is required to score the board on each side to approximately 1/3 of the thickness. If the boards are routed, an amount should be left between the boards to accommodate the router bit. This is usually 4.8, 5.0 or 6.3 mm [0.19, 0.20, or 0.25 inches]. When boards are routed the edges are usually very smooth. Scoring leaves the edges a bit rough where the remaining board thickness has exposed broken fibers. Assembly arrays also require borders but these are usually related to the conveyor of the assembly machines. The borders also contain tooling holes or Fiducials. Borders are only on opposite sides of the panel where the conveyer grips the panels, however, some material is necessary at the leading and trailing edge where the final board comes close to the panel edge. The relationship of the final board and the two panel concepts must be understood and considered in the design to maximize the manufacturing operations. Some companies find it
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useful to develop a Panelization drawing in order to maintain control of the tooling features of the assembly panel.
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Sequential layer conventions only apply to things that stay with the board. Data Layers for temporary masking, solder paste stencils, hole drilling templates can be numbered in any fashion because, as of this date, there is no industry-accepted consensus standard.
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Overhanging devices and ICT Place overhanging devices/hardware (such as heatsinks that are larger than their corresponding components) on the side opposite to the primary ICT probing side. For example, usually ICT probing is done only on the bottom side of the board. In that case, it would be preferable to place components having overhanging heatsinks on the top side of the board. Wave Soldered SMT Components The component packages detailed here are those that can pass through a full solder wave during assembly, i.e. those that can be placed on the solder side of the board when wave
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soldering will be used. These components are attached to the board with adhesive during the SMT process. Table: Wave Solderable SMT Components
SMT Weight Limits for Side 2 When designing a double-sided reflow board, ensure that components on the bottom side of the board will not fall off during the second reflow cycle. The weight of the component in relation to its solderable surface area determines whether there is enough surface tension to hold the component to the board. Place all components that will fall off on the same side of the board to be assembled during the second SMT pass. Refer to Figure 1 for a graph of package weight limits. Calculate the SMT component weight limit for the B-side as follows:
Note: If the actual weight is greater than the allowable weight, the part WILL fall off. Heat Dissipation It is preferred to have high-power parts (i.e. parts requiring heatsinks) placed on the top-side of the card for better heat dissipation within an enclosed test fixture during board testing. This is especially important if there is no provision of a low-power or sleep mode to prevent excessive heat generation. Parts with Large Variations in Position Parts with > 0.100" variation in body position should be evaluated, as they may interfere with ICT testing. Eliminate/replace these parts, or place on "top" side (Non Probing Side) if possible. Examples of potential problem parts: PTH soldered parts (e.g. parts that float in wave solder), tall parts that may lean over (e.g. standing TO220, PTH capacitors), manually placed or soldered parts, EMI shields, glued heatsinks, and other mechanical hardware. Impact on "probe" side of board is potential interference between part and milled-out fixture, and possible board damage. Impact on "top" side of board is potential interference between part and push
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fingers or other fixturing mechanical parts (including Opens Xpress and TestJet probes), and possible board damage and/or loss of test coverage. Large variations in body position can be more tolerable on the "top" side, if the test fixture is designed for this. General Component Spacing/Orientation Guidelines Component spacings are dictated by three factors: Component placement accuracy. Rework access. Inspection (visual and automated). In order of preference, ensure that: All manually assembled polarized components have the same orientation. All manually assembled components in the same package have the same orientation. All manually assembled components have the same orientation. All components that are polarized have the same orientation. All components with the same package style have the same orientation. All components have the same orientation. In addition: Components may overhang the edge of the PCB, but they may not hang below the plane of the PCB. Components below the plane either restrict card processing and fixturing or make it impossible. Component Distribution Follow these guidelines for component distribution: Distribute components evenly across the board surface to result in a more even thermal profile across the board and to improve solder joint quality. Unpopulated areas of the PCB may be prone to overheat and thermal damage. When possible, keep large and heavy PTH components distributed towards the card edges. This lessens the degree to which the card warps as it travels through the machine. When possible, keep PTH components grouped together. This will: create benefits in tool design, improve speed and accuracy during component insertion, and improve quality and cycle time during soldering processes. Component Spacing Matrix Note: Distances are always from the part or land (whichever is bigger) to the next part or land (whichever is closer). Adjacent Tall Components Because soldering irons are used for most repair operations, orient discrete components, especially ones between two tall TH parts, to allow for soldering iron accessibility.
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Figure. Discrete and Tall Component Orientation In the instances where the spacing matrix is not followed for small SMT components to tall components, one option to allow repair access is to orient discrete components parallel to the tall components. Minimum Distance between Components: For better machine programming, component verification and placement accuracy, rework, cleaning, test, etc. a minimum distance between components must be maintained. The required minimum distance is a function of device profile, shape, orientation, soldering options (reflow, wave, hand soldering), cleaning and overall PCBA configuration. The recommended minimum distance between components for primary or top and secondary or bottom side are provided in Table 1 and Table 2 respectively. Three spacing specifications, namely Preferred, Acceptable, Violation, are provided in both Table 1 & Table 2. Violation: spacing below this limit is a complete violation and can have detrimental effect in the manufacturability, testability or reliability of the product resulting in significant increase in manufacturing cost. Acceptable: any spacing above the violation limit that is expected to offer manufacturing benefits. Generally, manufacturability gains are expected to scale up with larger spacing. Preferred: is the most generous spacing range that generally simplifies manufacturability.
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Table 1. Recommended Minimum Distance between Components on PCB Primary or Top side
NOTES: Distances between components are based on closest features whether it is the component or component land.
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Table 2. Recommended Minimum Distances between secondary side SMT components for wave soldering.
NOTE: * All dimensions in mils * The dimensions listed above for SMT chips refer to the minimum distances between devices to prevent component shadowing during wave soldering. * For double-sided SMT without wave soldering use spacing provided in Table 1. * Do not mount PGA, axial, DIP or other through hole devices on secondary side
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Subsequently, component suppliers can identify the orientation of the parts on the reels by associating the placement of the part on the reel to zero orientations defined in IPC-7351. If pin 1 is at the lower left as defined by the pick and place machine tape and reel, for example, then the component on the reel is rotated 90 counterclockwise from the zero rotation given in IPC7351. Standardizing the orientation of components for the installation and utilization of various packaging methods, such as tubes, trays or tapes and reels, among the variations of automated assembly equipment existing today is outside the scope of this document.
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Figure 1-1 lists the most commonly used parts and their proper zero component rotation.
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Fig.1 Typical Process Flow for Full Surface Mount Type 1b and 2b Surface Mount Technology The process sequence for surface mount with through-hole or pin-in-hole (PIH) component technology is shown in Figure 2. Adhesive is applied and the surface mounted components placed. The adhesive is then cured, and the board is inverted to receive the through-hole component leads automatically or by hand insertion. After lead clinching (if required), and with the through-hole components on top and the surface mount components beneath, the board is typically wave soldered. An alternative sequence is to reverse the initial stages i.e., insert (and clinch) the through-hole components before attaching the surface mounted components and then wave soldering. Finally the assembly may be cleaned, inspected, repaired if necessary, and tested, though not necessarily in that order.
Figure 2 Assembly Process Flow for Two-Side Surface Mount with PIH
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Besides the above-mentioned data sets, the system also requires the following additional information regardless of CAD tools used. In order to create ODB++ intelligence and perform DFA analysis, the following lists the additional information needed: 1) Approved Vendor List (AVL) Manufacturer, Manufacturer part number (mandatory) 2) Bill of Material (BOM) Customer part number, quantity, ref. designators (mandatory)
20.12 REWORK
The repair/rework of surface mount assemblies requires special care in design and practice. Because of the small land geometries, heat applied to the board should be minimized. There are various tools available for removing components. Resistance heating tweezers are usually used for removing surface mounted components. Various types of hot air/gas and IR systems are also used for removing surface mounted components. One of the main issues when using hot air/gas devices is preventing damage to adjacent components. Refer to IPC-7711/21. There are four basic requirements for a successful rework; good printed board design layout, selection
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of the correct rework equipment or tools, sufficient manual skill, and adequate training. Successful removal of large multi-leaded integrated circuit packages involves the use of hot gas or heated electrode tools. Sufficient clearance around the package to permit the re-work is essential. Clearance should be provided completely around the device as identified in the standards as the courtyard manufacturing zone.
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* It is important to allow enough room around components for the rework nozzle for BGA type rework. Further, clearance around components may be required to minimize undesired and adjacent component Reflow. * For component replacement the site must be prepared. There are various replacement site preparation techniques. The most common method involve screen-printing solder paste with a .micro stencil, placing the new part and reflow. A minimum clearance of 0.300. Around the component location may be required for printing and reflow. * For visual inspection and repair accessibility, a maximized view angle and spacing of 0.250 to 0.300 is recommended between high profile components such as PLCCs and ICs as shown in Figure 3
Figure 3 When a large part is too close to a small part, joints cannot be inspected or reworked. * A minimum spacing of 0.050 between chip devices and a minimum clearance of 0.200 between a PTH lead and nearest component body is recommended for repair without damaging adjacent component due to burning or solder splash. * Design ground planes to minimize thermal heat sinking effects. Component leads should not be connected directly to a large ground plane. Instead, device leads should be thermally isolated by using short conductors to ground as shown in Figure 4. Minimizing the time and temperature necessary to repair a defective site reduces the likelihood of damaging the PCB or adjacent components.
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Hot Air Rework Station Hot air rework stations are used to remove & replace large devices such as QFPs & BGAs, but can also be used for smaller devices such as CSPs, connectors, etc. The basic principle of removal & replacement is shown in Figure 5. The board is first pre-heated, to reduce stresses on the board, and a nozzle fitted to the part size is brought down over the component. Hot air or nitrogen is blown through the nozzle to heat the part to the reflow temperature. Once the solder is molten a vacuum nozzle lifts the part from the board completing the cycle. Before a new device is placed, the rework site (where the part was removed from) must be cleaned. This usually involves removal of the excess solder left on the pads followed by application of solder paste prior device placement. The solder paste is usually applied using a micro-stencil. This is a small section of stencil, similar to a screen-printing stencil, with the necessary apertures. The stencil fits over the site area and is manually aligned and solder paste is printed onto the pads
Figure 5: Hot Air Reflow Process It should be noted this method is designed to offer primarily localized heating. However, it is possible that parts close to the part being heated, or on the opposite side of the board, may also reflow and may be displaced or removed by accident
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